wcd937x codec fixes

Merge series from Alexey Klimov <alexey.klimov@linaro.org>:

This sent as RFC because of the following:

- regarding the LO switch patch. I've got info about that from two persons
independently hence not sure what tags to put there and who should be
the author. Please let me know if that needs to be corrected.

- the wcd937x pdm watchdog is a problem for audio playback and needs to be
fixed. The minimal fix would be to at least increase timeout value but
it will still trigger in case of plenty of dbg messages or other
delay-generating things. Unfortunately, I can't test HPHL/R outputs hence
the patch is only for AUX. The other options would be introducing
module parameter for debugging and using HOLD_OFF bit for that or
adding Kconfig option.

Alexey Klimov (2):
  ASoC: codecs: wcd937x: add missing LO Switch control
  ASoC: codecs: wcd937x: relax the AUX PDM watchdog

 sound/soc/codecs/wcd937x.c | 12 ++++++++++--
 sound/soc/codecs/wcd937x.h |  4 ++++
 2 files changed, 14 insertions(+), 2 deletions(-)

--
2.45.2
This commit is contained in:
Mark Brown 2024-10-29 19:18:48 +00:00
commit 2db63e9218
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
2 changed files with 14 additions and 2 deletions

View File

@ -715,12 +715,17 @@ static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
int hph_mode = wcd937x->hph_mode;
u8 val;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
val = WCD937X_DIGITAL_PDM_WD_CTL2_EN |
WCD937X_DIGITAL_PDM_WD_CTL2_TIMEOUT_SEL |
WCD937X_DIGITAL_PDM_WD_CTL2_HOLD_OFF;
snd_soc_component_update_bits(component,
WCD937X_DIGITAL_PDM_WD_CTL2,
BIT(0), BIT(0));
WCD937X_DIGITAL_PDM_WD_CTL2_MASK,
val);
break;
case SND_SOC_DAPM_POST_PMU:
usleep_range(1000, 1010);
@ -741,7 +746,8 @@ static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
hph_mode);
snd_soc_component_update_bits(component,
WCD937X_DIGITAL_PDM_WD_CTL2,
BIT(0), 0x00);
WCD937X_DIGITAL_PDM_WD_CTL2_MASK,
0x00);
break;
}
@ -2049,6 +2055,8 @@ static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
wcd937x_get_swr_port, wcd937x_set_swr_port),
SOC_SINGLE_EXT("HPHR Switch", WCD937X_HPH_R, 0, 1, 0,
wcd937x_get_swr_port, wcd937x_set_swr_port),
SOC_SINGLE_EXT("LO Switch", WCD937X_LO, 0, 1, 0,
wcd937x_get_swr_port, wcd937x_set_swr_port),
SOC_SINGLE_EXT("ADC1 Switch", WCD937X_ADC1, 1, 1, 0,
wcd937x_get_swr_port, wcd937x_set_swr_port),

View File

@ -391,6 +391,10 @@
#define WCD937X_DIGITAL_PDM_WD_CTL0 0x3465
#define WCD937X_DIGITAL_PDM_WD_CTL1 0x3466
#define WCD937X_DIGITAL_PDM_WD_CTL2 0x3467
#define WCD937X_DIGITAL_PDM_WD_CTL2_HOLD_OFF BIT(2)
#define WCD937X_DIGITAL_PDM_WD_CTL2_TIMEOUT_SEL BIT(1)
#define WCD937X_DIGITAL_PDM_WD_CTL2_EN BIT(0)
#define WCD937X_DIGITAL_PDM_WD_CTL2_MASK GENMASK(2, 0)
#define WCD937X_DIGITAL_INTR_MODE 0x346A
#define WCD937X_DIGITAL_INTR_MASK_0 0x346B
#define WCD937X_DIGITAL_INTR_MASK_1 0x346C