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can: sja1000: f81601: add Fintek F81601 support
This patch add support for Fintek PCIE to 2 CAN controller support Signed-off-by: Ji-Ze Hong (Peter Hong) <hpeter+linux_kernel@gmail.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Ji-Ze Hong (Peter Hong)
Marc Kleine-Budde
parent
4dfc39e1b6
commit
2d91fdccad
@ -21,6 +21,16 @@ config CAN_EMS_PCMCIA
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This driver is for the one or two channel CPC-CARD cards from
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EMS Dr. Thomas Wuensche (http://www.ems-wuensche.de).
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config CAN_F81601
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tristate "Fintek F81601 PCIE to 2 CAN Controller"
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depends on PCI
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help
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This driver adds support for Fintek F81601 PCIE to 2 CAN
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Controller. It had internal 24MHz clock source, but it can
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be changed by manufacturer. Use modinfo to get usage for
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parameters. Visit http://www.fintek.com.tw to get more
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information.
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config CAN_KVASER_PCI
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tristate "Kvaser PCIcanx and Kvaser PCIcan PCI Cards"
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depends on PCI
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@ -5,6 +5,7 @@
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obj-$(CONFIG_CAN_EMS_PCI) += ems_pci.o
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obj-$(CONFIG_CAN_EMS_PCMCIA) += ems_pcmcia.o
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obj-$(CONFIG_CAN_F81601) += f81601.o
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obj-$(CONFIG_CAN_KVASER_PCI) += kvaser_pci.o
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obj-$(CONFIG_CAN_PEAK_PCI) += peak_pci.o
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obj-$(CONFIG_CAN_PEAK_PCMCIA) += peak_pcmcia.o
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212
drivers/net/can/sja1000/f81601.c
Normal file
212
drivers/net/can/sja1000/f81601.c
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@ -0,0 +1,212 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Fintek F81601 PCIE to 2 CAN controller driver
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*
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* Copyright (C) 2019 Peter Hong <peter_hong@fintek.com.tw>
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* Copyright (C) 2019 Linux Foundation
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/netdevice.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <linux/can/dev.h>
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#include <linux/io.h>
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#include <linux/version.h>
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#include "sja1000.h"
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#define F81601_PCI_MAX_CHAN 2
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#define F81601_DECODE_REG 0x209
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#define F81601_IO_MODE BIT(7)
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#define F81601_MEM_MODE BIT(6)
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#define F81601_CFG_MODE BIT(5)
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#define F81601_CAN2_INTERNAL_CLK BIT(3)
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#define F81601_CAN1_INTERNAL_CLK BIT(2)
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#define F81601_CAN2_EN BIT(1)
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#define F81601_CAN1_EN BIT(0)
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#define F81601_TRAP_REG 0x20a
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#define F81601_CAN2_HAS_EN BIT(4)
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struct f81601_pci_card {
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void __iomem *addr;
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spinlock_t lock; /* use this spin lock only for write access */
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struct pci_dev *dev;
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struct net_device *net_dev[F81601_PCI_MAX_CHAN];
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};
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static const struct pci_device_id f81601_pci_tbl[] = {
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{ PCI_DEVICE(0x1c29, 0x1703) },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(pci, f81601_pci_tbl);
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static bool internal_clk = true;
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module_param(internal_clk, bool, 0444);
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MODULE_PARM_DESC(internal_clk, "Use internal clock, default true (24MHz)");
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static unsigned int external_clk;
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module_param(external_clk, uint, 0444);
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MODULE_PARM_DESC(external_clk, "External clock when internal_clk disabled");
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static u8 f81601_pci_read_reg(const struct sja1000_priv *priv, int port)
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{
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return readb(priv->reg_base + port);
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}
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static void f81601_pci_write_reg(const struct sja1000_priv *priv, int port,
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u8 val)
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{
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struct f81601_pci_card *card = priv->priv;
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unsigned long flags;
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spin_lock_irqsave(&card->lock, flags);
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writeb(val, priv->reg_base + port);
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readb(priv->reg_base);
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spin_unlock_irqrestore(&card->lock, flags);
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}
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static void f81601_pci_remove(struct pci_dev *pdev)
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{
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struct f81601_pci_card *card = pci_get_drvdata(pdev);
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struct net_device *dev;
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int i;
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for (i = 0; i < ARRAY_SIZE(card->net_dev); i++) {
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dev = card->net_dev[i];
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if (!dev)
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continue;
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dev_info(&pdev->dev, "%s: Removing %s\n", __func__, dev->name);
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unregister_sja1000dev(dev);
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free_sja1000dev(dev);
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}
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}
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/* Probe F81601 based device for the SJA1000 chips and register each
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* available CAN channel to SJA1000 Socket-CAN subsystem.
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*/
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static int f81601_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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struct sja1000_priv *priv;
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struct net_device *dev;
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struct f81601_pci_card *card;
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int err, i, count;
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u8 tmp;
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if (pcim_enable_device(pdev) < 0) {
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dev_err(&pdev->dev, "Failed to enable PCI device\n");
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return -ENODEV;
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}
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dev_info(&pdev->dev, "Detected card at slot #%i\n",
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PCI_SLOT(pdev->devfn));
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card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);
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if (!card)
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return -ENOMEM;
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card->dev = pdev;
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spin_lock_init(&card->lock);
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pci_set_drvdata(pdev, card);
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tmp = F81601_IO_MODE | F81601_MEM_MODE | F81601_CFG_MODE |
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F81601_CAN2_EN | F81601_CAN1_EN;
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if (internal_clk) {
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tmp |= F81601_CAN2_INTERNAL_CLK | F81601_CAN1_INTERNAL_CLK;
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dev_info(&pdev->dev,
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"F81601 running with internal clock: 24Mhz\n");
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} else {
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dev_info(&pdev->dev,
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"F81601 running with external clock: %dMhz\n",
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external_clk / 1000000);
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}
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pci_write_config_byte(pdev, F81601_DECODE_REG, tmp);
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card->addr = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0));
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if (!card->addr) {
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err = -ENOMEM;
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dev_err(&pdev->dev, "%s: Failed to remap BAR\n", __func__);
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goto failure_cleanup;
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}
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/* read CAN2_HW_EN strap pin to detect how many CANBUS do we have */
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count = ARRAY_SIZE(card->net_dev);
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pci_read_config_byte(pdev, F81601_TRAP_REG, &tmp);
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if (!(tmp & F81601_CAN2_HAS_EN))
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count = 1;
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for (i = 0; i < count; i++) {
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dev = alloc_sja1000dev(0);
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if (!dev) {
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err = -ENOMEM;
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goto failure_cleanup;
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}
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priv = netdev_priv(dev);
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priv->priv = card;
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priv->irq_flags = IRQF_SHARED;
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priv->reg_base = card->addr + 0x80 * i;
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priv->read_reg = f81601_pci_read_reg;
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priv->write_reg = f81601_pci_write_reg;
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if (internal_clk)
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priv->can.clock.freq = 24000000 / 2;
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else
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priv->can.clock.freq = external_clk / 2;
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priv->ocr = OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL;
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priv->cdr = CDR_CBP;
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SET_NETDEV_DEV(dev, &pdev->dev);
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dev->dev_id = i;
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dev->irq = pdev->irq;
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/* Register SJA1000 device */
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err = register_sja1000dev(dev);
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if (err) {
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dev_err(&pdev->dev,
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"%s: Registering device failed: %x\n", __func__,
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err);
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free_sja1000dev(dev);
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goto failure_cleanup;
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}
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card->net_dev[i] = dev;
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dev_info(&pdev->dev, "Channel #%d, %s at 0x%p, irq %d\n", i,
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dev->name, priv->reg_base, dev->irq);
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}
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return 0;
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failure_cleanup:
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dev_err(&pdev->dev, "%s: failed: %d. Cleaning Up.\n", __func__, err);
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f81601_pci_remove(pdev);
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return err;
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}
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static struct pci_driver f81601_pci_driver = {
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.name = "f81601",
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.id_table = f81601_pci_tbl,
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.probe = f81601_pci_probe,
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.remove = f81601_pci_remove,
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};
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MODULE_DESCRIPTION("Fintek F81601 PCIE to 2 CANBUS adaptor driver");
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MODULE_AUTHOR("Peter Hong <peter_hong@fintek.com.tw>");
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MODULE_LICENSE("GPL v2");
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module_pci_driver(f81601_pci_driver);
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