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Merge remote-tracking branch 'jwb/next' into next

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This commit is contained in:
Benjamin Herrenschmidt 2012-03-21 10:56:00 +11:00
commit 2d87e06e74
6 changed files with 199 additions and 5 deletions
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2
MAINTAINERS
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@ -4034,7 +4034,7 @@ M: Josh Boyer <jwboyer@gmail.com>
M: Matt Porter <mporter@kernel.crashing.org>
W: http://www.penguinppc.org/
L: linuxppc-dev@lists.ozlabs.org
T: git git://git.infradead.org/users/jwboyer/powerpc-4xx.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git
S: Maintained
F: arch/powerpc/platforms/40x/
F: arch/powerpc/platforms/44x/

127
arch/powerpc/boot/dts/bluestone.dts
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@ -33,7 +33,7 @@
aliases {
ethernet0 = &EMAC0;
serial0 = &UART0;
//serial1 = &UART1; --gcl missing UART1 label
serial1 = &UART1;
};
cpus {
@ -52,7 +52,7 @@
d-cache-size = <32768>;
dcr-controller;
dcr-access-method = "native";
//next-level-cache = <&L2C0>; --gcl missing L2C0 label
next-level-cache = <&L2C0>;
};
};
@ -117,6 +117,16 @@
dcr-reg = <0x00c 0x002>;
};
L2C0: l2c {
compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
dcr-reg = <0x020 0x008
0x030 0x008>;
cache-line-size = <32>;
cache-size = <262144>;
interrupt-parent = <&UIC1>;
interrupts = <11 1>;
};
plb {
compatible = "ibm,plb4";
#address-cells = <2>;
@ -182,6 +192,53 @@
reg = <0x001a0000 0x00060000>;
};
};
ndfc@1,0 {
compatible = "ibm,ndfc";
reg = <0x00000003 0x00000000 0x00002000>;
ccr = <0x00001000>;
bank-settings = <0x80002222>;
#address-cells = <1>;
#size-cells = <1>;
/* 2Gb Nand Flash */
nand {
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "firmware";
reg = <0x00000000 0x00C00000>;
};
partition@c00000 {
label = "environment";
reg = <0x00C00000 0x00B00000>;
};
partition@1700000 {
label = "kernel";
reg = <0x01700000 0x00E00000>;
};
partition@2500000 {
label = "root";
reg = <0x02500000 0x08200000>;
};
partition@a700000 {
label = "device-tree";
reg = <0x0A700000 0x00B00000>;
};
partition@b200000 {
label = "config";
reg = <0x0B200000 0x00D00000>;
};
partition@bf00000 {
label = "diag";
reg = <0x0BF00000 0x00C00000>;
};
partition@cb00000 {
label = "vendor";
reg = <0x0CB00000 0x3500000>;
};
};
};
};
UART0: serial@ef600300 {
@ -195,11 +252,36 @@
interrupts = <0x1 0x4>;
};
UART1: serial@ef600400 {
device_type = "serial";
compatible = "ns16550";
reg = <0xef600400 0x00000008>;
virtual-reg = <0xef600400>;
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>; /* Filled in by U-Boot */
interrupt-parent = <&UIC0>;
interrupts = <0x1 0x4>;
};
IIC0: i2c@ef600700 {
compatible = "ibm,iic";
reg = <0xef600700 0x00000014>;
interrupt-parent = <&UIC0>;
interrupts = <0x2 0x4>;
#address-cells = <1>;
#size-cells = <0>;
rtc@68 {
compatible = "stm,m41t80";
reg = <0x68>;
interrupt-parent = <&UIC0>;
interrupts = <0x9 0x8>;
};
sttm@4C {
compatible = "adm,adm1032";
reg = <0x4C>;
interrupt-parent = <&UIC1>;
interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */
};
};
IIC1: i2c@ef600800 {
@ -250,5 +332,46 @@
};
};
PCIE0: pciex@d00000000 {
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
primary;
port = <0x0>; /* port number */
reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
0x0000000c 0x08010000 0x00001000>; /* Registers */
dcr-reg = <0x100 0x020>;
sdr-base = <0x300>;
/* Outbound ranges, one memory and one IO,
* later cannot be changed
*/
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
/* Inbound 2GB range starting at 0 */
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
/* This drives busses 40 to 0x7f */
bus-range = <0x40 0x7f>;
/* Legacy interrupts (note the weird polarity, the bridge seems
* to invert PCIe legacy interrupts).
* We are de-swizzling here because the numbers are actually for
* port of the root complex virtual P2P bridge. But I want
* to avoid putting a node for it in the tree, so the numbers
* below are basically de-swizzled numbers.
* The real slot is on idsel 0, so the swizzling is 1:1
*/
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <
0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
};
};
};

2
arch/powerpc/kernel/cputable.c
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@ -1816,7 +1816,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.platform = "ppc440",
},
{ /* 464 in APM821xx */
.pvr_mask = 0xffffff00,
.pvr_mask = 0xfffffff0,
.pvr_value = 0x12C41C80,
.cpu_name = "APM821XX",
.cpu_features = CPU_FTRS_44X,

1
arch/powerpc/platforms/44x/Kconfig
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@ -23,6 +23,7 @@ config BLUESTONE
default n
select PPC44x_SIMPLE
select APM821xx
select PPC4xx_PCI_EXPRESS
select IBM_EMAC_RGMII
help
This option enables support for the APM APM821xx Evaluation board.

2
arch/powerpc/platforms/44x/ppc44x_simple.c
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@ -52,7 +52,7 @@ machine_device_initcall(ppc44x_simple, ppc44x_device_probe);
static char *board[] __initdata = {
"amcc,arches",
"amcc,bamboo",
"amcc,bluestone",
"apm,bluestone",
"amcc,glacier",
"ibm,ebony",
"amcc,eiger",

70
arch/powerpc/sysdev/ppc4xx_pci.c
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@ -1050,6 +1050,74 @@ static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
.check_link = ppc4xx_pciex_check_link_sdr,
};
static int __init apm821xx_pciex_core_init(struct device_node *np)
{
/* Return the number of pcie port */
return 1;
}
static int apm821xx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
{
u32 val;
/*
* Do a software reset on PCIe ports.
* This code is to fix the issue that pci drivers doesn't re-assign
* bus number for PCIE devices after Uboot
* scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
* PT quad port, SAS LSI 1064E)
*/
mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
mdelay(10);
if (port->endpoint)
val = PTYPE_LEGACY_ENDPOINT << 20;
else
val = PTYPE_ROOT_PORT << 20;
val |= LNKW_X1 << 12;
mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
mdelay(50);
mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
/* Poll for PHY reset */
val = PESDR0_460EX_RSTSTA - port->sdr_base;
if (ppc4xx_pciex_wait_on_sdr(port, val, 0x1, 1, 100)) {
printk(KERN_WARNING "%s: PCIE: Can't reset PHY\n", __func__);
return -EBUSY;
} else {
mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
(mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
PESDRx_RCSSET_RSTPYN);
port->has_ibpre = 1;
return 0;
}
}
static struct ppc4xx_pciex_hwops apm821xx_pcie_hwops __initdata = {
.want_sdr = true,
.core_init = apm821xx_pciex_core_init,
.port_init_hw = apm821xx_pciex_init_port_hw,
.setup_utl = ppc460ex_pciex_init_utl,
.check_link = ppc4xx_pciex_check_link_sdr,
};
static int __init ppc460sx_pciex_core_init(struct device_node *np)
{
/* HSS drive amplitude */
@ -1362,6 +1430,8 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
if (of_device_is_compatible(np, "ibm,plb-pciex-460sx"))
ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops;
if (of_device_is_compatible(np, "ibm,plb-pciex-apm821xx"))
ppc4xx_pciex_hwops = &apm821xx_pcie_hwops;
#endif /* CONFIG_44x */
#ifdef CONFIG_40x
if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))