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mfd: dbx500-prcmu: Drop DSI pll clock functions

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The DSI PLLs are handled by the generic clock framework
since ages, this code is completely unused and misleading.
Delete it.

Cc: Stephan Gerhold <stephan@gerhold.net>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Linus Walleij 2019-12-28 23:26:15 +01:00 committed by Lee Jones
parent f41810921b
commit 2cce09eb11
3 changed files with 0 additions and 98 deletions
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66
drivers/mfd/db8500-prcmu.c
View File

@ -542,72 +542,6 @@ static struct dsiescclk dsiescclk[3] = {
}
};
/*
* Used by MCDE to setup all necessary PRCMU registers
*/
#define PRCMU_RESET_DSIPLL 0x00004000
#define PRCMU_UNCLAMP_DSIPLL 0x00400800
#define PRCMU_CLK_PLL_DIV_SHIFT 0
#define PRCMU_CLK_PLL_SW_SHIFT 5
#define PRCMU_CLK_38 (1 << 9)
#define PRCMU_CLK_38_SRC (1 << 10)
#define PRCMU_CLK_38_DIV (1 << 11)
/* D=101, N=1, R=4, SELDIV2=0 */
#define PRCMU_PLLDSI_FREQ_SETTING 0x00040165
#define PRCMU_ENABLE_PLLDSI 0x00000001
#define PRCMU_DISABLE_PLLDSI 0x00000000
#define PRCMU_RELEASE_RESET_DSS 0x0000400C
#define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202
/* ESC clk, div0=1, div1=1, div2=3 */
#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101
#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101
#define PRCMU_DSI_RESET_SW 0x00000007
#define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
int db8500_prcmu_enable_dsipll(void)
{
int i;
/* Clear DSIPLL_RESETN */
writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
/* Unclamp DSIPLL in/out */
writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
/* Set DSI PLL FREQ */
writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
/* Enable Escape clocks */
writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
/* Start DSI PLL */
writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
/* Reset DSI PLL */
writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
for (i = 0; i < 10; i++) {
if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
== PRCMU_PLLDSI_LOCKP_LOCKED)
break;
udelay(100);
}
/* Set DSIPLL_RESETN */
writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
return 0;
}
int db8500_prcmu_disable_dsipll(void)
{
/* Disable dsi pll */
writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
/* Disable escapeclock */
writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
return 0;
}
u32 db8500_prcmu_read(unsigned int reg)
{
return readl(prcmu_base + reg);

12
include/linux/mfd/db8500-prcmu.h
View File

@ -525,8 +525,6 @@ u8 db8500_prcmu_get_power_state_result(void);
void db8500_prcmu_enable_wakeups(u32 wakeups);
int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
int db8500_prcmu_request_clock(u8 clock, bool enable);
int db8500_prcmu_disable_dsipll(void);
int db8500_prcmu_enable_dsipll(void);
void db8500_prcmu_config_abb_event_readout(u32 abb_events);
void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
int db8500_prcmu_config_esram0_deep_sleep(u8 state);
@ -681,16 +679,6 @@ static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
return 0;
}
static inline int db8500_prcmu_disable_dsipll(void)
{
return 0;
}
static inline int db8500_prcmu_enable_dsipll(void)
{
return 0;
}
static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
{
return 0;

20
include/linux/mfd/dbx500-prcmu.h
View File

@ -321,16 +321,6 @@ static inline bool prcmu_is_ac_wake_requested(void)
return db8500_prcmu_is_ac_wake_requested();
}
static inline int prcmu_disable_dsipll(void)
{
return db8500_prcmu_disable_dsipll();
}
static inline int prcmu_enable_dsipll(void)
{
return db8500_prcmu_enable_dsipll();
}
static inline int prcmu_config_esram0_deep_sleep(u8 state)
{
return db8500_prcmu_config_esram0_deep_sleep(state);
@ -506,16 +496,6 @@ static inline bool prcmu_is_ac_wake_requested(void)
return false;
}
static inline int prcmu_disable_dsipll(void)
{
return 0;
}
static inline int prcmu_enable_dsipll(void)
{
return 0;
}
static inline int prcmu_config_esram0_deep_sleep(u8 state)
{
return 0;