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pxafb: introduce "struct pxafb_dma_buff" for palette and dma descriptors
Use structure and array for palette buffer and dma descriptors to: 1. better organize code for future expansion like overlays 2. separate palette and dma descriptors from frame buffer Signed-off-by: eric miao <eric.miao@marvell.com> Cc: "Antonino A. Daplas" <adaplas@pol.net> Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
eric miao
Linus Torvalds
parent
ce4fb7b892
commit
2c42dd8ebd
@ -361,7 +361,6 @@ static int pxafb_set_par(struct fb_info *info)
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{
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struct pxafb_info *fbi = (struct pxafb_info *)info;
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struct fb_var_screeninfo *var = &info->var;
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unsigned long palette_mem_size;
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if (var->bits_per_pixel == 16)
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fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
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@ -384,13 +383,7 @@ static int pxafb_set_par(struct fb_info *info)
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fbi->palette_size = var->bits_per_pixel == 1 ?
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4 : 1 << var->bits_per_pixel;
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if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
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palette_mem_size = fbi->palette_size * sizeof(u16);
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else
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palette_mem_size = fbi->palette_size * sizeof(u32);
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fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
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fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
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fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
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/*
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* Set (any) board control register to handle new color depth
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@ -546,6 +539,48 @@ unsigned long pxafb_get_hsync_time(struct device *dev)
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}
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EXPORT_SYMBOL(pxafb_get_hsync_time);
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static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
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unsigned int offset, size_t size)
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{
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struct pxafb_dma_descriptor *dma_desc, *pal_desc;
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unsigned int dma_desc_off, pal_desc_off;
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if (dma < 0 || dma >= DMA_MAX)
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return -EINVAL;
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dma_desc = &fbi->dma_buff->dma_desc[dma];
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dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
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dma_desc->fsadr = fbi->screen_dma + offset;
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dma_desc->fidr = 0;
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dma_desc->ldcmd = size;
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if (pal < 0 || pal >= PAL_MAX) {
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dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
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fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
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} else {
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pal_desc = &fbi->dma_buff->pal_desc[dma];
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pal_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[pal]);
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pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
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pal_desc->fidr = 0;
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if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
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pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
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else
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pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
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pal_desc->ldcmd |= LDCMD_PAL;
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/* flip back and forth between palette and frame buffer */
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pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
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dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
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fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
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}
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return 0;
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}
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/*
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* pxafb_activate_var():
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* Configures LCD Controller based on entries in var parameter.
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@ -557,6 +592,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
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struct pxafb_lcd_reg new_regs;
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u_long flags;
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u_int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
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size_t nbytes;
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#if DEBUG_VAR
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if (var->xres < 16 || var->xres > 1024)
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@ -634,54 +670,15 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
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/* Update shadow copy atomically */
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local_irq_save(flags);
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/* setup dma descriptors */
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fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)
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((unsigned int)fbi->palette_cpu - 3*16);
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fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)
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((unsigned int)fbi->palette_cpu - 2*16);
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fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)
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((unsigned int)fbi->palette_cpu - 1*16);
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nbytes = lines_per_panel * fbi->fb.fix.line_length;
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fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16;
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fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16;
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fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16;
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if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
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setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
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#define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length)
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/* populate descriptors */
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fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma;
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fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL;
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fbi->dmadesc_fblow_cpu->fidr = 0;
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fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL;
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fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */
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fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma;
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fbi->dmadesc_fbhigh_cpu->fidr = 0;
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fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL;
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fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma;
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fbi->dmadesc_palette_cpu->fidr = 0;
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if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
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fbi->dmadesc_palette_cpu->ldcmd = fbi->palette_size *
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sizeof(u16);
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if (var->bits_per_pixel >= 16)
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setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
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else
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fbi->dmadesc_palette_cpu->ldcmd = fbi->palette_size *
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sizeof(u32);
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fbi->dmadesc_palette_cpu->ldcmd |= LDCMD_PAL;
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if (var->bits_per_pixel == 16) {
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/* palette shouldn't be loaded in true-color mode */
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fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
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fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */
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/* init it to something, even though we won't be using it */
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fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma;
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} else {
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/* flips back and forth between pal and fbhigh */
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fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
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fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma;
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fbi->fdadr0 = fbi->dmadesc_palette_dma;
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}
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setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
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fbi->reg_lccr0 = new_regs.lccr0;
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fbi->reg_lccr1 = new_regs.lccr1;
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@ -701,8 +698,8 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
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(__raw_readl(fbi->mmio_base + LCCR1) != fbi->reg_lccr1) ||
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(__raw_readl(fbi->mmio_base + LCCR2) != fbi->reg_lccr2) ||
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(__raw_readl(fbi->mmio_base + LCCR3) != fbi->reg_lccr3) ||
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(__raw_readl(fbi->mmio_base + FDADR0) != fbi->fdadr0) ||
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(__raw_readl(fbi->mmio_base + FDADR1) != fbi->fdadr1))
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(__raw_readl(fbi->mmio_base + FDADR0) != fbi->fdadr[0]) ||
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(__raw_readl(fbi->mmio_base + FDADR1) != fbi->fdadr[1]))
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pxafb_schedule_work(fbi, C_REENABLE);
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return 0;
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@ -777,8 +774,8 @@ static void pxafb_setup_gpio(struct pxafb_info *fbi)
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static void pxafb_enable_controller(struct pxafb_info *fbi)
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{
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pr_debug("pxafb: Enabling LCD controller\n");
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pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0);
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pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1);
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pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
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pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
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pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
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pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
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pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
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@ -793,8 +790,8 @@ static void pxafb_enable_controller(struct pxafb_info *fbi)
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__raw_writel(fbi->reg_lccr1, fbi->mmio_base + LCCR1);
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__raw_writel(fbi->reg_lccr0 & ~LCCR0_ENB, fbi->mmio_base + LCCR0);
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__raw_writel(fbi->fdadr0, fbi->mmio_base + FDADR0);
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__raw_writel(fbi->fdadr1, fbi->mmio_base + FDADR1);
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__raw_writel(fbi->fdadr[0], fbi->mmio_base + FDADR0);
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__raw_writel(fbi->fdadr[1], fbi->mmio_base + FDADR1);
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__raw_writel(fbi->reg_lccr0 | LCCR0_ENB, fbi->mmio_base + LCCR0);
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}
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@ -1038,8 +1035,6 @@ static int pxafb_resume(struct platform_device *dev)
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*/
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static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
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{
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u_long palette_mem_size;
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/*
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* We reserve one page for the palette, plus the size
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* of the framebuffer.
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@ -1062,14 +1057,9 @@ static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
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fbi->fb.fix.smem_start = fbi->screen_dma;
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fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
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if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
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palette_mem_size = fbi->palette_size * sizeof(u16);
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else
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palette_mem_size = fbi->palette_size * sizeof(u32);
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fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE
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- palette_mem_size);
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fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
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fbi->dma_buff = (void *)fbi->map_cpu;
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fbi->dma_buff_phys = fbi->map_dma;
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fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
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}
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return fbi->map_cpu ? 0 : -ENOMEM;
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@ -37,6 +37,36 @@ struct pxafb_dma_descriptor {
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unsigned int ldcmd;
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};
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enum {
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PAL_NONE = -1,
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PAL_BASE = 0,
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PAL_OV1 = 1,
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PAL_OV2 = 2,
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PAL_MAX,
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};
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enum {
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DMA_BASE = 0,
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DMA_UPPER = 0,
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DMA_LOWER = 1,
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DMA_OV1 = 1,
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DMA_OV2_Y = 2,
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DMA_OV2_Cb = 3,
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DMA_OV2_Cr = 4,
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DMA_CURSOR = 5,
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DMA_CMD = 6,
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DMA_MAX,
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};
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/* maximum palette size - 256 entries, each 4 bytes long */
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#define PALETTE_SIZE (256 * 4)
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struct pxafb_dma_buff {
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unsigned char palette[PAL_MAX * PALETTE_SIZE];
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struct pxafb_dma_descriptor pal_desc[PAL_MAX];
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struct pxafb_dma_descriptor dma_desc[DMA_MAX];
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};
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struct pxafb_info {
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struct fb_info fb;
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struct device *dev;
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@ -44,6 +74,10 @@ struct pxafb_info {
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void __iomem *mmio_base;
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struct pxafb_dma_buff *dma_buff;
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dma_addr_t dma_buff_phys;
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dma_addr_t fdadr[DMA_MAX];
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/*
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* These are the addresses we mapped
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* the framebuffer memory region to.
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@ -57,20 +91,8 @@ struct pxafb_info {
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u_char * screen_cpu; /* virtual address of frame buffer */
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dma_addr_t screen_dma; /* physical address of frame buffer */
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u16 * palette_cpu; /* virtual address of palette memory */
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dma_addr_t palette_dma; /* physical address of palette memory */
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u_int palette_size;
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/* DMA descriptors */
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struct pxafb_dma_descriptor * dmadesc_fblow_cpu;
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dma_addr_t dmadesc_fblow_dma;
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struct pxafb_dma_descriptor * dmadesc_fbhigh_cpu;
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dma_addr_t dmadesc_fbhigh_dma;
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struct pxafb_dma_descriptor * dmadesc_palette_cpu;
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dma_addr_t dmadesc_palette_dma;
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dma_addr_t fdadr0;
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dma_addr_t fdadr1;
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u_int lccr0;
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u_int lccr3;
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u_int lccr4;
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