From 2c1966af073c3469e886e8f4c4c83403fe2ac857 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Tue, 28 Apr 2020 20:03:02 +0300 Subject: [PATCH] interconnect: imx: Add platform driver for imx8mm Add a platform driver for the i.MX8MM SoC describing bus topology. Bandwidth adjustments is currently only supported on the DDRC and main NOC. Scaling for the vpu/gpu/display NICs could be added in the future. Signed-off-by: Alexandre Bailon Signed-off-by: Leonard Crestez Link: https://lore.kernel.org/r/b14eef179dbd837a486619724b8033490f49db72.1586174566.git.leonard.crestez@nxp.com Signed-off-by: Georgi Djakov --- drivers/interconnect/imx/Kconfig | 4 + drivers/interconnect/imx/Makefile | 2 + drivers/interconnect/imx/imx8mm.c | 105 ++++++++++++++++++++++ include/dt-bindings/interconnect/imx8mm.h | 50 +++++++++++ 4 files changed, 161 insertions(+) create mode 100644 drivers/interconnect/imx/imx8mm.c create mode 100644 include/dt-bindings/interconnect/imx8mm.h diff --git a/drivers/interconnect/imx/Kconfig b/drivers/interconnect/imx/Kconfig index f39336f8d603..2cd4fad4976a 100644 --- a/drivers/interconnect/imx/Kconfig +++ b/drivers/interconnect/imx/Kconfig @@ -3,3 +3,7 @@ config INTERCONNECT_IMX depends on ARCH_MXC || COMPILE_TEST help Generic interconnect drivers for i.MX SOCs + +config INTERCONNECT_IMX8MM + tristate "i.MX8MM interconnect driver" + depends on INTERCONNECT_IMX diff --git a/drivers/interconnect/imx/Makefile b/drivers/interconnect/imx/Makefile index 86ae0bd28d8c..c234e5d3dfd1 100644 --- a/drivers/interconnect/imx/Makefile +++ b/drivers/interconnect/imx/Makefile @@ -1,3 +1,5 @@ imx-interconnect-objs := imx.o +imx8mm-interconnect-objs := imx8mm.o obj-$(CONFIG_INTERCONNECT_IMX) += imx-interconnect.o +obj-$(CONFIG_INTERCONNECT_IMX8MM) += imx8mm-interconnect.o diff --git a/drivers/interconnect/imx/imx8mm.c b/drivers/interconnect/imx/imx8mm.c new file mode 100644 index 000000000000..1083490bb391 --- /dev/null +++ b/drivers/interconnect/imx/imx8mm.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Interconnect framework driver for i.MX8MM SoC + * + * Copyright (c) 2019, BayLibre + * Copyright (c) 2019-2020, NXP + * Author: Alexandre Bailon + * Author: Leonard Crestez + */ + +#include +#include +#include + +#include "imx.h" + +static const struct imx_icc_node_adj_desc imx8mm_dram_adj = { + .bw_mul = 1, + .bw_div = 16, + .phandle_name = "fsl,ddrc", +}; + +static const struct imx_icc_node_adj_desc imx8mm_noc_adj = { + .bw_mul = 1, + .bw_div = 16, + .main_noc = true, +}; + +/* + * Describe bus masters, slaves and connections between them + * + * This is a simplified subset of the bus diagram, there are several other + * PL301 nics which are skipped/merged into PL301_MAIN + */ +static struct imx_icc_node_desc nodes[] = { + DEFINE_BUS_INTERCONNECT("NOC", IMX8MM_ICN_NOC, &imx8mm_noc_adj, + IMX8MM_ICS_DRAM, IMX8MM_ICN_MAIN), + + DEFINE_BUS_SLAVE("DRAM", IMX8MM_ICS_DRAM, &imx8mm_dram_adj), + DEFINE_BUS_SLAVE("OCRAM", IMX8MM_ICS_OCRAM, NULL), + DEFINE_BUS_MASTER("A53", IMX8MM_ICM_A53, IMX8MM_ICN_NOC), + + /* VPUMIX */ + DEFINE_BUS_MASTER("VPU H1", IMX8MM_ICM_VPU_H1, IMX8MM_ICN_VIDEO), + DEFINE_BUS_MASTER("VPU G1", IMX8MM_ICM_VPU_G1, IMX8MM_ICN_VIDEO), + DEFINE_BUS_MASTER("VPU G2", IMX8MM_ICM_VPU_G2, IMX8MM_ICN_VIDEO), + DEFINE_BUS_INTERCONNECT("PL301_VIDEO", IMX8MM_ICN_VIDEO, NULL, IMX8MM_ICN_NOC), + + /* GPUMIX */ + DEFINE_BUS_MASTER("GPU 2D", IMX8MM_ICM_GPU2D, IMX8MM_ICN_GPU), + DEFINE_BUS_MASTER("GPU 3D", IMX8MM_ICM_GPU3D, IMX8MM_ICN_GPU), + DEFINE_BUS_INTERCONNECT("PL301_GPU", IMX8MM_ICN_GPU, NULL, IMX8MM_ICN_NOC), + + /* DISPLAYMIX */ + DEFINE_BUS_MASTER("CSI", IMX8MM_ICM_CSI, IMX8MM_ICN_MIPI), + DEFINE_BUS_MASTER("LCDIF", IMX8MM_ICM_LCDIF, IMX8MM_ICN_MIPI), + DEFINE_BUS_INTERCONNECT("PL301_MIPI", IMX8MM_ICN_MIPI, NULL, IMX8MM_ICN_NOC), + + /* HSIO */ + DEFINE_BUS_MASTER("USB1", IMX8MM_ICM_USB1, IMX8MM_ICN_HSIO), + DEFINE_BUS_MASTER("USB2", IMX8MM_ICM_USB2, IMX8MM_ICN_HSIO), + DEFINE_BUS_MASTER("PCIE", IMX8MM_ICM_PCIE, IMX8MM_ICN_HSIO), + DEFINE_BUS_INTERCONNECT("PL301_HSIO", IMX8MM_ICN_HSIO, NULL, IMX8MM_ICN_NOC), + + /* Audio */ + DEFINE_BUS_MASTER("SDMA2", IMX8MM_ICM_SDMA2, IMX8MM_ICN_AUDIO), + DEFINE_BUS_MASTER("SDMA3", IMX8MM_ICM_SDMA3, IMX8MM_ICN_AUDIO), + DEFINE_BUS_INTERCONNECT("PL301_AUDIO", IMX8MM_ICN_AUDIO, NULL, IMX8MM_ICN_MAIN), + + /* Ethernet */ + DEFINE_BUS_MASTER("ENET", IMX8MM_ICM_ENET, IMX8MM_ICN_ENET), + DEFINE_BUS_INTERCONNECT("PL301_ENET", IMX8MM_ICN_ENET, NULL, IMX8MM_ICN_MAIN), + + /* Other */ + DEFINE_BUS_MASTER("SDMA1", IMX8MM_ICM_SDMA1, IMX8MM_ICN_MAIN), + DEFINE_BUS_MASTER("NAND", IMX8MM_ICM_NAND, IMX8MM_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC1", IMX8MM_ICM_USDHC1, IMX8MM_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC2", IMX8MM_ICM_USDHC2, IMX8MM_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC3", IMX8MM_ICM_USDHC3, IMX8MM_ICN_MAIN), + DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MM_ICN_MAIN, NULL, + IMX8MM_ICN_NOC, IMX8MM_ICS_OCRAM), +}; + +static int imx8mm_icc_probe(struct platform_device *pdev) +{ + return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes)); +} + +static int imx8mm_icc_remove(struct platform_device *pdev) +{ + return imx_icc_unregister(pdev); +} + +static struct platform_driver imx8mm_icc_driver = { + .probe = imx8mm_icc_probe, + .remove = imx8mm_icc_remove, + .driver = { + .name = "imx8mm-interconnect", + }, +}; + +module_platform_driver(imx8mm_icc_driver); +MODULE_AUTHOR("Alexandre Bailon "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:imx8mm-interconnect"); diff --git a/include/dt-bindings/interconnect/imx8mm.h b/include/dt-bindings/interconnect/imx8mm.h new file mode 100644 index 000000000000..8f10bb06cb59 --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mm.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019, BayLibre + * Copyright (c) 2019-2020, NXP + * Author: Alexandre Bailon + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MM_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MM_H + +#define IMX8MM_ICN_NOC 1 +#define IMX8MM_ICS_DRAM 2 +#define IMX8MM_ICS_OCRAM 3 +#define IMX8MM_ICM_A53 4 + +#define IMX8MM_ICM_VPU_H1 5 +#define IMX8MM_ICM_VPU_G1 6 +#define IMX8MM_ICM_VPU_G2 7 +#define IMX8MM_ICN_VIDEO 8 + +#define IMX8MM_ICM_GPU2D 9 +#define IMX8MM_ICM_GPU3D 10 +#define IMX8MM_ICN_GPU 11 + +#define IMX8MM_ICM_CSI 12 +#define IMX8MM_ICM_LCDIF 13 +#define IMX8MM_ICN_MIPI 14 + +#define IMX8MM_ICM_USB1 15 +#define IMX8MM_ICM_USB2 16 +#define IMX8MM_ICM_PCIE 17 +#define IMX8MM_ICN_HSIO 18 + +#define IMX8MM_ICM_SDMA2 19 +#define IMX8MM_ICM_SDMA3 20 +#define IMX8MM_ICN_AUDIO 21 + +#define IMX8MM_ICN_ENET 22 +#define IMX8MM_ICM_ENET 23 + +#define IMX8MM_ICN_MAIN 24 +#define IMX8MM_ICM_NAND 25 +#define IMX8MM_ICM_SDMA1 26 +#define IMX8MM_ICM_USDHC1 27 +#define IMX8MM_ICM_USDHC2 28 +#define IMX8MM_ICM_USDHC3 29 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MM_H */