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Merge branch 'for-next/feat_lse128' into for-next/core

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* for-next/feat_lse128:
  : HWCAP for FEAT_LSE128
  kselftest/arm64: add FEAT_LSE128 to hwcap test
  arm64: add FEAT_LSE128 HWCAP
This commit is contained in:
Catalin Marinas 2023-10-26 17:10:07 +01:00
commit 2baca17e6a
7 changed files with 29 additions and 0 deletions
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3
Documentation/arch/arm64/elf_hwcaps.rst
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@ -314,6 +314,9 @@ HWCAP2_SVE_B16B16
HWCAP2_LRCPC3
Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0011.
HWCAP2_LSE128
Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0011.
4. Unused AT_HWCAP bits
-----------------------

1
arch/arm64/include/asm/hwcap.h
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@ -141,6 +141,7 @@
#define KERNEL_HWCAP_HBC __khwcap2_feature(HBC)
#define KERNEL_HWCAP_SVE_B16B16 __khwcap2_feature(SVE_B16B16)
#define KERNEL_HWCAP_LRCPC3 __khwcap2_feature(LRCPC3)
#define KERNEL_HWCAP_LSE128 __khwcap2_feature(LSE128)
/*
* This yields a mask that user programs can use to figure out what

1
arch/arm64/include/uapi/asm/hwcap.h
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@ -106,5 +106,6 @@
#define HWCAP2_HBC (1UL << 44)
#define HWCAP2_SVE_B16B16 (1UL << 45)
#define HWCAP2_LRCPC3 (1UL << 46)
#define HWCAP2_LSE128 (1UL << 47)
#endif /* _UAPI__ASM_HWCAP_H */

1
arch/arm64/kernel/cpufeature.c
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@ -2746,6 +2746,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512),
HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32),
HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128),
HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3),
HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3),

1
arch/arm64/kernel/cpuinfo.c
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@ -129,6 +129,7 @@ static const char *const hwcap_str[] = {
[KERNEL_HWCAP_HBC] = "hbc",
[KERNEL_HWCAP_SVE_B16B16] = "sveb16b16",
[KERNEL_HWCAP_LRCPC3] = "lrcpc3",
[KERNEL_HWCAP_LSE128] = "lse128",
};
#ifdef CONFIG_COMPAT

1
arch/arm64/tools/sysreg
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@ -1239,6 +1239,7 @@ EndEnum
UnsignedEnum 23:20 ATOMIC
0b0000 NI
0b0010 IMP
0b0011 FEAT_LSE128
EndEnum
UnsignedEnum 19:16 CRC32
0b0000 NI

21
tools/testing/selftests/arm64/abi/hwcap.c
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@ -81,6 +81,20 @@ static void lrcpc_sigill(void)
asm volatile(".inst 0xb8bfc3e0" : : : );
}
static void lse128_sigill(void)
{
u64 __attribute__ ((aligned (16))) mem[2] = { 10, 20 };
register u64 *memp asm ("x0") = mem;
register u64 val0 asm ("x1") = 5;
register u64 val1 asm ("x2") = 4;
/* SWPP X1, X2, [X0] */
asm volatile(".inst 0x19228001"
: "+r" (memp), "+r" (val0), "+r" (val1)
:
: "cc", "memory");
}
static void mops_sigill(void)
{
char dst[1], src[1];
@ -390,6 +404,13 @@ static const struct hwcap_data {
.sigbus_fn = uscat_sigbus,
.sigbus_reliable = true,
},
{
.name = "LSE128",
.at_hwcap = AT_HWCAP2,
.hwcap_bit = HWCAP2_LSE128,
.cpuinfo = "lse128",
.sigill_fn = lse128_sigill,
},
{
.name = "MOPS",
.at_hwcap = AT_HWCAP2,