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plat-orion: share time handling code
Split off Orion time handling code into plat-orion/. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Reviewed-by: Tzachi Perelstein <tzachi@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Nicolas Pitre <nico@marvell.com>
This commit is contained in:
Lennert Buytenhek
Nicolas Pitre
parent
abc0197d7a
commit
2bac1de203
@ -1,4 +1,4 @@
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obj-y += common.o addr-map.o pci.o gpio.o irq.o time.o
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obj-y += common.o addr-map.o pci.o gpio.o irq.o
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obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o
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obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o
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obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o
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@ -23,8 +23,11 @@
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#include <asm/timex.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/orion.h>
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#include <asm/arch/platform.h>
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#include <asm/plat-orion/time.h>
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#include "common.h"
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/*****************************************************************************
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@ -295,6 +298,19 @@ void __init orion_sata_init(struct mv_sata_platform_data *sata_data)
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platform_device_register(&orion_sata);
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}
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/*****************************************************************************
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* Time handling
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****************************************************************************/
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static void orion_timer_init(void)
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{
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orion_time_init(IRQ_ORION_BRIDGE, ORION_TCLK);
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}
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struct sys_timer orion_timer = {
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.init = orion_timer_init,
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};
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/*****************************************************************************
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* General
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****************************************************************************/
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@ -8,6 +8,7 @@
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void __init orion_map_io(void);
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void __init orion_init_irq(void);
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void __init orion_init(void);
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extern struct sys_timer orion_timer;
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/*
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* Enumerations and functions for Orion windows mapping. Used by Orion core
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@ -56,11 +57,6 @@ struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
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void __init orion_gpio_set_valid_pins(u32 pins);
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void gpio_display(void); /* debug */
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/*
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* Orion system timer (clocksource + clockevnt, /mach-orion/time.c)
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*/
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extern struct sys_timer orion_timer;
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/*
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* Pull in Orion Ethernet platform_data, used by machine-setup
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*/
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@ -1,181 +0,0 @@
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/*
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* arch/arm/mach-orion/time.c
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*
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* Core time functions for Marvell Orion System On Chip
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/mach/time.h>
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#include <asm/arch/orion.h>
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#include "common.h"
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/*
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* Timer0: clock_event_device, Tick.
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* Timer1: clocksource, Free running.
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* WatchDog: Not used.
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*
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* Timers are counting down.
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*/
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#define CLOCKEVENT 0
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#define CLOCKSOURCE 1
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/*
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* Timers bits
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*/
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#define BRIDGE_INT_TIMER(x) (1 << ((x) + 1))
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#define TIMER_EN(x) (1 << ((x) * 2))
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#define TIMER_RELOAD_EN(x) (1 << (((x) * 2) + 1))
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#define BRIDGE_INT_TIMER_WD (1 << 3)
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#define TIMER_WD_EN (1 << 4)
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#define TIMER_WD_RELOAD_EN (1 << 5)
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static cycle_t orion_clksrc_read(void)
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{
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return (0xffffffff - orion_read(TIMER_VAL(CLOCKSOURCE)));
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}
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static struct clocksource orion_clksrc = {
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.name = "orion_clocksource",
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.shift = 20,
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.rating = 300,
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.read = orion_clksrc_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int
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orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
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{
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unsigned long flags;
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if (delta == 0)
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return -ETIME;
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local_irq_save(flags);
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/*
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* Clear and enable timer interrupt bit
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*/
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orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
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orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
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/*
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* Setup new timer value
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*/
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orion_write(TIMER_VAL(CLOCKEVENT), delta);
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/*
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* Disable auto reload and kickoff the timer
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*/
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orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT));
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orion_setbits(TIMER_CTRL, TIMER_EN(CLOCKEVENT));
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local_irq_restore(flags);
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return 0;
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}
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static void
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orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
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{
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unsigned long flags;
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local_irq_save(flags);
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if (mode == CLOCK_EVT_MODE_PERIODIC) {
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/*
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* Setup latch cycles in timer and enable reload interrupt.
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*/
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orion_write(TIMER_VAL_RELOAD(CLOCKEVENT), LATCH);
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orion_write(TIMER_VAL(CLOCKEVENT), LATCH);
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orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
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orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) |
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TIMER_EN(CLOCKEVENT));
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} else {
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/*
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* Disable timer and interrupt
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*/
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orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
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orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
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orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) |
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TIMER_EN(CLOCKEVENT));
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}
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local_irq_restore(flags);
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}
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static struct clock_event_device orion_clkevt = {
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.name = "orion_tick",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.rating = 300,
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.cpumask = CPU_MASK_CPU0,
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.set_next_event = orion_clkevt_next_event,
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.set_mode = orion_clkevt_mode,
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};
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static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
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{
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/*
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* Clear cause bit and do event
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*/
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orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
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orion_clkevt.event_handler(&orion_clkevt);
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return IRQ_HANDLED;
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}
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static struct irqaction orion_timer_irq = {
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.name = "orion_tick",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = orion_timer_interrupt
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};
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static void orion_timer_init(void)
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{
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/*
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* Setup clocksource free running timer (no interrupt on reload)
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*/
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orion_write(TIMER_VAL(CLOCKSOURCE), 0xffffffff);
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orion_write(TIMER_VAL_RELOAD(CLOCKSOURCE), 0xffffffff);
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orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKSOURCE));
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orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKSOURCE) |
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TIMER_EN(CLOCKSOURCE));
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/*
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* Register clocksource
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*/
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orion_clksrc.mult =
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clocksource_hz2mult(CLOCK_TICK_RATE, orion_clksrc.shift);
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clocksource_register(&orion_clksrc);
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/*
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* Connect and enable tick handler
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*/
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setup_irq(IRQ_ORION_BRIDGE, &orion_timer_irq);
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/*
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* Register clockevent
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*/
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orion_clkevt.mult =
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div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, orion_clkevt.shift);
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orion_clkevt.max_delta_ns =
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clockevent_delta2ns(0xfffffffe, &orion_clkevt);
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orion_clkevt.min_delta_ns =
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clockevent_delta2ns(1, &orion_clkevt);
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clockevents_register_device(&orion_clkevt);
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}
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struct sys_timer orion_timer = {
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.init = orion_timer_init,
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};
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@ -2,7 +2,7 @@
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# Makefile for the linux kernel.
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#
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obj-y := irq.o pcie.o
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obj-y := irq.o pcie.o time.o
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obj-m :=
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obj-n :=
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obj- :=
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203
arch/arm/plat-orion/time.c
Normal file
203
arch/arm/plat-orion/time.c
Normal file
@ -0,0 +1,203 @@
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/*
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* arch/arm/plat-orion/time.c
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*
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* Marvell Orion SoC timer handling.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Timer 0 is used as free-running clocksource, while timer 1 is
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* used as clock_event_device.
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*/
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#include <linux/kernel.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/mach/time.h>
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#include <asm/arch/hardware.h>
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/*
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* Number of timer ticks per jiffy.
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*/
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static u32 ticks_per_jiffy;
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/*
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* Timer block registers.
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*/
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#define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000)
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#define TIMER0_EN 0x0001
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#define TIMER0_RELOAD_EN 0x0002
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#define TIMER1_EN 0x0004
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#define TIMER1_RELOAD_EN 0x0008
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#define TIMER0_RELOAD (TIMER_VIRT_BASE + 0x0010)
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#define TIMER0_VAL (TIMER_VIRT_BASE + 0x0014)
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#define TIMER1_RELOAD (TIMER_VIRT_BASE + 0x0018)
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#define TIMER1_VAL (TIMER_VIRT_BASE + 0x001c)
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/*
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* Clocksource handling.
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*/
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static cycle_t orion_clksrc_read(void)
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{
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return 0xffffffff - readl(TIMER0_VAL);
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}
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static struct clocksource orion_clksrc = {
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.name = "orion_clocksource",
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.shift = 20,
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.rating = 300,
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.read = orion_clksrc_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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/*
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* Clockevent handling.
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*/
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static int
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orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
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{
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unsigned long flags;
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u32 u;
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if (delta == 0)
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return -ETIME;
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local_irq_save(flags);
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/*
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* Clear and enable clockevent timer interrupt.
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*/
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writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
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u = readl(BRIDGE_MASK);
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u |= BRIDGE_INT_TIMER1;
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writel(u, BRIDGE_MASK);
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/*
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* Setup new clockevent timer value.
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*/
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writel(delta, TIMER1_VAL);
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/*
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* Enable the timer.
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*/
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u = readl(TIMER_CTRL);
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u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
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writel(u, TIMER_CTRL);
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local_irq_restore(flags);
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return 0;
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}
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static void
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orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
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{
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unsigned long flags;
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u32 u;
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local_irq_save(flags);
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if (mode == CLOCK_EVT_MODE_PERIODIC) {
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/*
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* Setup timer to fire at 1/HZ intervals.
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*/
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writel(ticks_per_jiffy - 1, TIMER1_RELOAD);
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writel(ticks_per_jiffy - 1, TIMER1_VAL);
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/*
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* Enable timer interrupt.
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*/
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u = readl(BRIDGE_MASK);
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writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK);
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/*
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* Enable timer.
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*/
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u = readl(TIMER_CTRL);
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writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL);
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} else {
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/*
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* Disable timer.
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*/
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u = readl(TIMER_CTRL);
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writel(u & ~TIMER1_EN, TIMER_CTRL);
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/*
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* Disable timer interrupt.
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*/
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u = readl(BRIDGE_MASK);
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writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK);
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/*
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* ACK pending timer interrupt.
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*/
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writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
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}
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local_irq_restore(flags);
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}
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static struct clock_event_device orion_clkevt = {
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.name = "orion_tick",
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
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.shift = 32,
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.rating = 300,
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.cpumask = CPU_MASK_CPU0,
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.set_next_event = orion_clkevt_next_event,
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.set_mode = orion_clkevt_mode,
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};
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static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
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{
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/*
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* ACK timer interrupt and call event handler.
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*/
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writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
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orion_clkevt.event_handler(&orion_clkevt);
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return IRQ_HANDLED;
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}
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static struct irqaction orion_timer_irq = {
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.name = "orion_tick",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = orion_timer_interrupt
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};
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void __init orion_time_init(unsigned int irq, unsigned int tclk)
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{
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u32 u;
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ticks_per_jiffy = (tclk + HZ/2) / HZ;
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/*
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* Setup free-running clocksource timer (interrupts
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* disabled.)
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*/
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writel(0xffffffff, TIMER0_VAL);
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writel(0xffffffff, TIMER0_RELOAD);
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u = readl(BRIDGE_MASK);
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writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK);
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u = readl(TIMER_CTRL);
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writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL);
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orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift);
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clocksource_register(&orion_clksrc);
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/*
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* Setup clockevent timer (interrupt-driven.)
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*/
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setup_irq(irq, &orion_timer_irq);
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orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
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orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
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orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
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clockevents_register_device(&orion_clkevt);
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}
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@ -137,11 +137,12 @@
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#define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C)
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#define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110)
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#define BRIDGE_MASK ORION_BRIDGE_REG(0x114)
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#define BRIDGE_INT_TIMER0 0x0002
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#define BRIDGE_INT_TIMER1 0x0004
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#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200)
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#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204)
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#define TIMER_CTRL ORION_BRIDGE_REG(0x300)
|
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#define TIMER_VAL(x) ORION_BRIDGE_REG(0x314 + ((x) * 8))
|
||||
#define TIMER_VAL_RELOAD(x) ORION_BRIDGE_REG(0x310 + ((x) * 8))
|
||||
|
||||
#define TIMER_VIRT_BASE (ORION_BRIDGE_VIRT_BASE | 0x300)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
|
||||
@ -8,5 +8,6 @@
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#define CLOCK_TICK_RATE (100 * HZ)
|
||||
|
||||
#define ORION_TCLK 166666667
|
||||
#define CLOCK_TICK_RATE ORION_TCLK
|
||||
|
||||
17
include/asm-arm/plat-orion/time.h
Normal file
17
include/asm-arm/plat-orion/time.h
Normal file
@ -0,0 +1,17 @@
|
||||
/*
|
||||
* include/asm-arm/plat-orion/time.h
|
||||
*
|
||||
* Marvell Orion SoC time handling.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_PLAT_ORION_TIME_H
|
||||
#define __ASM_PLAT_ORION_TIME_H
|
||||
|
||||
void orion_time_init(unsigned int irq, unsigned int tclk);
|
||||
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user