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soc: amlogic: Add Meson Clock Measure driver
The Amlogic Meson SoCs embeds a clock measurer IP to measure the internal clock paths frequencies. The precision is determined by stepping into the duration until the counter overflows. The debugfs slows a pretty summary and each clock can be measured individually aswell. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This commit is contained in:
Neil Armstrong
Kevin Hilman
parent
b4c29e8902
commit
2b45ebef39
@ -7,6 +7,14 @@ config MESON_CANVAS
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help
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Say yes to support the canvas IP for Amlogic SoCs.
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config MESON_CLK_MEASURE
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bool "Amlogic Meson SoC Clock Measure driver"
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depends on ARCH_MESON || COMPILE_TEST
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default ARCH_MESON
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help
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Say yes to support of Measuring a set of internal SoC clocks
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from the debugfs interface.
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config MESON_GX_SOCINFO
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bool "Amlogic Meson GX SoC Information driver"
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depends on ARCH_MESON || COMPILE_TEST
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@ -1,4 +1,5 @@
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obj-$(CONFIG_MESON_CANVAS) += meson-canvas.o
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obj-$(CONFIG_MESON_CLK_MEASURE) += meson-clk-measure.o
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obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o
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obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o
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obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o
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350
drivers/soc/amlogic/meson-clk-measure.c
Normal file
350
drivers/soc/amlogic/meson-clk-measure.c
Normal file
@ -0,0 +1,350 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2018 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/bitfield.h>
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#include <linux/seq_file.h>
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#include <linux/debugfs.h>
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#include <linux/regmap.h>
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#define MSR_CLK_DUTY 0x0
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#define MSR_CLK_REG0 0x4
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#define MSR_CLK_REG1 0x8
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#define MSR_CLK_REG2 0xc
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#define MSR_DURATION GENMASK(15, 0)
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#define MSR_ENABLE BIT(16)
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#define MSR_CONT BIT(17) /* continuous measurement */
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#define MSR_INTR BIT(18) /* interrupts */
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#define MSR_RUN BIT(19)
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#define MSR_CLK_SRC GENMASK(26, 20)
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#define MSR_BUSY BIT(31)
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#define MSR_VAL_MASK GENMASK(15, 0)
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#define DIV_MIN 32
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#define DIV_STEP 32
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#define DIV_MAX 640
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#define CLK_MSR_MAX 128
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struct meson_msr_id {
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struct meson_msr *priv;
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unsigned int id;
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const char *name;
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};
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struct meson_msr {
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struct regmap *regmap;
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struct meson_msr_id msr_table[CLK_MSR_MAX];
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};
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#define CLK_MSR_ID(__id, __name) \
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[__id] = {.id = __id, .name = __name,}
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static struct meson_msr_id clk_msr_m8[CLK_MSR_MAX] = {
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CLK_MSR_ID(0, "ring_osc_out_ee0"),
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CLK_MSR_ID(1, "ring_osc_out_ee1"),
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CLK_MSR_ID(2, "ring_osc_out_ee2"),
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CLK_MSR_ID(3, "a9_ring_osck"),
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CLK_MSR_ID(6, "vid_pll"),
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CLK_MSR_ID(7, "clk81"),
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CLK_MSR_ID(8, "encp"),
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CLK_MSR_ID(9, "encl"),
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CLK_MSR_ID(11, "eth_rmii"),
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CLK_MSR_ID(13, "amclk"),
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CLK_MSR_ID(14, "fec_clk_0"),
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CLK_MSR_ID(15, "fec_clk_1"),
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CLK_MSR_ID(16, "fec_clk_2"),
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CLK_MSR_ID(18, "a9_clk_div16"),
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CLK_MSR_ID(19, "hdmi_sys"),
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CLK_MSR_ID(20, "rtc_osc_clk_out"),
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CLK_MSR_ID(21, "i2s_clk_in_src0"),
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CLK_MSR_ID(22, "clk_rmii_from_pad"),
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CLK_MSR_ID(23, "hdmi_ch0_tmds"),
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CLK_MSR_ID(24, "lvds_fifo"),
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CLK_MSR_ID(26, "sc_clk_int"),
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CLK_MSR_ID(28, "sar_adc"),
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CLK_MSR_ID(30, "mpll_clk_test_out"),
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CLK_MSR_ID(31, "audac_clkpi"),
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CLK_MSR_ID(32, "vdac"),
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CLK_MSR_ID(33, "sdhc_rx"),
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CLK_MSR_ID(34, "sdhc_sd"),
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CLK_MSR_ID(35, "mali"),
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CLK_MSR_ID(36, "hdmi_tx_pixel"),
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CLK_MSR_ID(38, "vdin_meas"),
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CLK_MSR_ID(39, "pcm_sclk"),
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CLK_MSR_ID(40, "pcm_mclk"),
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CLK_MSR_ID(41, "eth_rx_tx"),
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CLK_MSR_ID(42, "pwm_d"),
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CLK_MSR_ID(43, "pwm_c"),
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CLK_MSR_ID(44, "pwm_b"),
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CLK_MSR_ID(45, "pwm_a"),
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CLK_MSR_ID(46, "pcm2_sclk"),
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CLK_MSR_ID(47, "ddr_dpll_pt"),
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CLK_MSR_ID(48, "pwm_f"),
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CLK_MSR_ID(49, "pwm_e"),
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CLK_MSR_ID(59, "hcodec"),
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CLK_MSR_ID(60, "usb_32k_alt"),
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CLK_MSR_ID(61, "gpio"),
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CLK_MSR_ID(62, "vid2_pll"),
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CLK_MSR_ID(63, "mipi_csi_cfg"),
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};
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static struct meson_msr_id clk_msr_gx[CLK_MSR_MAX] = {
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CLK_MSR_ID(0, "ring_osc_out_ee_0"),
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CLK_MSR_ID(1, "ring_osc_out_ee_1"),
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CLK_MSR_ID(2, "ring_osc_out_ee_2"),
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CLK_MSR_ID(3, "a53_ring_osc"),
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CLK_MSR_ID(4, "gp0_pll"),
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CLK_MSR_ID(6, "enci"),
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CLK_MSR_ID(7, "clk81"),
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CLK_MSR_ID(8, "encp"),
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CLK_MSR_ID(9, "encl"),
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CLK_MSR_ID(10, "vdac"),
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CLK_MSR_ID(11, "rgmii_tx"),
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CLK_MSR_ID(12, "pdm"),
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CLK_MSR_ID(13, "amclk"),
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CLK_MSR_ID(14, "fec_0"),
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CLK_MSR_ID(15, "fec_1"),
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CLK_MSR_ID(16, "fec_2"),
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CLK_MSR_ID(17, "sys_pll_div16"),
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CLK_MSR_ID(18, "sys_cpu_div16"),
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CLK_MSR_ID(19, "hdmitx_sys"),
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CLK_MSR_ID(20, "rtc_osc_out"),
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CLK_MSR_ID(21, "i2s_in_src0"),
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CLK_MSR_ID(22, "eth_phy_ref"),
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CLK_MSR_ID(23, "hdmi_todig"),
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CLK_MSR_ID(26, "sc_int"),
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CLK_MSR_ID(28, "sar_adc"),
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CLK_MSR_ID(31, "mpll_test_out"),
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CLK_MSR_ID(32, "vdec"),
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CLK_MSR_ID(35, "mali"),
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CLK_MSR_ID(36, "hdmi_tx_pixel"),
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CLK_MSR_ID(37, "i958"),
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CLK_MSR_ID(38, "vdin_meas"),
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CLK_MSR_ID(39, "pcm_sclk"),
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CLK_MSR_ID(40, "pcm_mclk"),
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CLK_MSR_ID(41, "eth_rx_or_rmii"),
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CLK_MSR_ID(42, "mp0_out"),
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CLK_MSR_ID(43, "fclk_div5"),
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CLK_MSR_ID(44, "pwm_b"),
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CLK_MSR_ID(45, "pwm_a"),
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CLK_MSR_ID(46, "vpu"),
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CLK_MSR_ID(47, "ddr_dpll_pt"),
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CLK_MSR_ID(48, "mp1_out"),
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CLK_MSR_ID(49, "mp2_out"),
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CLK_MSR_ID(50, "mp3_out"),
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CLK_MSR_ID(51, "nand_core"),
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CLK_MSR_ID(52, "sd_emmc_b"),
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CLK_MSR_ID(53, "sd_emmc_a"),
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CLK_MSR_ID(55, "vid_pll_div_out"),
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CLK_MSR_ID(56, "cci"),
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CLK_MSR_ID(57, "wave420l_c"),
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CLK_MSR_ID(58, "wave420l_b"),
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CLK_MSR_ID(59, "hcodec"),
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CLK_MSR_ID(60, "alt_32k"),
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CLK_MSR_ID(61, "gpio_msr"),
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CLK_MSR_ID(62, "hevc"),
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CLK_MSR_ID(66, "vid_lock"),
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CLK_MSR_ID(70, "pwm_f"),
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CLK_MSR_ID(71, "pwm_e"),
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CLK_MSR_ID(72, "pwm_d"),
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CLK_MSR_ID(73, "pwm_c"),
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CLK_MSR_ID(75, "aoclkx2_int"),
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CLK_MSR_ID(76, "aoclk_int"),
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CLK_MSR_ID(77, "rng_ring_osc_0"),
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CLK_MSR_ID(78, "rng_ring_osc_1"),
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CLK_MSR_ID(79, "rng_ring_osc_2"),
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CLK_MSR_ID(80, "rng_ring_osc_3"),
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CLK_MSR_ID(81, "vapb"),
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CLK_MSR_ID(82, "ge2d"),
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};
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static int meson_measure_id(struct meson_msr_id *clk_msr_id,
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unsigned int duration)
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{
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struct meson_msr *priv = clk_msr_id->priv;
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unsigned int val;
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int ret;
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regmap_write(priv->regmap, MSR_CLK_REG0, 0);
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/* Set measurement duration */
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regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_DURATION,
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FIELD_PREP(MSR_DURATION, duration - 1));
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/* Set ID */
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regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_CLK_SRC,
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FIELD_PREP(MSR_CLK_SRC, clk_msr_id->id));
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/* Enable & Start */
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regmap_update_bits(priv->regmap, MSR_CLK_REG0,
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MSR_RUN | MSR_ENABLE,
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MSR_RUN | MSR_ENABLE);
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ret = regmap_read_poll_timeout(priv->regmap, MSR_CLK_REG0,
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val, !(val & MSR_BUSY), 10, 10000);
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if (ret)
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return ret;
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/* Disable */
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regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_ENABLE, 0);
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/* Get the value in multiple of gate time counts */
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regmap_read(priv->regmap, MSR_CLK_REG2, &val);
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if (val >= MSR_VAL_MASK)
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return -EINVAL;
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return DIV_ROUND_CLOSEST_ULL((val & MSR_VAL_MASK) * 1000000ULL,
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duration);
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}
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static int meson_measure_best_id(struct meson_msr_id *clk_msr_id,
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unsigned int *precision)
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{
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unsigned int duration = DIV_MAX;
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int ret;
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/* Start from max duration and down to min duration */
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do {
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ret = meson_measure_id(clk_msr_id, duration);
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if (ret >= 0)
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*precision = (2 * 1000000) / duration;
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else
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duration -= DIV_STEP;
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} while (duration >= DIV_MIN && ret == -EINVAL);
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return ret;
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}
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static int clk_msr_show(struct seq_file *s, void *data)
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{
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struct meson_msr_id *clk_msr_id = s->private;
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unsigned int precision = 0;
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int val;
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val = meson_measure_best_id(clk_msr_id, &precision);
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if (val < 0)
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return val;
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seq_printf(s, "%d\t+/-%dHz\n", val, precision);
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(clk_msr);
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static int clk_msr_summary_show(struct seq_file *s, void *data)
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{
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struct meson_msr_id *msr_table = s->private;
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unsigned int precision = 0;
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int val, i;
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seq_puts(s, " clock rate precision\n");
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seq_puts(s, "---------------------------------------------\n");
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for (i = 0 ; i < CLK_MSR_MAX ; ++i) {
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if (!msr_table[i].name)
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continue;
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val = meson_measure_best_id(&msr_table[i], &precision);
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if (val < 0)
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return val;
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seq_printf(s, " %-20s %10d +/-%dHz\n",
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msr_table[i].name, val, precision);
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}
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(clk_msr_summary);
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static const struct regmap_config meson_clk_msr_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = MSR_CLK_REG2,
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};
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static int meson_msr_probe(struct platform_device *pdev)
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{
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const struct meson_msr_id *match_data;
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struct meson_msr *priv;
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struct resource *res;
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struct dentry *root, *clks;
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void __iomem *base;
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int i;
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priv = devm_kzalloc(&pdev->dev, sizeof(struct meson_msr),
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GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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match_data = device_get_match_data(&pdev->dev);
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if (!match_data) {
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dev_err(&pdev->dev, "failed to get match data\n");
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return -ENODEV;
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}
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memcpy(priv->msr_table, match_data, sizeof(priv->msr_table));
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base)) {
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dev_err(&pdev->dev, "io resource mapping failed\n");
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return PTR_ERR(base);
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}
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priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
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&meson_clk_msr_regmap_config);
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if (IS_ERR(priv->regmap))
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return PTR_ERR(priv->regmap);
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root = debugfs_create_dir("meson-clk-msr", NULL);
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clks = debugfs_create_dir("clks", root);
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debugfs_create_file("measure_summary", 0444, root,
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priv->msr_table, &clk_msr_summary_fops);
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for (i = 0 ; i < CLK_MSR_MAX ; ++i) {
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if (!priv->msr_table[i].name)
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continue;
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priv->msr_table[i].priv = priv;
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debugfs_create_file(priv->msr_table[i].name, 0444, clks,
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&priv->msr_table[i], &clk_msr_fops);
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}
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return 0;
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}
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static const struct of_device_id meson_msr_match_table[] = {
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{
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.compatible = "amlogic,meson-gx-clk-measure",
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.data = (void *)clk_msr_gx,
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},
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{
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.compatible = "amlogic,meson8-clk-measure",
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.data = (void *)clk_msr_m8,
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},
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{
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.compatible = "amlogic,meson8b-clk-measure",
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.data = (void *)clk_msr_m8,
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},
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{ /* sentinel */ }
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};
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static struct platform_driver meson_msr_driver = {
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.probe = meson_msr_probe,
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.driver = {
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.name = "meson_msr",
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.of_match_table = meson_msr_match_table,
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},
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};
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builtin_platform_driver(meson_msr_driver);
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