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drm/nouveau/ppwr: enable ppwr on gm107

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For some reason, it is now required to wait a 20 µs after the 0x200 reset of
the engine.

Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Martin Peres 2014-08-17 17:33:09 +02:00 committed by Ben Skeggs
parent 808a188a33
commit 2a5e5fa734
2 changed files with 5 additions and 1 deletions
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3
drivers/gpu/drm/nouveau/core/engine/device/gm100.c
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@ -75,8 +75,9 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
#if 0
device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass;
#if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
#endif
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;

3
drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
View File

@ -204,6 +204,9 @@ _nouveau_pwr_init(struct nouveau_object *object)
nv_mask(ppwr, 0x000200, 0x00002000, 0x00000000);
nv_mask(ppwr, 0x000200, 0x00002000, 0x00002000);
/* At least one GM107 needs this delay after reset */
udelay(20);
/* upload data segment */
nv_wr32(ppwr, 0x10a1c0, 0x01000000);
for (i = 0; i < impl->data.size / 4; i++)