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spi: npcm: add NPCM PSPI controller driver
Add Nuvoton NPCM BMC Peripheral SPI controller driver. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Tomer Maimon
Mark Brown
parent
4ad26864df
commit
2a22f1b30c
@ -397,6 +397,13 @@ config SPI_MT65XX
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say Y or M here.If you are not sure, say N.
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SPI drivers for Mediatek MT65XX and MT81XX series ARM SoCs.
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config SPI_NPCM_PSPI
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tristate "Nuvoton NPCM PSPI Controller"
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depends on ARCH_NPCM || COMPILE_TEST
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help
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This driver provides support for Nuvoton NPCM BMC
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Peripheral SPI controller in master mode.
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config SPI_NUC900
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tristate "Nuvoton NUC900 series SPI"
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depends on ARCH_W90X900
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@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
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obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
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obj-$(CONFIG_SPI_MXIC) += spi-mxic.o
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obj-$(CONFIG_SPI_MXS) += spi-mxs.o
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obj-$(CONFIG_SPI_NPCM_PSPI) += spi-npcm-pspi.o
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obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
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obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
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spi-octeon-objs := spi-cavium.o spi-cavium-octeon.o
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480
drivers/spi/spi-npcm-pspi.c
Normal file
480
drivers/spi/spi-npcm-pspi.c
Normal file
@ -0,0 +1,480 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018 Nuvoton Technology corporation.
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#include <linux/kernel.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/gpio.h>
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#include <linux/of_gpio.h>
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#include <asm/unaligned.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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struct npcm_pspi {
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struct completion xfer_done;
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struct regmap *rst_regmap;
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struct spi_master *master;
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unsigned int tx_bytes;
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unsigned int rx_bytes;
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void __iomem *base;
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bool is_save_param;
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u8 bits_per_word;
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const u8 *tx_buf;
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struct clk *clk;
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u32 speed_hz;
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u8 *rx_buf;
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u16 mode;
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u32 id;
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};
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#define DRIVER_NAME "npcm-pspi"
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#define NPCM_PSPI_DATA 0x00
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#define NPCM_PSPI_CTL1 0x02
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#define NPCM_PSPI_STAT 0x04
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/* definitions for control and status register */
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#define NPCM_PSPI_CTL1_SPIEN BIT(0)
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#define NPCM_PSPI_CTL1_MOD BIT(2)
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#define NPCM_PSPI_CTL1_EIR BIT(5)
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#define NPCM_PSPI_CTL1_EIW BIT(6)
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#define NPCM_PSPI_CTL1_SCM BIT(7)
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#define NPCM_PSPI_CTL1_SCIDL BIT(8)
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#define NPCM_PSPI_CTL1_SCDV6_0 GENMASK(15, 9)
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#define NPCM_PSPI_STAT_BSY BIT(0)
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#define NPCM_PSPI_STAT_RBF BIT(1)
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/* general definitions */
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#define NPCM_PSPI_TIMEOUT_MS 2000
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#define NPCM_PSPI_MAX_CLK_DIVIDER 256
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#define NPCM_PSPI_MIN_CLK_DIVIDER 4
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#define NPCM_PSPI_DEFAULT_CLK 25000000
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/* reset register */
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#define NPCM7XX_IPSRST2_OFFSET 0x24
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#define NPCM7XX_PSPI1_RESET BIT(22)
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#define NPCM7XX_PSPI2_RESET BIT(23)
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static inline unsigned int bytes_per_word(unsigned int bits)
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{
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return bits <= 8 ? 1 : 2;
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}
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static inline void npcm_pspi_irq_enable(struct npcm_pspi *priv, u16 mask)
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{
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u16 val;
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val = ioread16(priv->base + NPCM_PSPI_CTL1);
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val |= mask;
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iowrite16(val, priv->base + NPCM_PSPI_CTL1);
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}
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static inline void npcm_pspi_irq_disable(struct npcm_pspi *priv, u16 mask)
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{
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u16 val;
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val = ioread16(priv->base + NPCM_PSPI_CTL1);
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val &= ~mask;
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iowrite16(val, priv->base + NPCM_PSPI_CTL1);
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}
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static inline void npcm_pspi_enable(struct npcm_pspi *priv)
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{
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u16 val;
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val = ioread16(priv->base + NPCM_PSPI_CTL1);
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val |= NPCM_PSPI_CTL1_SPIEN;
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iowrite16(val, priv->base + NPCM_PSPI_CTL1);
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}
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static inline void npcm_pspi_disable(struct npcm_pspi *priv)
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{
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u16 val;
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val = ioread16(priv->base + NPCM_PSPI_CTL1);
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val &= ~NPCM_PSPI_CTL1_SPIEN;
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iowrite16(val, priv->base + NPCM_PSPI_CTL1);
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}
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static void npcm_pspi_set_mode(struct spi_device *spi)
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{
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struct npcm_pspi *priv = spi_master_get_devdata(spi->master);
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u16 regtemp;
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u16 mode_val;
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switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
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case SPI_MODE_0:
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mode_val = 0;
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break;
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case SPI_MODE_1:
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mode_val = NPCM_PSPI_CTL1_SCIDL;
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break;
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case SPI_MODE_2:
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mode_val = NPCM_PSPI_CTL1_SCM;
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break;
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case SPI_MODE_3:
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mode_val = NPCM_PSPI_CTL1_SCIDL | NPCM_PSPI_CTL1_SCM;
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break;
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}
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regtemp = ioread16(priv->base + NPCM_PSPI_CTL1);
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regtemp &= ~(NPCM_PSPI_CTL1_SCM | NPCM_PSPI_CTL1_SCIDL);
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iowrite16(regtemp | mode_val, priv->base + NPCM_PSPI_CTL1);
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}
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static void npcm_pspi_set_transfer_size(struct npcm_pspi *priv, int size)
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{
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u16 regtemp;
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regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base);
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switch (size) {
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case 8:
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regtemp &= ~NPCM_PSPI_CTL1_MOD;
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break;
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case 16:
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regtemp |= NPCM_PSPI_CTL1_MOD;
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break;
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}
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iowrite16(regtemp, NPCM_PSPI_CTL1 + priv->base);
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}
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static void npcm_pspi_set_baudrate(struct npcm_pspi *priv, unsigned int speed)
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{
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u32 ckdiv;
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u16 regtemp;
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/* the supported rates are numbers from 4 to 256. */
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ckdiv = DIV_ROUND_CLOSEST(clk_get_rate(priv->clk), (2 * speed)) - 1;
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regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base);
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regtemp &= ~NPCM_PSPI_CTL1_SCDV6_0;
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iowrite16(regtemp | (ckdiv << 9), NPCM_PSPI_CTL1 + priv->base);
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}
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static void npcm_pspi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct npcm_pspi *priv = spi_master_get_devdata(spi->master);
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priv->tx_buf = t->tx_buf;
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priv->rx_buf = t->rx_buf;
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priv->tx_bytes = t->len;
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priv->rx_bytes = t->len;
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if (!priv->is_save_param || priv->mode != spi->mode) {
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npcm_pspi_set_mode(spi);
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priv->mode = spi->mode;
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}
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if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) {
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npcm_pspi_set_transfer_size(priv, t->bits_per_word);
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priv->bits_per_word = t->bits_per_word;
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}
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if (!priv->is_save_param || priv->speed_hz != t->speed_hz) {
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npcm_pspi_set_baudrate(priv, t->speed_hz);
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priv->speed_hz = t->speed_hz;
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}
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if (!priv->is_save_param)
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priv->is_save_param = true;
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}
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static void npcm_pspi_send(struct npcm_pspi *priv)
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{
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int wsize;
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wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
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priv->tx_bytes -= wsize;
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if (priv->tx_buf) {
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if (wsize == 1)
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iowrite8(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
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if (wsize == 2)
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iowrite16(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
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priv->tx_buf += wsize;
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}
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}
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static void npcm_pspi_recv(struct npcm_pspi *priv)
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{
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int rsize;
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u16 val;
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rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
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priv->rx_bytes -= rsize;
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if (priv->rx_buf) {
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if (rsize == 1)
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val = ioread8(priv->base + NPCM_PSPI_DATA);
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if (rsize == 2)
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val = ioread16(priv->base + NPCM_PSPI_DATA);
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*priv->rx_buf = val;
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priv->rx_buf += rsize;
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}
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}
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static int npcm_pspi_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct npcm_pspi *priv = spi_master_get_devdata(master);
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int status;
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npcm_pspi_setup_transfer(spi, t);
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reinit_completion(&priv->xfer_done);
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npcm_pspi_enable(priv);
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status = wait_for_completion_timeout(&priv->xfer_done,
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msecs_to_jiffies
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(NPCM_PSPI_TIMEOUT_MS));
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if (status == 0) {
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npcm_pspi_disable(priv);
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int npcm_pspi_prepare_transfer_hardware(struct spi_master *master)
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{
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struct npcm_pspi *priv = spi_master_get_devdata(master);
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npcm_pspi_irq_enable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW);
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return 0;
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}
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static int npcm_pspi_unprepare_transfer_hardware(struct spi_master *master)
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{
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struct npcm_pspi *priv = spi_master_get_devdata(master);
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npcm_pspi_irq_disable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW);
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return 0;
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}
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static void npcm_pspi_reset_hw(struct npcm_pspi *priv)
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{
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regmap_write(priv->rst_regmap, NPCM7XX_IPSRST2_OFFSET,
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NPCM7XX_PSPI1_RESET << priv->id);
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regmap_write(priv->rst_regmap, NPCM7XX_IPSRST2_OFFSET, 0x0);
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}
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static irqreturn_t npcm_pspi_handler(int irq, void *dev_id)
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{
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struct npcm_pspi *priv = dev_id;
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u16 val;
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u8 stat;
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stat = ioread8(priv->base + NPCM_PSPI_STAT);
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if (!priv->tx_buf && !priv->rx_buf)
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return IRQ_NONE;
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if (priv->tx_buf) {
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if (stat & NPCM_PSPI_STAT_RBF) {
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val = ioread8(NPCM_PSPI_DATA + priv->base);
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if (priv->tx_bytes == 0) {
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npcm_pspi_disable(priv);
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complete(&priv->xfer_done);
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return IRQ_HANDLED;
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}
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}
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if ((stat & NPCM_PSPI_STAT_BSY) == 0)
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if (priv->tx_bytes)
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npcm_pspi_send(priv);
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}
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if (priv->rx_buf) {
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if (stat & NPCM_PSPI_STAT_RBF) {
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if (!priv->rx_bytes)
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return IRQ_NONE;
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npcm_pspi_recv(priv);
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if (!priv->rx_bytes) {
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npcm_pspi_disable(priv);
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complete(&priv->xfer_done);
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return IRQ_HANDLED;
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}
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}
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if (((stat & NPCM_PSPI_STAT_BSY) == 0) && !priv->tx_buf)
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iowrite8(0x0, NPCM_PSPI_DATA + priv->base);
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}
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return IRQ_HANDLED;
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}
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static int npcm_pspi_probe(struct platform_device *pdev)
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{
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struct npcm_pspi *priv;
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struct spi_master *master;
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struct resource *res;
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unsigned long clk_hz;
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struct device_node *np = pdev->dev.of_node;
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int num_cs, i;
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u32 csgpio;
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int irq;
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int ret;
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num_cs = of_gpio_named_count(np, "cs-gpios");
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if (num_cs < 0)
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return num_cs;
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pdev->id = of_alias_get_id(np, "spi");
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if (pdev->id < 0)
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pdev->id = 0;
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master = spi_alloc_master(&pdev->dev, sizeof(*priv));
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if (!master)
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return -ENOMEM;
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platform_set_drvdata(pdev, master);
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priv = spi_master_get_devdata(master);
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priv->master = master;
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priv->is_save_param = false;
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priv->id = pdev->id;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(priv->base)) {
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ret = PTR_ERR(priv->base);
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goto out_master_put;
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}
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priv->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(priv->clk)) {
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dev_err(&pdev->dev, "failed to get clock\n");
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ret = PTR_ERR(priv->clk);
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goto out_master_put;
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}
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ret = clk_prepare_enable(priv->clk);
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if (ret)
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goto out_master_put;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "failed to get IRQ\n");
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ret = irq;
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goto out_disable_clk;
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}
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priv->rst_regmap =
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syscon_regmap_lookup_by_compatible("nuvoton,npcm750-rst");
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if (IS_ERR(priv->rst_regmap)) {
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dev_err(&pdev->dev, "failed to find nuvoton,npcm750-rst\n");
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return IS_ERR(priv->rst_regmap);
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}
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/* reset SPI-HW block */
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npcm_pspi_reset_hw(priv);
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ret = devm_request_irq(&pdev->dev, irq, npcm_pspi_handler, 0,
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"npcm-pspi", priv);
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if (ret) {
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dev_err(&pdev->dev, "failed to request IRQ\n");
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goto out_disable_clk;
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}
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init_completion(&priv->xfer_done);
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clk_hz = clk_get_rate(priv->clk);
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master->max_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MIN_CLK_DIVIDER);
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master->min_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MAX_CLK_DIVIDER);
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master->mode_bits = SPI_CPHA | SPI_CPOL;
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master->dev.of_node = pdev->dev.of_node;
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master->bus_num = pdev->id;
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master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
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master->transfer_one = npcm_pspi_transfer_one;
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master->prepare_transfer_hardware =
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npcm_pspi_prepare_transfer_hardware;
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master->unprepare_transfer_hardware =
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npcm_pspi_unprepare_transfer_hardware;
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master->num_chipselect = num_cs;
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for (i = 0; i < num_cs; i++) {
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csgpio = of_get_named_gpio(np, "cs-gpios", i);
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if (csgpio < 0) {
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dev_err(&pdev->dev, "failed to get csgpio#%u\n", i);
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goto out_disable_clk;
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}
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dev_dbg(&pdev->dev, "csgpio#%u = %u\n", i, csgpio);
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ret = devm_gpio_request_one(&pdev->dev, csgpio,
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GPIOF_OUT_INIT_HIGH, DRIVER_NAME);
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if (ret < 0) {
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dev_err(&pdev->dev,
|
||||
"failed to configure csgpio#%u %u\n"
|
||||
, i, csgpio);
|
||||
goto out_disable_clk;
|
||||
}
|
||||
}
|
||||
|
||||
/* set to default clock rate */
|
||||
npcm_pspi_set_baudrate(priv, NPCM_PSPI_DEFAULT_CLK);
|
||||
|
||||
ret = devm_spi_register_master(&pdev->dev, master);
|
||||
if (ret)
|
||||
goto out_disable_clk;
|
||||
|
||||
pr_info("NPCM Peripheral SPI %d probed\n", pdev->id);
|
||||
|
||||
return 0;
|
||||
|
||||
out_disable_clk:
|
||||
clk_disable_unprepare(priv->clk);
|
||||
|
||||
out_master_put:
|
||||
spi_master_put(master);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int npcm_pspi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct npcm_pspi *priv = platform_get_drvdata(pdev);
|
||||
|
||||
npcm_pspi_reset_hw(priv);
|
||||
clk_disable_unprepare(priv->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id npcm_pspi_match[] = {
|
||||
{ .compatible = "nuvoton,npcm750-pspi", .data = NULL },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, npcm_pspi_match);
|
||||
|
||||
static struct platform_driver npcm_pspi_driver = {
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.of_match_table = npcm_pspi_match,
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = npcm_pspi_probe,
|
||||
.remove = npcm_pspi_remove,
|
||||
};
|
||||
module_platform_driver(npcm_pspi_driver);
|
||||
|
||||
MODULE_DESCRIPTION("NPCM peripheral SPI Controller driver");
|
||||
MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
Loading…
Reference in New Issue
Block a user