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hte: Changes for v6.4-rc1
The changes for the hte/timestamp subsystem include the following: - Add Tegra234 HTE provider and relevant DT bindings - Update MAINTAINERS file for the HTE subsystem -----BEGIN PGP SIGNATURE----- iIgEABYIADAWIQT4slW2T0Q/rXAa29f4pUxhzZTZKAUCZErbLBIcZGlwZW5wQG52 aWRpYS5jb20ACgkQ+KVMYc2U2SiW0QEAt3bPgopjIMzaInOguZthR1pHCuKtyK7F u4aJAyHv7tIA/jtsFJuFO4LmiwA/IsNits5l7F36oaB94/cQGuRH1M8E =opcL -----END PGP SIGNATURE----- Merge tag 'for-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux Pull hardware timestamp engine updates from Dipen Patel: "The changes for the hte subsystem include: - Add Tegra234 HTE provider and relevant DT bindings - Update MAINTAINERS file for the HTE subsystem" * tag 'for-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux: hte: tegra-194: Use proper includes hte: Use device_match_of_node() hte: tegra-194: Fix off by one in tegra_hte_map_to_line_id() hte: tegra: fix 'struct of_device_id' build error hte: Use of_property_present() for testing DT property presence gpio: tegra186: Add Tegra234 hte support hte: handle nvidia,gpio-controller property hte: Deprecate nvidia,slices property hte: Add Tegra234 provider hte: Re-phrase tegra API document arm64: tegra: Add Tegra234 GTE nodes dt-bindings: timestamp: Deprecate nvidia,slices property dt-bindings: timestamp: Add Tegra234 support MAINTAINERS: Add HTE/timestamp subsystem details
This commit is contained in:
Linus Torvalds
commit
29ee463d6f
@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Tegra194 on chip generic hardware timestamping engine (HTE)
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title: Tegra on chip generic hardware timestamping engine (HTE) provider
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maintainers:
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- Dipen Patel <dipenp@nvidia.com>
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@ -23,6 +23,8 @@ properties:
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enum:
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- nvidia,tegra194-gte-aon
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- nvidia,tegra194-gte-lic
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- nvidia,tegra234-gte-aon
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- nvidia,tegra234-gte-lic
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reg:
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maxItems: 1
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@ -40,12 +42,20 @@ properties:
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nvidia,slices:
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$ref: /schemas/types.yaml#/definitions/uint32
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deprecated: true
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description:
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HTE lines are arranged in 32 bit slice where each bit represents different
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line/signal that it can enable/configure for the timestamp. It is u32
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property and depends on the HTE instance in the chip. The value 3 is for
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GPIO GTE and 11 for IRQ GTE.
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enum: [3, 11]
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property and the value depends on the HTE instance in the chip. The AON
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GTE instances for both Tegra194 and Tegra234 has 3 slices. The Tegra194
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LIC instance has 11 slices and Tegra234 LIC has 17 slices.
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enum: [3, 11, 17]
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nvidia,gpio-controller:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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The phandle to AON gpio controller instance. This is required to handle
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namespace conversion between GPIO and GTE.
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'#timestamp-cells':
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description:
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@ -59,9 +69,53 @@ required:
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- compatible
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- reg
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- interrupts
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- nvidia,slices
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- "#timestamp-cells"
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra194-gte-aon
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- nvidia,tegra234-gte-aon
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then:
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properties:
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nvidia,slices:
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const: 3
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra194-gte-lic
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then:
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properties:
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nvidia,slices:
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const: 11
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra234-gte-lic
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then:
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properties:
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nvidia,slices:
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const: 17
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra234-gte-aon
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then:
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required:
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- nvidia,gpio-controller
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additionalProperties: false
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examples:
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@ -71,7 +125,6 @@ examples:
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reg = <0xc1e0000 0x10000>;
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interrupts = <0 13 0x4>;
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nvidia,int-threshold = <1>;
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nvidia,slices = <3>;
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#timestamp-cells = <1>;
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};
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@ -81,7 +134,6 @@ examples:
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reg = <0x3aa0000 0x10000>;
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interrupts = <0 11 0x4>;
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nvidia,int-threshold = <1>;
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nvidia,slices = <11>;
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#timestamp-cells = <1>;
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};
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@ -18,5 +18,5 @@ HTE Tegra Provider
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.. toctree::
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:maxdepth: 1
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tegra194-hte
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tegra-hte
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@ -5,25 +5,25 @@ HTE Kernel provider driver
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Description
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-----------
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The Nvidia tegra194 HTE provider driver implements two GTE
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(Generic Timestamping Engine) instances: 1) GPIO GTE and 2) LIC
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(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the
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timestamp from the system counter TSC which has 31.25MHz clock rate, and the
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driver converts clock tick rate to nanoseconds before storing it as timestamp
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value.
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The Nvidia tegra HTE provider also known as GTE (Generic Timestamping Engine)
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driver implements two GTE instances: 1) GPIO GTE and 2) LIC
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(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the timestamp
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from the system counter TSC which has 31.25MHz clock rate, and the driver
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converts clock tick rate to nanoseconds before storing it as timestamp value.
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GPIO GTE
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--------
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This GTE instance timestamps GPIO in real time. For that to happen GPIO
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needs to be configured as input. The always on (AON) GPIO controller instance
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supports timestamping GPIOs in real time and it has 39 GPIO lines. The GPIO GTE
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and AON GPIO controller are tightly coupled as it requires very specific bits
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to be set in GPIO config register before GPIO GTE can be used, for that GPIOLIB
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adds two optional APIs as below. The GPIO GTE code supports both kernel
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and userspace consumers. The kernel space consumers can directly talk to HTE
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subsystem while userspace consumers timestamp requests go through GPIOLIB CDEV
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framework to HTE subsystem.
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needs to be configured as input. Only the always on (AON) GPIO controller
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instance supports timestamping GPIOs in real time as it is tightly coupled with
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the GPIO GTE. To support this, GPIOLIB adds two optional APIs as mentioned
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below. The GPIO GTE code supports both kernel and userspace consumers. The
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kernel space consumers can directly talk to HTE subsystem while userspace
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consumers timestamp requests go through GPIOLIB CDEV framework to HTE
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subsystem. The hte devicetree binding described at
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``Documentation/devicetree/bindings/timestamp`` provides an example of how a
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consumer can request an GPIO line.
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See gpiod_enable_hw_timestamp_ns() and gpiod_disable_hw_timestamp_ns().
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@ -34,9 +34,8 @@ returns the timestamp in nanoseconds.
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LIC (Legacy Interrupt Controller) IRQ GTE
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-----------------------------------------
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This GTE instance timestamps LIC IRQ lines in real time. There are 352 IRQ
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lines which this instance can add timestamps to in real time. The hte
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devicetree binding described at ``Documentation/devicetree/bindings/timestamp``
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This GTE instance timestamps LIC IRQ lines in real time. The hte devicetree
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binding described at ``Documentation/devicetree/bindings/timestamp``
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provides an example of how a consumer can request an IRQ line. Since it is a
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one-to-one mapping with IRQ GTE provider, consumers can simply specify the IRQ
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number that they are interested in. There is no userspace consumer support for
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@ -9489,6 +9489,9 @@ F: drivers/input/touchscreen/htcpen.c
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HTE SUBSYSTEM
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M: Dipen Patel <dipenp@nvidia.com>
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L: timestamp@lists.linux.dev
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux.git
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Q: https://patchwork.kernel.org/project/timestamp/list/
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S: Maintained
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F: Documentation/devicetree/bindings/timestamp/
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F: Documentation/driver-api/hte/
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@ -1154,6 +1154,14 @@
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clock-names = "fuse";
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};
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hte_lic: hardware-timestamp@3aa0000 {
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compatible = "nvidia,tegra234-gte-lic";
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reg = <0x0 0x3aa0000 0x0 0x10000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,int-threshold = <1>;
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#timestamp-cells = <1>;
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};
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hsp_top0: hsp@3c00000 {
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compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
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reg = <0x0 0x03c00000 0x0 0xa0000>;
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@ -1671,6 +1679,15 @@
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#mbox-cells = <2>;
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};
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hte_aon: hardware-timestamp@c1e0000 {
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compatible = "nvidia,tegra234-gte-aon";
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reg = <0x0 0xc1e0000 0x0 0x10000>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,int-threshold = <1>;
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nvidia,gpio-controller = <&gpio_aon>;
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#timestamp-cells = <1>;
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};
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gen2_i2c: i2c@c240000 {
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compatible = "nvidia,tegra194-i2c";
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reg = <0x0 0xc240000 0x0 0x100>;
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@ -1134,6 +1134,7 @@ static const struct tegra_gpio_soc tegra234_aon_soc = {
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.name = "tegra234-gpio-aon",
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.instance = 1,
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.num_irqs_per_bank = 8,
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.has_gte = true,
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};
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#define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
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@ -16,7 +16,7 @@
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#include <linux/workqueue.h>
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/*
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* This sample HTE GPIO test driver demonstrates HTE API usage by enabling
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* This sample HTE test driver demonstrates HTE API usage by enabling
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* hardware timestamp on gpio_in and specified LIC IRQ lines.
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*
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* Note: gpio_out and gpio_in need to be shorted externally in order for this
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@ -62,6 +62,10 @@
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#define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25
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#define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26
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#define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27
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#define NV_AON_HTE_SLICE2_IRQ_GPIO_28 28
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#define NV_AON_HTE_SLICE2_IRQ_GPIO_29 29
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#define NV_AON_HTE_SLICE2_IRQ_GPIO_30 30
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#define NV_AON_HTE_SLICE2_IRQ_GPIO_31 31
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#define HTE_TECTRL 0x0
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#define HTE_TETSCH 0x4
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@ -114,6 +118,7 @@ struct tegra_hte_line_data {
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struct tegra_hte_data {
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enum tegra_hte_type type;
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u32 slices;
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u32 map_sz;
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u32 sec_map_sz;
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const struct tegra_hte_line_mapped *map;
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@ -220,18 +225,129 @@ static const struct tegra_hte_line_mapped tegra194_aon_gpio_sec_map[] = {
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[39] = {NV_AON_SLICE_INVALID, 0},
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};
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static const struct tegra_hte_data aon_hte = {
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static const struct tegra_hte_line_mapped tegra234_aon_gpio_map[] = {
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/* gpio, slice, bit_index */
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/* AA port */
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[0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
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[1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
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[2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
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[3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
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[4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
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[5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
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[6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
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[7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
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/* BB port */
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[8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
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[9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
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[10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
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[11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
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/* CC port */
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[12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
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[13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
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[14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
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[15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
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[16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
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[17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
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[18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
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[19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
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/* DD port */
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[20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
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[21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
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[22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
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/* EE port */
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[23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31},
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[24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30},
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[25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
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[26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
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[27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
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[28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
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[29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
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[30] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
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/* GG port */
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[31] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
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};
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static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = {
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/* gpio, slice, bit_index */
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/* AA port */
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[0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
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[1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
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[2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
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[3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
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[4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
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[5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
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[6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
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[7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
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/* BB port */
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[8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
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[9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
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[10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
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[11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
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[12] = {NV_AON_SLICE_INVALID, 0},
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[13] = {NV_AON_SLICE_INVALID, 0},
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[14] = {NV_AON_SLICE_INVALID, 0},
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[15] = {NV_AON_SLICE_INVALID, 0},
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/* CC port */
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[16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
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[17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
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[18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
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[19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
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[20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
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[21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
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[22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
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[23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
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/* DD port */
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[24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
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[25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
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[26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
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[27] = {NV_AON_SLICE_INVALID, 0},
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[28] = {NV_AON_SLICE_INVALID, 0},
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[29] = {NV_AON_SLICE_INVALID, 0},
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[30] = {NV_AON_SLICE_INVALID, 0},
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[31] = {NV_AON_SLICE_INVALID, 0},
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/* EE port */
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[32] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31},
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[33] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30},
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[34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
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[35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
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[36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
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[37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
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[38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
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[39] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
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/* GG port */
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[40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
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};
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static const struct tegra_hte_data t194_aon_hte = {
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.map_sz = ARRAY_SIZE(tegra194_aon_gpio_map),
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.map = tegra194_aon_gpio_map,
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.sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map),
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.sec_map = tegra194_aon_gpio_sec_map,
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.type = HTE_TEGRA_TYPE_GPIO,
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.slices = 3,
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};
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static const struct tegra_hte_data lic_hte = {
|
||||
static const struct tegra_hte_data t234_aon_hte = {
|
||||
.map_sz = ARRAY_SIZE(tegra234_aon_gpio_map),
|
||||
.map = tegra234_aon_gpio_map,
|
||||
.sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map),
|
||||
.sec_map = tegra234_aon_gpio_sec_map,
|
||||
.type = HTE_TEGRA_TYPE_GPIO,
|
||||
.slices = 3,
|
||||
};
|
||||
|
||||
static const struct tegra_hte_data t194_lic_hte = {
|
||||
.map_sz = 0,
|
||||
.map = NULL,
|
||||
.type = HTE_TEGRA_TYPE_LIC,
|
||||
.slices = 11,
|
||||
};
|
||||
|
||||
static const struct tegra_hte_data t234_lic_hte = {
|
||||
.map_sz = 0,
|
||||
.map = NULL,
|
||||
.type = HTE_TEGRA_TYPE_LIC,
|
||||
.slices = 17,
|
||||
};
|
||||
|
||||
static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg)
|
||||
@ -251,7 +367,7 @@ static int tegra_hte_map_to_line_id(u32 eid,
|
||||
{
|
||||
|
||||
if (m) {
|
||||
if (eid > map_sz)
|
||||
if (eid >= map_sz)
|
||||
return -EINVAL;
|
||||
if (m[eid].slice == NV_AON_SLICE_INVALID)
|
||||
return -EINVAL;
|
||||
@ -534,8 +650,10 @@ static bool tegra_hte_match_from_linedata(const struct hte_chip *chip,
|
||||
}
|
||||
|
||||
static const struct of_device_id tegra_hte_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte},
|
||||
{ .compatible = "nvidia,tegra194-gte-aon", .data = &aon_hte},
|
||||
{ .compatible = "nvidia,tegra194-gte-lic", .data = &t194_lic_hte},
|
||||
{ .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte},
|
||||
{ .compatible = "nvidia,tegra234-gte-lic", .data = &t234_lic_hte},
|
||||
{ .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte},
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, tegra_hte_of_match);
|
||||
@ -561,6 +679,11 @@ static int tegra_get_gpiochip_from_name(struct gpio_chip *chip, void *data)
|
||||
return !strcmp(chip->label, data);
|
||||
}
|
||||
|
||||
static int tegra_gpiochip_match(struct gpio_chip *chip, void *data)
|
||||
{
|
||||
return chip->fwnode == of_node_to_fwnode(data);
|
||||
}
|
||||
|
||||
static int tegra_hte_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
@ -569,16 +692,10 @@ static int tegra_hte_probe(struct platform_device *pdev)
|
||||
struct device *dev;
|
||||
struct tegra_hte_soc *hte_dev;
|
||||
struct hte_chip *gc;
|
||||
struct device_node *gpio_ctrl;
|
||||
|
||||
dev = &pdev->dev;
|
||||
|
||||
ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices);
|
||||
if (ret != 0) {
|
||||
dev_err(dev, "Could not read slices\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
nlines = slices << 5;
|
||||
|
||||
hte_dev = devm_kzalloc(dev, sizeof(*hte_dev), GFP_KERNEL);
|
||||
if (!hte_dev)
|
||||
return -ENOMEM;
|
||||
@ -590,6 +707,13 @@ static int tegra_hte_probe(struct platform_device *pdev)
|
||||
dev_set_drvdata(&pdev->dev, hte_dev);
|
||||
hte_dev->prov_data = of_device_get_match_data(&pdev->dev);
|
||||
|
||||
ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices);
|
||||
if (ret != 0)
|
||||
slices = hte_dev->prov_data->slices;
|
||||
|
||||
dev_dbg(dev, "slices:%d\n", slices);
|
||||
nlines = slices << 5;
|
||||
|
||||
hte_dev->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(hte_dev->regs))
|
||||
return PTR_ERR(hte_dev->regs);
|
||||
@ -635,8 +759,25 @@ static int tegra_hte_probe(struct platform_device *pdev)
|
||||
|
||||
gc->match_from_linedata = tegra_hte_match_from_linedata;
|
||||
|
||||
hte_dev->c = gpiochip_find("tegra194-gpio-aon",
|
||||
tegra_get_gpiochip_from_name);
|
||||
if (of_device_is_compatible(dev->of_node,
|
||||
"nvidia,tegra194-gte-aon")) {
|
||||
hte_dev->c = gpiochip_find("tegra194-gpio-aon",
|
||||
tegra_get_gpiochip_from_name);
|
||||
} else {
|
||||
gpio_ctrl = of_parse_phandle(dev->of_node,
|
||||
"nvidia,gpio-controller",
|
||||
0);
|
||||
if (!gpio_ctrl) {
|
||||
dev_err(dev,
|
||||
"gpio controller node not found\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
hte_dev->c = gpiochip_find(gpio_ctrl,
|
||||
tegra_gpiochip_match);
|
||||
of_node_put(gpio_ctrl);
|
||||
}
|
||||
|
||||
if (!hte_dev->c)
|
||||
return dev_err_probe(dev, -EPROBE_DEFER,
|
||||
"wait for gpio controller\n");
|
||||
|
||||
@ -444,7 +444,7 @@ static struct hte_device *of_node_to_htedevice(struct device_node *np)
|
||||
|
||||
list_for_each_entry(gdev, &hte_devices, list)
|
||||
if (gdev->chip && gdev->chip->dev &&
|
||||
gdev->chip->dev->of_node == np) {
|
||||
device_match_of_node(gdev->chip->dev, np)) {
|
||||
spin_unlock(&hte_lock);
|
||||
return gdev;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user