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perf report: Add support to print a textual representation of IBS raw sample data
Perf records IBS (Instruction Based Sampling) extra sample data when 'perf record --raw-samples' is used with an IBS-compatible event, on a machine that supports IBS. IBS support is indicated in CPUID_Fn80000001_ECX bit #10. Up until now, users have been able to see the extra sample data solely in raw hex format using 'perf report --dump-raw-trace'. From there, users could decode the data either manually, or by using an external script. Enable the built-in 'perf report --dump-raw-trace' to do the decoding of the extra sample data bits, so manual or external script decoding isn't necessary. Example usage: $ sudo perf record -c 10000001 -a --raw-samples -e ibs_fetch/rand_en=1/,ibs_op/cnt_ctl=1/ -C 0,1 taskset -c 0,1 7za b -mmt2 | perf report --dump-raw-trace Stdout contains IBS Fetch samples, e.g.: ibs_fetch_ctl: 02170007ffffffff MaxCnt 1048560 Cnt 1048560 Lat 7 En 1 Val 1 Comp 1 IcMiss 0 PhyAddrValid 1 L1TlbPgSz 4KB L1TlbMiss 0 L2TlbMiss 0 RandEn 1 L2Miss 0 IbsFetchLinAd: 000056016b2ead40 IbsFetchPhysAd: 000000115cedfd40 c_ibs_ext_ctl: 0000000000000000 IbsItlbRefillLat 0 ..and IBS Op samples, e.g.: ibs_op_ctl: 0000009e009e8968 MaxCnt 10000000 En 1 Val 1 CntCtl 1=uOps CurCnt 158 IbsOpRip: 000056016b2ea73d ibs_op_data: 00000000000b0002 CompToRetCtr 2 TagToRetCtr 11 BrnRet 0 RipInvalid 0 BrnFuse 0 Microcode 0 ibs_op_data2: 0000000000000002 CacheHitSt 0=M-state RmtNode 0 DataSrc 2=Local node cache ibs_op_data3: 0000000000c60002 LdOp 0 StOp 1 DcL1TlbMiss 0 DcL2TlbMiss 0 DcL1TlbHit2M 0 DcL1TlbHit1G 0 DcL2TlbHit2M 0 DcMiss 0 DcMisAcc 0 DcWcMemAcc 0 DcUcMemAcc 0 DcLockedOp 0 DcMissNoMabAlloc 0 DcLinAddrValid 1 DcPhyAddrValid 1 DcL2TlbHit1G 0 L2Miss 0 SwPf 0 OpMemWidth 4 bytes OpDcMissOpenMemReqs 0 DcMissLat 0 TlbRefillLat 0 IbsDCLinAd: 00007f133c319ce0 IbsDCPhysAd: 0000000270485ce0 Committer notes: Fixed up this: util/amd-sample-raw.c: In function ‘evlist__amd_sample_raw’: util/amd-sample-raw.c:125:42: error: ‘ bytes’ directive output may be truncated writing 6 bytes into a region of size between 4 and 7 [-Werror=format-truncation=] 125 | " OpMemWidth %2d bytes", 1 << (reg.op_mem_width - 1)); | ^~~~~~ In file included from /usr/include/stdio.h:866, from util/amd-sample-raw.c:7: /usr/include/bits/stdio2.h:71:10: note: ‘__builtin___snprintf_chk’ output between 21 and 24 bytes into a destination of size 21 71 | return __builtin___snprintf_chk (__s, __n, __USE_FORTIFY_LEVEL - 1, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 72 | __glibc_objsize (__s), __fmt, | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 73 | __va_arg_pack ()); | ~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors As that %2d won't limit the number of chars to 2, just state that 2 is the minimal width: $ cat printf.c #include <stdio.h> #include <stdlib.h> int main(int argc, char *argv[]) { char bf[64]; int len = snprintf(bf, sizeof(bf), "%2d", atoi(argv[1])); printf("strlen(%s): %u\n", bf, len); return 0; } $ ./printf 1 strlen( 1): 2 $ ./printf 12 strlen(12): 2 $ ./printf 123 strlen(123): 3 $ ./printf 1234 strlen(1234): 4 $ ./printf 12345 strlen(12345): 5 $ ./printf 123456 strlen(123456): 6 $ And since we probably don't want that output to be truncated, just assume the worst case, as the compiler did, and add a few more chars to that buffer. Also use sizeof(var) instead of sizeof(dup-of-wanted-format-string) to avoid bugs when changing one but not the other. I also had to change this: -#include <asm/amd-ibs.h> +#include "../../arch/x86/include/asm/amd-ibs.h" To make it build on other architectures, just like intel-pt does. Signed-off-by: Kim Phillips <kim.phillips@amd.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Joao Martins <joao.m.martins@oracle.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Michael Petlan <mpetlan@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Robert Richter <robert.richter@amd.com> Cc: Stephane Eranian <eranian@google.com> Link: https //lore.kernel.org/r/20210817221509.88391-4-kim.phillips@amd.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Kim Phillips
Arnaldo Carvalho de Melo
parent
dde994dd54
commit
291dcb98d7
@ -59,6 +59,7 @@ perf-y += pstack.o
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perf-y += session.o
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perf-y += sample-raw.o
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perf-y += s390-sample-raw.o
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perf-y += amd-sample-raw.o
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perf-$(CONFIG_TRACE) += syscalltbl.o
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perf-y += ordered-events.o
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perf-y += namespaces.o
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289
tools/perf/util/amd-sample-raw.c
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289
tools/perf/util/amd-sample-raw.c
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@ -0,0 +1,289 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* AMD specific. Provide textual annotation for IBS raw sample data.
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*/
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#include <unistd.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include <linux/string.h>
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#include "../../arch/x86/include/asm/amd-ibs.h"
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#include "debug.h"
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#include "session.h"
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#include "evlist.h"
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#include "sample-raw.h"
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#include "pmu-events/pmu-events.h"
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static u32 cpu_family, cpu_model, ibs_fetch_type, ibs_op_type;
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static void pr_ibs_fetch_ctl(union ibs_fetch_ctl reg)
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{
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const char * const ic_miss_strs[] = {
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" IcMiss 0",
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" IcMiss 1",
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};
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const char * const l1tlb_pgsz_strs[] = {
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" L1TlbPgSz 4KB",
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" L1TlbPgSz 2MB",
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" L1TlbPgSz 1GB",
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" L1TlbPgSz RESERVED"
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};
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const char * const l1tlb_pgsz_strs_erratum1347[] = {
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" L1TlbPgSz 4KB",
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" L1TlbPgSz 16KB",
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" L1TlbPgSz 2MB",
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" L1TlbPgSz 1GB"
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};
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const char *ic_miss_str = NULL;
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const char *l1tlb_pgsz_str = NULL;
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if (cpu_family == 0x19 && cpu_model < 0x10) {
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/*
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* Erratum #1238 workaround is to ignore MSRC001_1030[IbsIcMiss]
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* Erratum #1347 workaround is to use table provided in erratum
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*/
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if (reg.phy_addr_valid)
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l1tlb_pgsz_str = l1tlb_pgsz_strs_erratum1347[reg.l1tlb_pgsz];
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} else {
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if (reg.phy_addr_valid)
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l1tlb_pgsz_str = l1tlb_pgsz_strs[reg.l1tlb_pgsz];
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ic_miss_str = ic_miss_strs[reg.ic_miss];
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}
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printf("ibs_fetch_ctl:\t%016llx MaxCnt %7d Cnt %7d Lat %5d En %d Val %d Comp %d%s "
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"PhyAddrValid %d%s L1TlbMiss %d L2TlbMiss %d RandEn %d%s\n",
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reg.val, reg.fetch_maxcnt << 4, reg.fetch_cnt << 4, reg.fetch_lat,
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reg.fetch_en, reg.fetch_val, reg.fetch_comp, ic_miss_str ? : "",
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reg.phy_addr_valid, l1tlb_pgsz_str ? : "", reg.l1tlb_miss, reg.l2tlb_miss,
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reg.rand_en, reg.fetch_comp ? (reg.fetch_l2_miss ? " L2Miss 1" : " L2Miss 0") : "");
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}
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static void pr_ic_ibs_extd_ctl(union ic_ibs_extd_ctl reg)
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{
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printf("ic_ibs_ext_ctl:\t%016llx IbsItlbRefillLat %3d\n", reg.val, reg.itlb_refill_lat);
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}
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static void pr_ibs_op_ctl(union ibs_op_ctl reg)
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{
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printf("ibs_op_ctl:\t%016llx MaxCnt %9d En %d Val %d CntCtl %d=%s CurCnt %9d\n",
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reg.val, ((reg.opmaxcnt_ext << 16) | reg.opmaxcnt) << 4, reg.op_en, reg.op_val,
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reg.cnt_ctl, reg.cnt_ctl ? "uOps" : "cycles", reg.opcurcnt);
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}
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static void pr_ibs_op_data(union ibs_op_data reg)
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{
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printf("ibs_op_data:\t%016llx CompToRetCtr %5d TagToRetCtr %5d%s%s%s BrnRet %d "
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" RipInvalid %d BrnFuse %d Microcode %d\n",
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reg.val, reg.comp_to_ret_ctr, reg.tag_to_ret_ctr,
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reg.op_brn_ret ? (reg.op_return ? " OpReturn 1" : " OpReturn 0") : "",
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reg.op_brn_ret ? (reg.op_brn_taken ? " OpBrnTaken 1" : " OpBrnTaken 0") : "",
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reg.op_brn_ret ? (reg.op_brn_misp ? " OpBrnMisp 1" : " OpBrnMisp 0") : "",
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reg.op_brn_ret, reg.op_rip_invalid, reg.op_brn_fuse, reg.op_microcode);
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}
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static void pr_ibs_op_data2(union ibs_op_data2 reg)
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{
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static const char * const data_src_str[] = {
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"",
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" DataSrc 1=(reserved)",
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" DataSrc 2=Local node cache",
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" DataSrc 3=DRAM",
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" DataSrc 4=Remote node cache",
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" DataSrc 5=(reserved)",
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" DataSrc 6=(reserved)",
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" DataSrc 7=Other"
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};
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printf("ibs_op_data2:\t%016llx %sRmtNode %d%s\n", reg.val,
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reg.data_src == 2 ? (reg.cache_hit_st ? "CacheHitSt 1=O-State "
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: "CacheHitSt 0=M-state ") : "",
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reg.rmt_node, data_src_str[reg.data_src]);
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}
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static void pr_ibs_op_data3(union ibs_op_data3 reg)
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{
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char l2_miss_str[sizeof(" L2Miss _")] = "";
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char op_mem_width_str[sizeof(" OpMemWidth _____ bytes")] = "";
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char op_dc_miss_open_mem_reqs_str[sizeof(" OpDcMissOpenMemReqs __")] = "";
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/*
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* Erratum #1293
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* Ignore L2Miss and OpDcMissOpenMemReqs (and opdata2) if DcMissNoMabAlloc or SwPf set
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*/
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if (!(cpu_family == 0x19 && cpu_model < 0x10 && (reg.dc_miss_no_mab_alloc || reg.sw_pf))) {
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snprintf(l2_miss_str, sizeof(l2_miss_str), " L2Miss %d", reg.l2_miss);
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snprintf(op_dc_miss_open_mem_reqs_str, sizeof(op_dc_miss_open_mem_reqs_str),
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" OpDcMissOpenMemReqs %2d", reg.op_dc_miss_open_mem_reqs);
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}
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if (reg.op_mem_width)
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snprintf(op_mem_width_str, sizeof(op_mem_width_str),
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" OpMemWidth %2d bytes", 1 << (reg.op_mem_width - 1));
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printf("ibs_op_data3:\t%016llx LdOp %d StOp %d DcL1TlbMiss %d DcL2TlbMiss %d "
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"DcL1TlbHit2M %d DcL1TlbHit1G %d DcL2TlbHit2M %d DcMiss %d DcMisAcc %d "
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"DcWcMemAcc %d DcUcMemAcc %d DcLockedOp %d DcMissNoMabAlloc %d DcLinAddrValid %d "
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"DcPhyAddrValid %d DcL2TlbHit1G %d%s SwPf %d%s%s DcMissLat %5d TlbRefillLat %5d\n",
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reg.val, reg.ld_op, reg.st_op, reg.dc_l1tlb_miss, reg.dc_l2tlb_miss,
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reg.dc_l1tlb_hit_2m, reg.dc_l1tlb_hit_1g, reg.dc_l2tlb_hit_2m, reg.dc_miss,
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reg.dc_mis_acc, reg.dc_wc_mem_acc, reg.dc_uc_mem_acc, reg.dc_locked_op,
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reg.dc_miss_no_mab_alloc, reg.dc_lin_addr_valid, reg.dc_phy_addr_valid,
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reg.dc_l2_tlb_hit_1g, l2_miss_str, reg.sw_pf, op_mem_width_str,
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op_dc_miss_open_mem_reqs_str, reg.dc_miss_lat, reg.tlb_refill_lat);
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}
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/*
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* IBS Op/Execution MSRs always saved, in order, are:
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* IBS_OP_CTL, IBS_OP_RIP, IBS_OP_DATA, IBS_OP_DATA2,
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* IBS_OP_DATA3, IBS_DC_LINADDR, IBS_DC_PHYSADDR, BP_IBSTGT_RIP
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*/
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static void amd_dump_ibs_op(struct perf_sample *sample)
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{
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struct perf_ibs_data *data = sample->raw_data;
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union ibs_op_ctl *op_ctl = (union ibs_op_ctl *)data->data;
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__u64 *rip = (__u64 *)op_ctl + 1;
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union ibs_op_data *op_data = (union ibs_op_data *)(rip + 1);
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union ibs_op_data3 *op_data3 = (union ibs_op_data3 *)(rip + 3);
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pr_ibs_op_ctl(*op_ctl);
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if (!op_data->op_rip_invalid)
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printf("IbsOpRip:\t%016llx\n", *rip);
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pr_ibs_op_data(*op_data);
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/*
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* Erratum #1293: ignore op_data2 if DcMissNoMabAlloc or SwPf are set
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*/
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if (!(cpu_family == 0x19 && cpu_model < 0x10 &&
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(op_data3->dc_miss_no_mab_alloc || op_data3->sw_pf)))
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pr_ibs_op_data2(*(union ibs_op_data2 *)(rip + 2));
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pr_ibs_op_data3(*op_data3);
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if (op_data3->dc_lin_addr_valid)
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printf("IbsDCLinAd:\t%016llx\n", *(rip + 4));
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if (op_data3->dc_phy_addr_valid)
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printf("IbsDCPhysAd:\t%016llx\n", *(rip + 5));
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if (op_data->op_brn_ret && *(rip + 6))
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printf("IbsBrTarget:\t%016llx\n", *(rip + 6));
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}
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/*
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* IBS Fetch MSRs always saved, in order, are:
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* IBS_FETCH_CTL, IBS_FETCH_LINADDR, IBS_FETCH_PHYSADDR, IC_IBS_EXTD_CTL
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*/
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static void amd_dump_ibs_fetch(struct perf_sample *sample)
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{
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struct perf_ibs_data *data = sample->raw_data;
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union ibs_fetch_ctl *fetch_ctl = (union ibs_fetch_ctl *)data->data;
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__u64 *addr = (__u64 *)fetch_ctl + 1;
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union ic_ibs_extd_ctl *extd_ctl = (union ic_ibs_extd_ctl *)addr + 2;
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pr_ibs_fetch_ctl(*fetch_ctl);
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printf("IbsFetchLinAd:\t%016llx\n", *addr++);
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if (fetch_ctl->phy_addr_valid)
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printf("IbsFetchPhysAd:\t%016llx\n", *addr);
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pr_ic_ibs_extd_ctl(*extd_ctl);
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}
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/*
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* Test for enable and valid bits in captured control MSRs.
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*/
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static bool is_valid_ibs_fetch_sample(struct perf_sample *sample)
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{
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struct perf_ibs_data *data = sample->raw_data;
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union ibs_fetch_ctl *fetch_ctl = (union ibs_fetch_ctl *)data->data;
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if (fetch_ctl->fetch_en && fetch_ctl->fetch_val)
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return true;
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return false;
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}
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static bool is_valid_ibs_op_sample(struct perf_sample *sample)
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{
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struct perf_ibs_data *data = sample->raw_data;
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union ibs_op_ctl *op_ctl = (union ibs_op_ctl *)data->data;
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if (op_ctl->op_en && op_ctl->op_val)
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return true;
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return false;
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}
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/* AMD vendor specific raw sample function. Check for PERF_RECORD_SAMPLE events
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* and if the event was triggered by IBS, display its raw data with decoded text.
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* The function is only invoked when the dump flag -D is set.
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*/
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void evlist__amd_sample_raw(struct evlist *evlist, union perf_event *event,
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struct perf_sample *sample)
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{
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struct evsel *evsel;
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if (event->header.type != PERF_RECORD_SAMPLE || !sample->raw_size)
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return;
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evsel = evlist__event2evsel(evlist, event);
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if (!evsel)
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return;
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if (evsel->core.attr.type == ibs_fetch_type) {
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if (!is_valid_ibs_fetch_sample(sample)) {
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pr_debug("Invalid raw IBS Fetch MSR data encountered\n");
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return;
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}
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amd_dump_ibs_fetch(sample);
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} else if (evsel->core.attr.type == ibs_op_type) {
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if (!is_valid_ibs_op_sample(sample)) {
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pr_debug("Invalid raw IBS Op MSR data encountered\n");
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return;
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}
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amd_dump_ibs_op(sample);
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}
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}
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static void parse_cpuid(struct perf_env *env)
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{
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const char *cpuid;
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int ret;
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cpuid = perf_env__cpuid(env);
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/*
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* cpuid = "AuthenticAMD,family,model,stepping"
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*/
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ret = sscanf(cpuid, "%*[^,],%u,%u", &cpu_family, &cpu_model);
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if (ret != 2)
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pr_debug("problem parsing cpuid\n");
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}
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/*
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* Find and assign the type number used for ibs_op or ibs_fetch samples.
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* Device names can be large - we are only interested in the first 9 characters,
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* to match "ibs_fetch".
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*/
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bool evlist__has_amd_ibs(struct evlist *evlist)
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{
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struct perf_env *env = evlist->env;
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int ret, nr_pmu_mappings = perf_env__nr_pmu_mappings(env);
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const char *pmu_mapping = perf_env__pmu_mappings(env);
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char name[sizeof("ibs_fetch")];
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u32 type;
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while (nr_pmu_mappings--) {
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ret = sscanf(pmu_mapping, "%u:%9s", &type, name);
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if (ret == 2) {
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if (strstarts(name, "ibs_op"))
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ibs_op_type = type;
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else if (strstarts(name, "ibs_fetch"))
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ibs_fetch_type = type;
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}
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pmu_mapping += strlen(pmu_mapping) + 1 /* '\0' */;
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}
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if (ibs_fetch_type || ibs_op_type) {
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if (!cpu_family)
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parse_cpuid(env);
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return true;
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}
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return false;
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}
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@ -1,8 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#include <string.h>
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#include <linux/string.h>
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#include "evlist.h"
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#include "env.h"
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#include "header.h"
|
||||
#include "sample-raw.h"
|
||||
|
||||
/*
|
||||
@ -12,7 +14,13 @@
|
||||
void evlist__init_trace_event_sample_raw(struct evlist *evlist)
|
||||
{
|
||||
const char *arch_pf = perf_env__arch(evlist->env);
|
||||
const char *cpuid = perf_env__cpuid(evlist->env);
|
||||
|
||||
if (arch_pf && !strcmp("s390", arch_pf))
|
||||
evlist->trace_event_sample_raw = evlist__s390_sample_raw;
|
||||
else if (arch_pf && !strcmp("x86", arch_pf) &&
|
||||
cpuid && strstarts(cpuid, "AuthenticAMD") &&
|
||||
evlist__has_amd_ibs(evlist)) {
|
||||
evlist->trace_event_sample_raw = evlist__amd_sample_raw;
|
||||
}
|
||||
}
|
||||
|
||||
@ -6,6 +6,10 @@ struct evlist;
|
||||
union perf_event;
|
||||
struct perf_sample;
|
||||
|
||||
void evlist__s390_sample_raw(struct evlist *evlist, union perf_event *event, struct perf_sample *sample);
|
||||
void evlist__s390_sample_raw(struct evlist *evlist, union perf_event *event,
|
||||
struct perf_sample *sample);
|
||||
bool evlist__has_amd_ibs(struct evlist *evlist);
|
||||
void evlist__amd_sample_raw(struct evlist *evlist, union perf_event *event,
|
||||
struct perf_sample *sample);
|
||||
void evlist__init_trace_event_sample_raw(struct evlist *evlist);
|
||||
#endif /* __PERF_EVLIST_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user