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MIPS: Alchemy: get rid of allow_au1k_wait
Eliminate the 'allow_au1k_wait' variable. MIPS kernel installs the Alchemy-specific wait code before timer initialization; if the C0 timer must be used for timekeeping the wait function is set to NULL which means no wait implementation is available. As a sideeffect, the 'wait instruction available' output in /proc/cpuinfo now correctly indicates whether 'wait' is usable. Run-tested on DB1200. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -36,14 +36,13 @@
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <asm/processor.h>
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#include <asm/time.h>
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#include <asm/mach-au1x00/au1000.h>
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/* 32kHz clock enabled and detected */
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#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
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extern int allow_au1k_wait; /* default off for CP0 Counter */
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static cycle_t au1x_counter1_read(struct clocksource *cs)
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{
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return au_readl(SYS_RTCREAD);
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@ -153,13 +152,17 @@ void __init plat_time_init(void)
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printk(KERN_INFO "Alchemy clocksource installed\n");
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/* can now use 'wait' */
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allow_au1k_wait = 1;
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return;
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cntr_err:
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/* counters unusable, use C0 counter */
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/*
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* MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this
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* function is called. Because the Alchemy counters are unusable
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* the C0 timekeeping code is installed and use of the 'wait'
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* instruction must be prohibited, which is done most easily by
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* assigning NULL to cpu_wait.
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*/
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cpu_wait = NULL;
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r4k_clockevent_init();
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init_r4k_clocksource();
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allow_au1k_wait = 0;
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}
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@ -91,16 +91,13 @@ static void rm7k_wait_irqoff(void)
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local_irq_enable();
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}
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/* The Au1xxx wait is available only if using 32khz counter or
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* external timer source, but specifically not CP0 Counter. */
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int allow_au1k_wait;
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/*
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* The Au1xxx wait is available only if using 32khz counter or
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* external timer source, but specifically not CP0 Counter.
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* alchemy/common/time.c may override cpu_wait!
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*/
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static void au1k_wait(void)
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{
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if (!allow_au1k_wait)
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return;
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/* using the wait instruction makes CP0 counter unusable */
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__asm__(" .set mips3 \n"
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" cache 0x14, 0(%0) \n"
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" cache 0x14, 32(%0) \n"
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