From 27fd82726995bd75b68df9ce6a1eda8f6b3ad498 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Tue, 21 Feb 2023 12:24:35 +0300 Subject: [PATCH] mips: ralink: make SOC_MT7621 select PINCTRL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, out of every Ralink SoC, only the dt-binding of the MT7621 SoC uses pinctrl. Because of this, PINCTRL is not selected at all. Make SOC_MT7621 select PINCTRL. Remove PINCTRL_MT7621, enabling it for the MT7621 SoC will be handled under the PINCTRL_MT7621 option. Signed-off-by: Arınç ÜNAL Acked-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/ralink/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index 06031796c87b..83e61e147b90 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -54,7 +54,7 @@ choice select HAVE_PCI select PCI_DRIVERS_GENERIC select SOC_BUS - select PINCTRL_MT7621 + select PINCTRL help The MT7621 system-on-a-chip includes an 880 MHz MIPS1004Kc