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Merge branch 'master' of git://git.infradead.org/users/rafal/b43-next
This commit is contained in:
John W. Linville
commit
27eee235de
@ -30,6 +30,17 @@
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#include "radio_2059.h"
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#include "main.h"
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/* Force values to keep compatibility with wl */
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enum ht_rssi_type {
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HT_RSSI_W1 = 0,
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HT_RSSI_W2 = 1,
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HT_RSSI_NB = 2,
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HT_RSSI_IQ = 3,
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HT_RSSI_TSSI_2G = 4,
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HT_RSSI_TSSI_5G = 5,
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HT_RSSI_TBD = 6,
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};
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/**************************************************
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* Radio 2059.
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**************************************************/
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@ -37,8 +48,9 @@
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static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
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const struct b43_phy_ht_channeltab_e_radio2059 *e)
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{
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u8 i;
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u16 routing;
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static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3, };
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u16 r;
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int core;
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b43_radio_write(dev, 0x16, e->radio_syn16);
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b43_radio_write(dev, 0x17, e->radio_syn17);
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@ -53,25 +65,17 @@ static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
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b43_radio_write(dev, 0x41, e->radio_syn41);
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b43_radio_write(dev, 0x43, e->radio_syn43);
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b43_radio_write(dev, 0x47, e->radio_syn47);
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b43_radio_write(dev, 0x4a, e->radio_syn4a);
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b43_radio_write(dev, 0x58, e->radio_syn58);
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b43_radio_write(dev, 0x5a, e->radio_syn5a);
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b43_radio_write(dev, 0x6a, e->radio_syn6a);
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b43_radio_write(dev, 0x6d, e->radio_syn6d);
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b43_radio_write(dev, 0x6e, e->radio_syn6e);
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b43_radio_write(dev, 0x92, e->radio_syn92);
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b43_radio_write(dev, 0x98, e->radio_syn98);
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for (i = 0; i < 2; i++) {
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routing = i ? R2059_RXRX1 : R2059_TXRX0;
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b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
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b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
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b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
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b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a);
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b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d);
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b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e);
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b43_radio_write(dev, routing | 0x92, e->radio_rxtx92);
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b43_radio_write(dev, routing | 0x98, e->radio_rxtx98);
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for (core = 0; core < 3; core++) {
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r = routing[core];
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b43_radio_write(dev, r | 0x4a, e->radio_rxtx4a);
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b43_radio_write(dev, r | 0x58, e->radio_rxtx58);
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b43_radio_write(dev, r | 0x5a, e->radio_rxtx5a);
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b43_radio_write(dev, r | 0x6a, e->radio_rxtx6a);
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b43_radio_write(dev, r | 0x6d, e->radio_rxtx6d);
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b43_radio_write(dev, r | 0x6e, e->radio_rxtx6e);
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b43_radio_write(dev, r | 0x92, e->radio_rxtx92);
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b43_radio_write(dev, r | 0x98, e->radio_rxtx98);
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}
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udelay(50);
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@ -87,7 +91,7 @@ static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
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static void b43_radio_2059_init(struct b43_wldev *dev)
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{
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const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 };
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const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3 };
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const u16 radio_values[3][2] = {
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{ 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
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};
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@ -106,17 +110,17 @@ static void b43_radio_2059_init(struct b43_wldev *dev)
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b43_radio_mask(dev, 0xc0, ~0x0080);
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if (1) { /* FIXME */
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b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x1);
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b43_radio_set(dev, R2059_C3 | 0x4, 0x1);
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udelay(10);
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b43_radio_set(dev, R2059_RXRX1 | 0x0BF, 0x1);
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b43_radio_maskset(dev, R2059_RXRX1 | 0x19B, 0x3, 0x2);
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b43_radio_set(dev, R2059_C3 | 0x0BF, 0x1);
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b43_radio_maskset(dev, R2059_C3 | 0x19B, 0x3, 0x2);
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b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x2);
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b43_radio_set(dev, R2059_C3 | 0x4, 0x2);
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udelay(100);
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b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x2);
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b43_radio_mask(dev, R2059_C3 | 0x4, ~0x2);
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for (i = 0; i < 10000; i++) {
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if (b43_radio_read(dev, R2059_RXRX1 | 0x145) & 1) {
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if (b43_radio_read(dev, R2059_C3 | 0x145) & 1) {
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i = 0;
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break;
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}
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@ -125,7 +129,7 @@ static void b43_radio_2059_init(struct b43_wldev *dev)
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if (i)
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b43err(dev->wl, "radio 0x945 timeout\n");
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b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x1);
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b43_radio_mask(dev, R2059_C3 | 0x4, ~0x1);
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b43_radio_set(dev, 0xa, 0x60);
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for (i = 0; i < 3; i++) {
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@ -390,14 +394,14 @@ static void b43_phy_ht_tx_tone(struct b43_wldev *dev)
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**************************************************/
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static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
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u8 rssi_type)
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enum ht_rssi_type rssi_type)
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{
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static const u16 ctl_regs[3][2] = {
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{ B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER, },
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{ B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER, },
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{ B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER, },
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};
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static const u16 radio_r[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1, };
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static const u16 radio_r[] = { R2059_C1, R2059_C2, R2059_C3, };
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int core;
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if (core_sel == 0) {
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@ -411,13 +415,13 @@ static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
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continue;
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switch (rssi_type) {
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case 4:
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case HT_RSSI_TSSI_2G:
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b43_phy_set(dev, ctl_regs[core][0], 0x3 << 8);
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b43_phy_set(dev, ctl_regs[core][0], 0x3 << 10);
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b43_phy_set(dev, ctl_regs[core][1], 0x1 << 9);
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b43_phy_set(dev, ctl_regs[core][1], 0x1 << 10);
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b43_radio_set(dev, R2059_RXRX1 | 0xbf, 0x1);
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b43_radio_set(dev, R2059_C3 | 0xbf, 0x1);
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b43_radio_write(dev, radio_r[core] | 0x159,
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0x11);
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break;
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@ -429,8 +433,8 @@ static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
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}
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}
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static void b43_phy_ht_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
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u8 nsamp)
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static void b43_phy_ht_poll_rssi(struct b43_wldev *dev, enum ht_rssi_type type,
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s32 *buf, u8 nsamp)
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{
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u16 phy_regs_values[12];
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static const u16 phy_regs_to_save[] = {
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@ -504,15 +508,17 @@ static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable)
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static const u16 cmd_regs[3] = { B43_PHY_HT_TXPCTL_CMD_C1,
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B43_PHY_HT_TXPCTL_CMD_C2,
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B43_PHY_HT_TXPCTL_CMD_C3 };
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static const u16 status_regs[3] = { B43_PHY_HT_TX_PCTL_STATUS_C1,
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B43_PHY_HT_TX_PCTL_STATUS_C2,
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B43_PHY_HT_TX_PCTL_STATUS_C3 };
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int i;
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if (!enable) {
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if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) {
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/* We disable enabled TX pwr ctl, save it's state */
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/*
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* TODO: find the registers. On N-PHY they were 0x1ed
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* and 0x1ee, we need 3 such a registers for HT-PHY
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*/
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for (i = 0; i < 3; i++)
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phy_ht->tx_pwr_idx[i] =
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b43_phy_read(dev, status_regs[i]);
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}
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b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits);
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} else {
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@ -536,13 +542,25 @@ static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable)
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static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
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{
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struct b43_phy_ht *phy_ht = dev->phy.ht;
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static const u16 base[] = { 0x840, 0x860, 0x880 };
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u16 save_regs[3][3];
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s32 rssi_buf[6];
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int core;
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/* TODO */
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for (core = 0; core < 3; core++) {
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save_regs[core][1] = b43_phy_read(dev, base[core] + 6);
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save_regs[core][2] = b43_phy_read(dev, base[core] + 7);
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save_regs[core][0] = b43_phy_read(dev, base[core] + 0);
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b43_phy_write(dev, base[core] + 6, 0);
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b43_phy_mask(dev, base[core] + 7, ~0xF); /* 0xF? Or just 0x6? */
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b43_phy_set(dev, base[core] + 0, 0x0400);
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b43_phy_set(dev, base[core] + 0, 0x1000);
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}
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b43_phy_ht_tx_tone(dev);
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udelay(20);
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b43_phy_ht_poll_rssi(dev, 4, rssi_buf, 1);
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b43_phy_ht_poll_rssi(dev, HT_RSSI_TSSI_2G, rssi_buf, 1);
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b43_phy_ht_stop_playback(dev);
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b43_phy_ht_reset_cca(dev);
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@ -550,7 +568,23 @@ static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
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phy_ht->idle_tssi[1] = rssi_buf[2] & 0xff;
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phy_ht->idle_tssi[2] = rssi_buf[4] & 0xff;
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/* TODO */
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for (core = 0; core < 3; core++) {
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b43_phy_write(dev, base[core] + 0, save_regs[core][0]);
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b43_phy_write(dev, base[core] + 6, save_regs[core][1]);
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b43_phy_write(dev, base[core] + 7, save_regs[core][2]);
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}
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}
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static void b43_phy_ht_tssi_setup(struct b43_wldev *dev)
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{
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static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3, };
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int core;
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/* 0x159 is probably TX_SSI_MUX or TSSIG (by comparing to N-PHY) */
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for (core = 0; core < 3; core++) {
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b43_radio_set(dev, 0x8bf, 0x1);
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b43_radio_write(dev, routing[core] | 0x0159, 0x0011);
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}
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}
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static void b43_phy_ht_tx_power_ctl_setup(struct b43_wldev *dev)
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@ -946,6 +980,7 @@ static int b43_phy_ht_op_init(struct b43_wldev *dev)
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b43_phy_ht_tx_power_ctl(dev, false);
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b43_phy_ht_tx_power_ctl_idle_tssi(dev);
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b43_phy_ht_tx_power_ctl_setup(dev);
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b43_phy_ht_tssi_setup(dev);
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b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl);
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return 0;
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@ -23,6 +23,9 @@
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#define B43_PHY_HT_SAMP_WAIT_CNT 0x0C5 /* Sample wait count */
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#define B43_PHY_HT_SAMP_DEP_CNT 0x0C6 /* Sample depth count */
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#define B43_PHY_HT_SAMP_STAT 0x0C7 /* Sample status */
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#define B43_PHY_HT_EST_PWR_C1 0x118
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#define B43_PHY_HT_EST_PWR_C2 0x119
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#define B43_PHY_HT_EST_PWR_C3 0x11A
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#define B43_PHY_HT_TSSIMODE 0x122 /* TSSI mode */
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#define B43_PHY_HT_TSSIMODE_EN 0x0001 /* TSSI enable */
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#define B43_PHY_HT_TSSIMODE_PDEN 0x0002 /* Power det enable */
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@ -53,6 +56,8 @@
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#define B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT 0
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#define B43_PHY_HT_TXPCTL_TARG_PWR_C2 0xFF00 /* Power 1 */
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#define B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT 8
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#define B43_PHY_HT_TX_PCTL_STATUS_C1 0x1ED
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#define B43_PHY_HT_TX_PCTL_STATUS_C2 0x1EE
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#define B43_PHY_HT_TXPCTL_CMD_C2 0x222
|
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#define B43_PHY_HT_TXPCTL_CMD_C2_INIT 0x007F
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#define B43_PHY_HT_RSSI_C1 0x219
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@ -97,6 +102,7 @@
|
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#define B43_PHY_HT_TXPCTL_TARG_PWR2 B43_PHY_EXTG(0x166) /* TX power control target power */
|
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#define B43_PHY_HT_TXPCTL_TARG_PWR2_C3 0x00FF
|
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#define B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT 0
|
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#define B43_PHY_HT_TX_PCTL_STATUS_C3 B43_PHY_EXTG(0x169)
|
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|
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#define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A)
|
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|
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|
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@ -281,8 +281,8 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
|
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b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
|
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b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
|
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} else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
|
||||
(dev->dev->board_type == 0x048A) || ((dev->phy.rev == 0) &&
|
||||
(sprom->boardflags_lo & B43_BFL_FEM))) {
|
||||
(dev->dev->board_type == SSB_BOARD_BU4312) ||
|
||||
(dev->phy.rev == 0 && (sprom->boardflags_lo & B43_BFL_FEM))) {
|
||||
b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
|
||||
b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
|
||||
b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -54,10 +54,15 @@
|
||||
#define B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT 7
|
||||
#define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */
|
||||
#define B43_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */
|
||||
#define B43_NPHY_REV3_C1_INITGAIN_A B43_PHY_N(0x020)
|
||||
#define B43_NPHY_C1_CLIP1_HIGAIN B43_PHY_N(0x021) /* Core 1 clip1 high gain code */
|
||||
#define B43_NPHY_REV3_C1_INITGAIN_B B43_PHY_N(0x021)
|
||||
#define B43_NPHY_C1_CLIP1_MEDGAIN B43_PHY_N(0x022) /* Core 1 clip1 medium gain code */
|
||||
#define B43_NPHY_REV3_C1_CLIP_HIGAIN_A B43_PHY_N(0x022)
|
||||
#define B43_NPHY_C1_CLIP1_LOGAIN B43_PHY_N(0x023) /* Core 1 clip1 low gain code */
|
||||
#define B43_NPHY_REV3_C1_CLIP_HIGAIN_B B43_PHY_N(0x023)
|
||||
#define B43_NPHY_C1_CLIP2_GAIN B43_PHY_N(0x024) /* Core 1 clip2 gain code */
|
||||
#define B43_NPHY_REV3_C1_CLIP_MEDGAIN_A B43_PHY_N(0x024)
|
||||
#define B43_NPHY_C1_FILTERGAIN B43_PHY_N(0x025) /* Core 1 filter gain */
|
||||
#define B43_NPHY_C1_LPF_QHPF_BW B43_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */
|
||||
#define B43_NPHY_C1_CLIPWBTHRES B43_PHY_N(0x027) /* Core 1 clip wideband threshold */
|
||||
@ -107,10 +112,15 @@
|
||||
#define B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7
|
||||
#define B43_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */
|
||||
#define B43_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */
|
||||
#define B43_NPHY_REV3_C1_CLIP_MEDGAIN_B B43_PHY_N(0x036)
|
||||
#define B43_NPHY_C2_CLIP1_HIGAIN B43_PHY_N(0x037) /* Core 2 clip1 high gain code */
|
||||
#define B43_NPHY_REV3_C1_CLIP_LOGAIN_A B43_PHY_N(0x037)
|
||||
#define B43_NPHY_C2_CLIP1_MEDGAIN B43_PHY_N(0x038) /* Core 2 clip1 medium gain code */
|
||||
#define B43_NPHY_REV3_C1_CLIP_LOGAIN_B B43_PHY_N(0x038)
|
||||
#define B43_NPHY_C2_CLIP1_LOGAIN B43_PHY_N(0x039) /* Core 2 clip1 low gain code */
|
||||
#define B43_NPHY_REV3_C1_CLIP2_GAIN_A B43_PHY_N(0x039)
|
||||
#define B43_NPHY_C2_CLIP2_GAIN B43_PHY_N(0x03A) /* Core 2 clip2 gain code */
|
||||
#define B43_NPHY_REV3_C1_CLIP2_GAIN_B B43_PHY_N(0x03A)
|
||||
#define B43_NPHY_C2_FILTERGAIN B43_PHY_N(0x03B) /* Core 2 filter gain */
|
||||
#define B43_NPHY_C2_LPF_QHPF_BW B43_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */
|
||||
#define B43_NPHY_C2_CLIPWBTHRES B43_PHY_N(0x03D) /* Core 2 clip wideband threshold */
|
||||
@ -706,10 +716,146 @@
|
||||
#define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power control init */
|
||||
#define B43_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */
|
||||
#define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0
|
||||
#define B43_NPHY_ED_CRSEN B43_PHY_N(0x223)
|
||||
#define B43_NPHY_ED_CRS40ASSERTTHRESH0 B43_PHY_N(0x224)
|
||||
#define B43_NPHY_ED_CRS40ASSERTTHRESH1 B43_PHY_N(0x225)
|
||||
#define B43_NPHY_ED_CRS40DEASSERTTHRESH0 B43_PHY_N(0x226)
|
||||
#define B43_NPHY_ED_CRS40DEASSERTTHRESH1 B43_PHY_N(0x227)
|
||||
#define B43_NPHY_ED_CRS20LASSERTTHRESH0 B43_PHY_N(0x228)
|
||||
#define B43_NPHY_ED_CRS20LASSERTTHRESH1 B43_PHY_N(0x229)
|
||||
#define B43_NPHY_ED_CRS20LDEASSERTTHRESH0 B43_PHY_N(0x22A)
|
||||
#define B43_NPHY_ED_CRS20LDEASSERTTHRESH1 B43_PHY_N(0x22B)
|
||||
#define B43_NPHY_ED_CRS20UASSERTTHRESH0 B43_PHY_N(0x22C)
|
||||
#define B43_NPHY_ED_CRS20UASSERTTHRESH1 B43_PHY_N(0x22D)
|
||||
#define B43_NPHY_ED_CRS20UDEASSERTTHRESH0 B43_PHY_N(0x22E)
|
||||
#define B43_NPHY_ED_CRS20UDEASSERTTHRESH1 B43_PHY_N(0x22F)
|
||||
#define B43_NPHY_ED_CRS B43_PHY_N(0x230)
|
||||
#define B43_NPHY_TIMEOUTEN B43_PHY_N(0x231)
|
||||
#define B43_NPHY_OFDMPAYDECODETIMEOUTLEN B43_PHY_N(0x232)
|
||||
#define B43_NPHY_CCKPAYDECODETIMEOUTLEN B43_PHY_N(0x233)
|
||||
#define B43_NPHY_NONPAYDECODETIMEOUTLEN B43_PHY_N(0x234)
|
||||
#define B43_NPHY_TIMEOUTSTATUS B43_PHY_N(0x235)
|
||||
#define B43_NPHY_RFCTRLCORE0GPIO0 B43_PHY_N(0x236)
|
||||
#define B43_NPHY_RFCTRLCORE0GPIO1 B43_PHY_N(0x237)
|
||||
#define B43_NPHY_RFCTRLCORE0GPIO2 B43_PHY_N(0x238)
|
||||
#define B43_NPHY_RFCTRLCORE0GPIO3 B43_PHY_N(0x239)
|
||||
#define B43_NPHY_RFCTRLCORE1GPIO0 B43_PHY_N(0x23A)
|
||||
#define B43_NPHY_RFCTRLCORE1GPIO1 B43_PHY_N(0x23B)
|
||||
#define B43_NPHY_RFCTRLCORE1GPIO2 B43_PHY_N(0x23C)
|
||||
#define B43_NPHY_RFCTRLCORE1GPIO3 B43_PHY_N(0x23D)
|
||||
#define B43_NPHY_BPHYTESTCONTROL B43_PHY_N(0x23E)
|
||||
/* REV3+ */
|
||||
#define B43_NPHY_FORCEFRONT0 B43_PHY_N(0x23F)
|
||||
#define B43_NPHY_FORCEFRONT1 B43_PHY_N(0x240)
|
||||
#define B43_NPHY_NORMVARHYSTTH B43_PHY_N(0x241)
|
||||
#define B43_NPHY_TXCCKERROR B43_PHY_N(0x242)
|
||||
#define B43_NPHY_AFESEQINITDACGAIN B43_PHY_N(0x243)
|
||||
#define B43_NPHY_TXANTSWLUT B43_PHY_N(0x244)
|
||||
#define B43_NPHY_CORECONFIG B43_PHY_N(0x245)
|
||||
#define B43_NPHY_ANTENNADIVDWELLTIME B43_PHY_N(0x246)
|
||||
#define B43_NPHY_ANTENNACCKDIVDWELLTIME B43_PHY_N(0x247)
|
||||
#define B43_NPHY_ANTENNADIVBACKOFFGAIN B43_PHY_N(0x248)
|
||||
#define B43_NPHY_ANTENNADIVMINGAIN B43_PHY_N(0x249)
|
||||
#define B43_NPHY_BRDSEL_NORMVARHYSTTH B43_PHY_N(0x24A)
|
||||
#define B43_NPHY_RXANTSWITCHCTRL B43_PHY_N(0x24B)
|
||||
#define B43_NPHY_ENERGYDROPTIMEOUTLEN2 B43_PHY_N(0x24C)
|
||||
#define B43_NPHY_ML_LOG_TXEVM0 B43_PHY_N(0x250)
|
||||
#define B43_NPHY_ML_LOG_TXEVM1 B43_PHY_N(0x251)
|
||||
#define B43_NPHY_ML_LOG_TXEVM2 B43_PHY_N(0x252)
|
||||
#define B43_NPHY_ML_LOG_TXEVM3 B43_PHY_N(0x253)
|
||||
#define B43_NPHY_ML_LOG_TXEVM4 B43_PHY_N(0x254)
|
||||
#define B43_NPHY_ML_LOG_TXEVM5 B43_PHY_N(0x255)
|
||||
#define B43_NPHY_ML_LOG_TXEVM6 B43_PHY_N(0x256)
|
||||
#define B43_NPHY_ML_LOG_TXEVM7 B43_PHY_N(0x257)
|
||||
#define B43_NPHY_ML_SCALE_TWEAK B43_PHY_N(0x258)
|
||||
#define B43_NPHY_MLUA B43_PHY_N(0x259)
|
||||
#define B43_NPHY_ZFUA B43_PHY_N(0x25A)
|
||||
#define B43_NPHY_CHANUPSYM01 B43_PHY_N(0x25B)
|
||||
#define B43_NPHY_CHANUPSYM2 B43_PHY_N(0x25C)
|
||||
#define B43_NPHY_RXSTRNFILT20NUM00 B43_PHY_N(0x25D)
|
||||
#define B43_NPHY_RXSTRNFILT20NUM01 B43_PHY_N(0x25E)
|
||||
#define B43_NPHY_RXSTRNFILT20NUM02 B43_PHY_N(0x25F)
|
||||
#define B43_NPHY_RXSTRNFILT20DEN00 B43_PHY_N(0x260)
|
||||
#define B43_NPHY_RXSTRNFILT20DEN01 B43_PHY_N(0x261)
|
||||
#define B43_NPHY_RXSTRNFILT20NUM10 B43_PHY_N(0x262)
|
||||
#define B43_NPHY_RXSTRNFILT20NUM11 B43_PHY_N(0x263)
|
||||
#define B43_NPHY_RXSTRNFILT20NUM12 B43_PHY_N(0x264)
|
||||
#define B43_NPHY_RXSTRNFILT20DEN10 B43_PHY_N(0x265)
|
||||
#define B43_NPHY_RXSTRNFILT20DEN11 B43_PHY_N(0x266)
|
||||
#define B43_NPHY_RXSTRNFILT40NUM00 B43_PHY_N(0x267)
|
||||
#define B43_NPHY_RXSTRNFILT40NUM01 B43_PHY_N(0x268)
|
||||
#define B43_NPHY_RXSTRNFILT40NUM02 B43_PHY_N(0x269)
|
||||
#define B43_NPHY_RXSTRNFILT40DEN00 B43_PHY_N(0x26A)
|
||||
#define B43_NPHY_RXSTRNFILT40DEN01 B43_PHY_N(0x26B)
|
||||
#define B43_NPHY_RXSTRNFILT40NUM10 B43_PHY_N(0x26C)
|
||||
#define B43_NPHY_RXSTRNFILT40NUM11 B43_PHY_N(0x26D)
|
||||
#define B43_NPHY_RXSTRNFILT40NUM12 B43_PHY_N(0x26E)
|
||||
#define B43_NPHY_RXSTRNFILT40DEN10 B43_PHY_N(0x26F)
|
||||
#define B43_NPHY_RXSTRNFILT40DEN11 B43_PHY_N(0x270)
|
||||
#define B43_NPHY_CRSHIGHPOWTHRESHOLD1 B43_PHY_N(0x271)
|
||||
#define B43_NPHY_CRSHIGHPOWTHRESHOLD2 B43_PHY_N(0x272)
|
||||
#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLD B43_PHY_N(0x273)
|
||||
#define B43_NPHY_CRSHIGHPOWTHRESHOLD1L B43_PHY_N(0x274)
|
||||
#define B43_NPHY_CRSHIGHPOWTHRESHOLD2L B43_PHY_N(0x275)
|
||||
#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDL B43_PHY_N(0x276)
|
||||
#define B43_NPHY_CRSHIGHPOWTHRESHOLD1U B43_PHY_N(0x277)
|
||||
#define B43_NPHY_CRSHIGHPOWTHRESHOLD2U B43_PHY_N(0x278)
|
||||
#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDU B43_PHY_N(0x279)
|
||||
#define B43_NPHY_CRSACIDETECTTHRESH B43_PHY_N(0x27A)
|
||||
#define B43_NPHY_CRSACIDETECTTHRESHL B43_PHY_N(0x27B)
|
||||
#define B43_NPHY_CRSACIDETECTTHRESHU B43_PHY_N(0x27C)
|
||||
#define B43_NPHY_CRSMINPOWER0 B43_PHY_N(0x27D)
|
||||
#define B43_NPHY_CRSMINPOWER1 B43_PHY_N(0x27E)
|
||||
#define B43_NPHY_CRSMINPOWER2 B43_PHY_N(0x27F)
|
||||
#define B43_NPHY_CRSMINPOWERL0 B43_PHY_N(0x280)
|
||||
#define B43_NPHY_CRSMINPOWERL1 B43_PHY_N(0x281)
|
||||
#define B43_NPHY_CRSMINPOWERL2 B43_PHY_N(0x282)
|
||||
#define B43_NPHY_CRSMINPOWERU0 B43_PHY_N(0x283)
|
||||
#define B43_NPHY_CRSMINPOWERU1 B43_PHY_N(0x284)
|
||||
#define B43_NPHY_CRSMINPOWERU2 B43_PHY_N(0x285)
|
||||
#define B43_NPHY_STRPARAM B43_PHY_N(0x286)
|
||||
#define B43_NPHY_STRPARAML B43_PHY_N(0x287)
|
||||
#define B43_NPHY_STRPARAMU B43_PHY_N(0x288)
|
||||
#define B43_NPHY_BPHYCRSMINPOWER0 B43_PHY_N(0x289)
|
||||
#define B43_NPHY_BPHYCRSMINPOWER1 B43_PHY_N(0x28A)
|
||||
#define B43_NPHY_BPHYCRSMINPOWER2 B43_PHY_N(0x28B)
|
||||
#define B43_NPHY_BPHYFILTDEN0COEF B43_PHY_N(0x28C)
|
||||
#define B43_NPHY_BPHYFILTDEN1COEF B43_PHY_N(0x28D)
|
||||
#define B43_NPHY_BPHYFILTDEN2COEF B43_PHY_N(0x28E)
|
||||
#define B43_NPHY_BPHYFILTNUM0COEF B43_PHY_N(0x28F)
|
||||
#define B43_NPHY_BPHYFILTNUM1COEF B43_PHY_N(0x290)
|
||||
#define B43_NPHY_BPHYFILTNUM2COEF B43_PHY_N(0x291)
|
||||
#define B43_NPHY_BPHYFILTNUM01COEF2 B43_PHY_N(0x292)
|
||||
#define B43_NPHY_BPHYFILTBYPASS B43_PHY_N(0x293)
|
||||
#define B43_NPHY_SGILTRNOFFSET B43_PHY_N(0x294)
|
||||
#define B43_NPHY_RADAR_T2_MIN B43_PHY_N(0x295)
|
||||
#define B43_NPHY_TXPWRCTRLDAMPING B43_PHY_N(0x296)
|
||||
#define B43_NPHY_PAPD_EN0 B43_PHY_N(0x297) /* PAPD Enable0 TBD */
|
||||
#define B43_NPHY_EPS_TABLE_ADJ0 B43_PHY_N(0x298) /* EPS Table Adj0 TBD */
|
||||
#define B43_NPHY_EPS_OVERRIDEI_0 B43_PHY_N(0x299)
|
||||
#define B43_NPHY_EPS_OVERRIDEQ_0 B43_PHY_N(0x29A)
|
||||
#define B43_NPHY_PAPD_EN1 B43_PHY_N(0x29B) /* PAPD Enable1 TBD */
|
||||
#define B43_NPHY_EPS_TABLE_ADJ1 B43_PHY_N(0x29C) /* EPS Table Adj1 TBD */
|
||||
#define B43_NPHY_EPS_OVERRIDEI_1 B43_PHY_N(0x29D)
|
||||
#define B43_NPHY_EPS_OVERRIDEQ_1 B43_PHY_N(0x29E)
|
||||
#define B43_NPHY_PAPD_CAL_ADDRESS B43_PHY_N(0x29F)
|
||||
#define B43_NPHY_PAPD_CAL_YREFEPSILON B43_PHY_N(0x2A0)
|
||||
#define B43_NPHY_PAPD_CAL_SETTLE B43_PHY_N(0x2A1)
|
||||
#define B43_NPHY_PAPD_CAL_CORRELATE B43_PHY_N(0x2A2)
|
||||
#define B43_NPHY_PAPD_CAL_SHIFTS0 B43_PHY_N(0x2A3)
|
||||
#define B43_NPHY_PAPD_CAL_SHIFTS1 B43_PHY_N(0x2A4)
|
||||
#define B43_NPHY_SAMPLE_START_ADDR B43_PHY_N(0x2A5)
|
||||
#define B43_NPHY_RADAR_ADC_TO_DBM B43_PHY_N(0x2A6)
|
||||
#define B43_NPHY_REV3_C2_INITGAIN_A B43_PHY_N(0x2A7)
|
||||
#define B43_NPHY_REV3_C2_INITGAIN_B B43_PHY_N(0x2A8)
|
||||
#define B43_NPHY_REV3_C2_CLIP_HIGAIN_A B43_PHY_N(0x2A9)
|
||||
#define B43_NPHY_REV3_C2_CLIP_HIGAIN_B B43_PHY_N(0x2AA)
|
||||
#define B43_NPHY_REV3_C2_CLIP_MEDGAIN_A B43_PHY_N(0x2AB)
|
||||
#define B43_NPHY_REV3_C2_CLIP_MEDGAIN_B B43_PHY_N(0x2AC)
|
||||
#define B43_NPHY_REV3_C2_CLIP_LOGAIN_A B43_PHY_N(0x2AD)
|
||||
#define B43_NPHY_REV3_C2_CLIP_LOGAIN_B B43_PHY_N(0x2AE)
|
||||
#define B43_NPHY_REV3_C2_CLIP2_GAIN_A B43_PHY_N(0x2AF)
|
||||
#define B43_NPHY_REV3_C2_CLIP2_GAIN_B B43_PHY_N(0x2B0)
|
||||
|
||||
#define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) /* BB config */
|
||||
#define B43_PHY_B_TEST B43_PHY_N_BMODE(0x00A)
|
||||
|
||||
@ -27,7 +27,7 @@
|
||||
|
||||
#define RADIOREGS(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \
|
||||
r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \
|
||||
r20, r21, r22, r23, r24, r25, r26, r27, r28) \
|
||||
r20) \
|
||||
.radio_syn16 = r00, \
|
||||
.radio_syn17 = r01, \
|
||||
.radio_syn22 = r02, \
|
||||
@ -41,22 +41,14 @@
|
||||
.radio_syn41 = r10, \
|
||||
.radio_syn43 = r11, \
|
||||
.radio_syn47 = r12, \
|
||||
.radio_syn4a = r13, \
|
||||
.radio_syn58 = r14, \
|
||||
.radio_syn5a = r15, \
|
||||
.radio_syn6a = r16, \
|
||||
.radio_syn6d = r17, \
|
||||
.radio_syn6e = r18, \
|
||||
.radio_syn92 = r19, \
|
||||
.radio_syn98 = r20, \
|
||||
.radio_rxtx4a = r21, \
|
||||
.radio_rxtx58 = r22, \
|
||||
.radio_rxtx5a = r23, \
|
||||
.radio_rxtx6a = r24, \
|
||||
.radio_rxtx6d = r25, \
|
||||
.radio_rxtx6e = r26, \
|
||||
.radio_rxtx92 = r27, \
|
||||
.radio_rxtx98 = r28
|
||||
.radio_rxtx4a = r13, \
|
||||
.radio_rxtx58 = r14, \
|
||||
.radio_rxtx5a = r15, \
|
||||
.radio_rxtx6a = r16, \
|
||||
.radio_rxtx6d = r17, \
|
||||
.radio_rxtx6e = r18, \
|
||||
.radio_rxtx92 = r19, \
|
||||
.radio_rxtx98 = r20
|
||||
|
||||
#define PHYREGS(r0, r1, r2, r3, r4, r5) \
|
||||
.phy_regs.bw1 = r0, \
|
||||
@ -70,91 +62,78 @@ static const struct b43_phy_ht_channeltab_e_radio2059 b43_phy_ht_channeltab_radi
|
||||
{ .freq = 2412,
|
||||
RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c,
|
||||
0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
|
||||
},
|
||||
{ .freq = 2417,
|
||||
RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71,
|
||||
0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441),
|
||||
},
|
||||
{ .freq = 2422,
|
||||
RADIOREGS(0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76,
|
||||
0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f),
|
||||
},
|
||||
{ .freq = 2427,
|
||||
RADIOREGS(0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b,
|
||||
0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d),
|
||||
},
|
||||
{ .freq = 2432,
|
||||
RADIOREGS(0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80,
|
||||
0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a),
|
||||
},
|
||||
{ .freq = 2437,
|
||||
RADIOREGS(0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85,
|
||||
0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438),
|
||||
},
|
||||
{ .freq = 2442,
|
||||
RADIOREGS(0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a,
|
||||
0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436),
|
||||
},
|
||||
{ .freq = 2447,
|
||||
RADIOREGS(0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f,
|
||||
0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434),
|
||||
},
|
||||
{ .freq = 2452,
|
||||
RADIOREGS(0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94,
|
||||
0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431),
|
||||
},
|
||||
{ .freq = 2457,
|
||||
RADIOREGS(0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99,
|
||||
0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f),
|
||||
},
|
||||
{ .freq = 2462,
|
||||
RADIOREGS(0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e,
|
||||
0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d),
|
||||
},
|
||||
{ .freq = 2467,
|
||||
RADIOREGS(0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3,
|
||||
0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b),
|
||||
},
|
||||
{ .freq = 2472,
|
||||
RADIOREGS(0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8,
|
||||
0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429),
|
||||
},
|
||||
|
||||
@ -5,9 +5,9 @@
|
||||
|
||||
#include "phy_ht.h"
|
||||
|
||||
#define R2059_SYN 0x000
|
||||
#define R2059_TXRX0 0x400
|
||||
#define R2059_RXRX1 0x800
|
||||
#define R2059_C1 0x000
|
||||
#define R2059_C2 0x400
|
||||
#define R2059_C3 0x800
|
||||
#define R2059_ALL 0xC00
|
||||
|
||||
/* Values for various registers uploaded on channel switching */
|
||||
@ -28,14 +28,6 @@ struct b43_phy_ht_channeltab_e_radio2059 {
|
||||
u8 radio_syn41;
|
||||
u8 radio_syn43;
|
||||
u8 radio_syn47;
|
||||
u8 radio_syn4a;
|
||||
u8 radio_syn58;
|
||||
u8 radio_syn5a;
|
||||
u8 radio_syn6a;
|
||||
u8 radio_syn6d;
|
||||
u8 radio_syn6e;
|
||||
u8 radio_syn92;
|
||||
u8 radio_syn98;
|
||||
u8 radio_rxtx4a;
|
||||
u8 radio_rxtx58;
|
||||
u8 radio_rxtx5a;
|
||||
|
||||
@ -2174,7 +2174,7 @@ static const u16 b43_ntab_loftlt1_r3[] = {
|
||||
/* volatile tables, PHY revision >= 3 */
|
||||
|
||||
/* indexed by antswctl2g */
|
||||
static const u16 b43_ntab_antswctl2g_r3[4][32] = {
|
||||
static const u16 b43_ntab_antswctl_r3[4][32] = {
|
||||
{
|
||||
0x0082, 0x0082, 0x0211, 0x0222, 0x0328,
|
||||
0x0000, 0x0000, 0x0000, 0x0144, 0x0000,
|
||||
@ -3095,9 +3095,55 @@ void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset,
|
||||
}
|
||||
|
||||
#define ntab_upload(dev, offset, data) do { \
|
||||
b43_ntab_write_bulk(dev, offset, offset##_SIZE, data); \
|
||||
b43_ntab_write_bulk(dev, offset, ARRAY_SIZE(data), data); \
|
||||
} while (0)
|
||||
void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev)
|
||||
|
||||
static void b43_nphy_tables_init_rev3(struct b43_wldev *dev)
|
||||
{
|
||||
struct ssb_sprom *sprom = dev->dev->bus_sprom;
|
||||
u8 antswlut;
|
||||
|
||||
if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
|
||||
antswlut = sprom->fem.ghz5.antswlut;
|
||||
else
|
||||
antswlut = sprom->fem.ghz2.antswlut;
|
||||
|
||||
/* Static tables */
|
||||
ntab_upload(dev, B43_NTAB_FRAMESTRUCT_R3, b43_ntab_framestruct_r3);
|
||||
ntab_upload(dev, B43_NTAB_PILOT_R3, b43_ntab_pilot_r3);
|
||||
ntab_upload(dev, B43_NTAB_TMAP_R3, b43_ntab_tmap_r3);
|
||||
ntab_upload(dev, B43_NTAB_INTLEVEL_R3, b43_ntab_intlevel_r3);
|
||||
ntab_upload(dev, B43_NTAB_TDTRN_R3, b43_ntab_tdtrn_r3);
|
||||
ntab_upload(dev, B43_NTAB_NOISEVAR0_R3, b43_ntab_noisevar0_r3);
|
||||
ntab_upload(dev, B43_NTAB_NOISEVAR1_R3, b43_ntab_noisevar1_r3);
|
||||
ntab_upload(dev, B43_NTAB_MCS_R3, b43_ntab_mcs_r3);
|
||||
ntab_upload(dev, B43_NTAB_TDI20A0_R3, b43_ntab_tdi20a0_r3);
|
||||
ntab_upload(dev, B43_NTAB_TDI20A1_R3, b43_ntab_tdi20a1_r3);
|
||||
ntab_upload(dev, B43_NTAB_TDI40A0_R3, b43_ntab_tdi40a0_r3);
|
||||
ntab_upload(dev, B43_NTAB_TDI40A1_R3, b43_ntab_tdi40a1_r3);
|
||||
ntab_upload(dev, B43_NTAB_PILOTLT_R3, b43_ntab_pilotlt_r3);
|
||||
ntab_upload(dev, B43_NTAB_CHANEST_R3, b43_ntab_channelest_r3);
|
||||
ntab_upload(dev, B43_NTAB_FRAMELT_R3, b43_ntab_framelookup_r3);
|
||||
ntab_upload(dev, B43_NTAB_C0_ESTPLT_R3, b43_ntab_estimatepowerlt0_r3);
|
||||
ntab_upload(dev, B43_NTAB_C1_ESTPLT_R3, b43_ntab_estimatepowerlt1_r3);
|
||||
ntab_upload(dev, B43_NTAB_C0_ADJPLT_R3, b43_ntab_adjustpower0_r3);
|
||||
ntab_upload(dev, B43_NTAB_C1_ADJPLT_R3, b43_ntab_adjustpower1_r3);
|
||||
ntab_upload(dev, B43_NTAB_C0_GAINCTL_R3, b43_ntab_gainctl0_r3);
|
||||
ntab_upload(dev, B43_NTAB_C1_GAINCTL_R3, b43_ntab_gainctl1_r3);
|
||||
ntab_upload(dev, B43_NTAB_C0_IQLT_R3, b43_ntab_iqlt0_r3);
|
||||
ntab_upload(dev, B43_NTAB_C1_IQLT_R3, b43_ntab_iqlt1_r3);
|
||||
ntab_upload(dev, B43_NTAB_C0_LOFEEDTH_R3, b43_ntab_loftlt0_r3);
|
||||
ntab_upload(dev, B43_NTAB_C1_LOFEEDTH_R3, b43_ntab_loftlt1_r3);
|
||||
|
||||
/* Volatile tables */
|
||||
if (antswlut < ARRAY_SIZE(b43_ntab_antswctl_r3))
|
||||
ntab_upload(dev, B43_NTAB_ANT_SW_CTL_R3,
|
||||
b43_ntab_antswctl_r3[antswlut]);
|
||||
else
|
||||
B43_WARN_ON(1);
|
||||
}
|
||||
|
||||
static void b43_nphy_tables_init_rev0(struct b43_wldev *dev)
|
||||
{
|
||||
/* Static tables */
|
||||
ntab_upload(dev, B43_NTAB_FRAMESTRUCT, b43_ntab_framestruct);
|
||||
@ -3130,48 +3176,13 @@ void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev)
|
||||
ntab_upload(dev, B43_NTAB_C1_LOFEEDTH, b43_ntab_loftlt1);
|
||||
}
|
||||
|
||||
#define ntab_upload_r3(dev, offset, data) do { \
|
||||
b43_ntab_write_bulk(dev, offset, ARRAY_SIZE(data), data); \
|
||||
} while (0)
|
||||
void b43_nphy_rev3plus_tables_init(struct b43_wldev *dev)
|
||||
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables */
|
||||
void b43_nphy_tables_init(struct b43_wldev *dev)
|
||||
{
|
||||
struct ssb_sprom *sprom = dev->dev->bus_sprom;
|
||||
|
||||
/* Static tables */
|
||||
ntab_upload_r3(dev, B43_NTAB_FRAMESTRUCT_R3, b43_ntab_framestruct_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_PILOT_R3, b43_ntab_pilot_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_TMAP_R3, b43_ntab_tmap_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_INTLEVEL_R3, b43_ntab_intlevel_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_TDTRN_R3, b43_ntab_tdtrn_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_NOISEVAR0_R3, b43_ntab_noisevar0_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_NOISEVAR1_R3, b43_ntab_noisevar1_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_MCS_R3, b43_ntab_mcs_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_TDI20A0_R3, b43_ntab_tdi20a0_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_TDI20A1_R3, b43_ntab_tdi20a1_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_TDI40A0_R3, b43_ntab_tdi40a0_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_TDI40A1_R3, b43_ntab_tdi40a1_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_PILOTLT_R3, b43_ntab_pilotlt_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_CHANEST_R3, b43_ntab_channelest_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_FRAMELT_R3, b43_ntab_framelookup_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_C0_ESTPLT_R3,
|
||||
b43_ntab_estimatepowerlt0_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_C1_ESTPLT_R3,
|
||||
b43_ntab_estimatepowerlt1_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_C0_ADJPLT_R3, b43_ntab_adjustpower0_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_C1_ADJPLT_R3, b43_ntab_adjustpower1_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_C0_GAINCTL_R3, b43_ntab_gainctl0_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_C1_GAINCTL_R3, b43_ntab_gainctl1_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_C0_IQLT_R3, b43_ntab_iqlt0_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_C1_IQLT_R3, b43_ntab_iqlt1_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_C0_LOFEEDTH_R3, b43_ntab_loftlt0_r3);
|
||||
ntab_upload_r3(dev, B43_NTAB_C1_LOFEEDTH_R3, b43_ntab_loftlt1_r3);
|
||||
|
||||
/* Volatile tables */
|
||||
if (sprom->fem.ghz2.antswlut < ARRAY_SIZE(b43_ntab_antswctl2g_r3))
|
||||
ntab_upload_r3(dev, B43_NTAB_ANT_SW_CTL_R3,
|
||||
b43_ntab_antswctl2g_r3[sprom->fem.ghz2.antswlut]);
|
||||
if (dev->phy.rev >= 3)
|
||||
b43_nphy_tables_init_rev3(dev);
|
||||
else
|
||||
B43_WARN_ON(1);
|
||||
b43_nphy_tables_init_rev0(dev);
|
||||
}
|
||||
|
||||
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
|
||||
|
||||
@ -115,22 +115,22 @@ struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
|
||||
#define B43_NTAB_NOISEVAR11_SIZE 256
|
||||
#define B43_NTAB_C0_ESTPLT B43_NTAB8 (0x1A, 0x000) /* Estimate Power Lookup Table Core 0 */
|
||||
#define B43_NTAB_C0_ESTPLT_SIZE 64
|
||||
#define B43_NTAB_C1_ESTPLT B43_NTAB8 (0x1B, 0x000) /* Estimate Power Lookup Table Core 1 */
|
||||
#define B43_NTAB_C1_ESTPLT_SIZE 64
|
||||
#define B43_NTAB_C0_ADJPLT B43_NTAB8 (0x1A, 0x040) /* Adjust Power Lookup Table Core 0 */
|
||||
#define B43_NTAB_C0_ADJPLT_SIZE 128
|
||||
#define B43_NTAB_C1_ADJPLT B43_NTAB8 (0x1B, 0x040) /* Adjust Power Lookup Table Core 1 */
|
||||
#define B43_NTAB_C1_ADJPLT_SIZE 128
|
||||
#define B43_NTAB_C0_GAINCTL B43_NTAB32(0x1A, 0x0C0) /* Gain Control Lookup Table Core 0 */
|
||||
#define B43_NTAB_C0_GAINCTL_SIZE 128
|
||||
#define B43_NTAB_C1_GAINCTL B43_NTAB32(0x1B, 0x0C0) /* Gain Control Lookup Table Core 1 */
|
||||
#define B43_NTAB_C1_GAINCTL_SIZE 128
|
||||
#define B43_NTAB_C0_IQLT B43_NTAB32(0x1A, 0x140) /* IQ Lookup Table Core 0 */
|
||||
#define B43_NTAB_C0_IQLT_SIZE 128
|
||||
#define B43_NTAB_C1_IQLT B43_NTAB32(0x1B, 0x140) /* IQ Lookup Table Core 1 */
|
||||
#define B43_NTAB_C1_IQLT_SIZE 128
|
||||
#define B43_NTAB_C0_LOFEEDTH B43_NTAB16(0x1A, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 0 */
|
||||
#define B43_NTAB_C0_LOFEEDTH_SIZE 128
|
||||
#define B43_NTAB_C1_ESTPLT B43_NTAB8 (0x1B, 0x000) /* Estimate Power Lookup Table Core 1 */
|
||||
#define B43_NTAB_C1_ESTPLT_SIZE 64
|
||||
#define B43_NTAB_C1_ADJPLT B43_NTAB8 (0x1B, 0x040) /* Adjust Power Lookup Table Core 1 */
|
||||
#define B43_NTAB_C1_ADJPLT_SIZE 128
|
||||
#define B43_NTAB_C1_GAINCTL B43_NTAB32(0x1B, 0x0C0) /* Gain Control Lookup Table Core 1 */
|
||||
#define B43_NTAB_C1_GAINCTL_SIZE 128
|
||||
#define B43_NTAB_C1_IQLT B43_NTAB32(0x1B, 0x140) /* IQ Lookup Table Core 1 */
|
||||
#define B43_NTAB_C1_IQLT_SIZE 128
|
||||
#define B43_NTAB_C1_LOFEEDTH B43_NTAB16(0x1B, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 1 */
|
||||
#define B43_NTAB_C1_LOFEEDTH_SIZE 128
|
||||
|
||||
@ -154,15 +154,17 @@ struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
|
||||
#define B43_NTAB_CHANEST_R3 B43_NTAB32(22, 0) /* channel estimate */
|
||||
#define B43_NTAB_FRAMELT_R3 B43_NTAB8(24, 0) /* frame lookup */
|
||||
#define B43_NTAB_C0_ESTPLT_R3 B43_NTAB8(26, 0) /* estimated power lookup 0 */
|
||||
#define B43_NTAB_C1_ESTPLT_R3 B43_NTAB8(27, 0) /* estimated power lookup 1 */
|
||||
#define B43_NTAB_C0_ADJPLT_R3 B43_NTAB8(26, 64) /* adjusted power lookup 0 */
|
||||
#define B43_NTAB_C1_ADJPLT_R3 B43_NTAB8(27, 64) /* adjusted power lookup 1 */
|
||||
#define B43_NTAB_C0_GAINCTL_R3 B43_NTAB32(26, 192) /* gain control lookup 0 */
|
||||
#define B43_NTAB_C1_GAINCTL_R3 B43_NTAB32(27, 192) /* gain control lookup 1 */
|
||||
#define B43_NTAB_C0_IQLT_R3 B43_NTAB32(26, 320) /* I/Q lookup 0 */
|
||||
#define B43_NTAB_C1_IQLT_R3 B43_NTAB32(27, 320) /* I/Q lookup 1 */
|
||||
#define B43_NTAB_C0_LOFEEDTH_R3 B43_NTAB16(26, 448) /* Local Oscillator Feed Through lookup 0 */
|
||||
#define B43_NTAB_C0_PAPD_COMP_R3 B43_NTAB16(26, 576)
|
||||
#define B43_NTAB_C1_ESTPLT_R3 B43_NTAB8(27, 0) /* estimated power lookup 1 */
|
||||
#define B43_NTAB_C1_ADJPLT_R3 B43_NTAB8(27, 64) /* adjusted power lookup 1 */
|
||||
#define B43_NTAB_C1_GAINCTL_R3 B43_NTAB32(27, 192) /* gain control lookup 1 */
|
||||
#define B43_NTAB_C1_IQLT_R3 B43_NTAB32(27, 320) /* I/Q lookup 1 */
|
||||
#define B43_NTAB_C1_LOFEEDTH_R3 B43_NTAB16(27, 448) /* Local Oscillator Feed Through lookup 1 */
|
||||
#define B43_NTAB_C1_PAPD_COMP_R3 B43_NTAB16(27, 576)
|
||||
|
||||
#define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_40_SIZE 18
|
||||
#define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_20_SIZE 18
|
||||
@ -182,8 +184,7 @@ void b43_ntab_write(struct b43_wldev *dev, u32 offset, u32 value);
|
||||
void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset,
|
||||
unsigned int nr_elements, const void *_data);
|
||||
|
||||
void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev);
|
||||
void b43_nphy_rev3plus_tables_init(struct b43_wldev *dev);
|
||||
void b43_nphy_tables_init(struct b43_wldev *dev);
|
||||
|
||||
const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user