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ASoC: AMD: Configure channel 1 or channel 0 for capture
ST/CZ SoC have 2 channels for capture in the I2SSP path. The DMA though these channels is done using the same dma descriptors. We configure the channel and enable it on the basis of channel selected by machine driver. Machine driver knows which codec sits on which channel and thus sends the information to dma driver. Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Akshu Agrawal
Mark Brown
parent
44fedd7da4
commit
2718c89a23
@ -149,6 +149,7 @@ static int cz_da7219_startup(struct snd_pcm_substream *substream)
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&constraints_rates);
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machine->i2s_instance = I2S_SP_INSTANCE;
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machine->capture_channel = CAP_CHANNEL1;
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return da7219_clk_enable(substream);
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}
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@ -172,7 +173,7 @@ static void cz_max_shutdown(struct snd_pcm_substream *substream)
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da7219_clk_disable();
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}
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static int cz_dmic_startup(struct snd_pcm_substream *substream)
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static int cz_dmic0_startup(struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_card *card = rtd->card;
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@ -182,6 +183,17 @@ static int cz_dmic_startup(struct snd_pcm_substream *substream)
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return da7219_clk_enable(substream);
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}
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static int cz_dmic1_startup(struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_card *card = rtd->card;
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struct acp_platform_info *machine = snd_soc_card_get_drvdata(card);
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machine->i2s_instance = I2S_SP_INSTANCE;
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machine->capture_channel = CAP_CHANNEL0;
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return da7219_clk_enable(substream);
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}
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static void cz_dmic_shutdown(struct snd_pcm_substream *substream)
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{
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da7219_clk_disable();
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@ -197,8 +209,13 @@ static const struct snd_soc_ops cz_max_play_ops = {
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.shutdown = cz_max_shutdown,
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};
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static const struct snd_soc_ops cz_dmic_cap_ops = {
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.startup = cz_dmic_startup,
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static const struct snd_soc_ops cz_dmic0_cap_ops = {
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.startup = cz_dmic0_startup,
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.shutdown = cz_dmic_shutdown,
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};
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static const struct snd_soc_ops cz_dmic1_cap_ops = {
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.startup = cz_dmic1_startup,
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.shutdown = cz_dmic_shutdown,
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};
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@ -241,8 +258,9 @@ static struct snd_soc_dai_link cz_dai_7219_98357[] = {
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.ops = &cz_max_play_ops,
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},
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{
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.name = "dmic",
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.stream_name = "DMIC Capture",
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/* C panel DMIC */
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.name = "dmic0",
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.stream_name = "DMIC0 Capture",
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.platform_name = "acp_audio_dma.0.auto",
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.cpu_dai_name = "designware-i2s.3.auto",
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.codec_dai_name = "adau7002-hifi",
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@ -250,7 +268,20 @@ static struct snd_soc_dai_link cz_dai_7219_98357[] = {
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.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
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| SND_SOC_DAIFMT_CBM_CFM,
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.dpcm_capture = 1,
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.ops = &cz_dmic_cap_ops,
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.ops = &cz_dmic0_cap_ops,
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},
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{
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/* A/B panel DMIC */
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.name = "dmic1",
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.stream_name = "DMIC1 Capture",
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.platform_name = "acp_audio_dma.0.auto",
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.cpu_dai_name = "designware-i2s.2.auto",
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.codec_dai_name = "adau7002-hifi",
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.codec_name = "ADAU7002:00",
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.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
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| SND_SOC_DAIFMT_CBM_CFM,
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.dpcm_capture = 1,
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.ops = &cz_dmic1_cap_ops,
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},
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};
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@ -336,6 +336,61 @@ static void config_acp_dma(void __iomem *acp_mmio,
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rtd->dma_dscr_idx_2, asic_type);
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}
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static void acp_dma_cap_channel_enable(void __iomem *acp_mmio,
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u16 cap_channel)
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{
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u32 val, ch_reg, imr_reg, res_reg;
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switch (cap_channel) {
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case CAP_CHANNEL1:
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ch_reg = mmACP_I2SMICSP_RER1;
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res_reg = mmACP_I2SMICSP_RCR1;
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imr_reg = mmACP_I2SMICSP_IMR1;
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break;
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case CAP_CHANNEL0:
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default:
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ch_reg = mmACP_I2SMICSP_RER0;
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res_reg = mmACP_I2SMICSP_RCR0;
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imr_reg = mmACP_I2SMICSP_IMR0;
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break;
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}
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val = acp_reg_read(acp_mmio,
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mmACP_I2S_16BIT_RESOLUTION_EN);
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if (val & ACP_I2S_MIC_16BIT_RESOLUTION_EN) {
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acp_reg_write(0x0, acp_mmio, ch_reg);
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/* Set 16bit resolution on capture */
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acp_reg_write(0x2, acp_mmio, res_reg);
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}
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val = acp_reg_read(acp_mmio, imr_reg);
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val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK;
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val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK;
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acp_reg_write(val, acp_mmio, imr_reg);
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acp_reg_write(0x1, acp_mmio, ch_reg);
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}
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static void acp_dma_cap_channel_disable(void __iomem *acp_mmio,
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u16 cap_channel)
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{
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u32 val, ch_reg, imr_reg;
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switch (cap_channel) {
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case CAP_CHANNEL1:
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imr_reg = mmACP_I2SMICSP_IMR1;
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ch_reg = mmACP_I2SMICSP_RER1;
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break;
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case CAP_CHANNEL0:
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default:
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imr_reg = mmACP_I2SMICSP_IMR0;
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ch_reg = mmACP_I2SMICSP_RER0;
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break;
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}
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val = acp_reg_read(acp_mmio, imr_reg);
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val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK;
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val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK;
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acp_reg_write(val, acp_mmio, imr_reg);
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acp_reg_write(0x0, acp_mmio, ch_reg);
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}
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/* Start a given DMA channel transfer */
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static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num)
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{
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@ -773,8 +828,10 @@ static int acp_dma_hw_params(struct snd_pcm_substream *substream,
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if (WARN_ON(!rtd))
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return -EINVAL;
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if (pinfo)
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if (pinfo) {
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rtd->i2s_instance = pinfo->i2s_instance;
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rtd->capture_channel = pinfo->capture_channel;
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}
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if (adata->asic_type == CHIP_STONEY) {
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val = acp_reg_read(adata->acp_mmio,
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mmACP_I2S_16BIT_RESOLUTION_EN);
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@ -990,6 +1047,18 @@ static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
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acp_dma_start(rtd->acp_mmio, rtd->ch1);
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acp_dma_start(rtd->acp_mmio, rtd->ch2);
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} else {
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if (rtd->capture_channel == CAP_CHANNEL0) {
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acp_dma_cap_channel_disable(rtd->acp_mmio,
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CAP_CHANNEL1);
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acp_dma_cap_channel_enable(rtd->acp_mmio,
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CAP_CHANNEL0);
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}
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if (rtd->capture_channel == CAP_CHANNEL1) {
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acp_dma_cap_channel_disable(rtd->acp_mmio,
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CAP_CHANNEL0);
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acp_dma_cap_channel_enable(rtd->acp_mmio,
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CAP_CHANNEL1);
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}
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acp_dma_start(rtd->acp_mmio, rtd->ch2);
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acp_dma_start(rtd->acp_mmio, rtd->ch1);
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}
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@ -55,6 +55,8 @@
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#define I2S_SP_INSTANCE 0x01
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#define I2S_BT_INSTANCE 0x02
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#define CAP_CHANNEL0 0x00
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#define CAP_CHANNEL1 0x01
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#define ACP_TILE_ON_MASK 0x03
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#define ACP_TILE_OFF_MASK 0x02
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@ -125,6 +127,7 @@ struct audio_substream_data {
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unsigned int order;
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u16 num_of_pages;
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u16 i2s_instance;
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u16 capture_channel;
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u16 direction;
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u16 ch1;
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u16 ch2;
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@ -155,6 +158,7 @@ struct audio_drv_data {
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*/
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struct acp_platform_info {
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u16 i2s_instance;
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u16 capture_channel;
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};
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union acp_dma_count {
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