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ARCv2: Support dynamic peripheral address space in HS38 rel 3.0 cores

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HS release 3.0 provides for even more flexibility in specifying the
volatile address space for mapping peripherals.

With HS 2.1 @start was made flexible / programmable - with HS 3.0 even
@end can be setup (vs. fixed to 0xFFFF_FFFF before).

So add code to reflect that and while at it remove an unused struct
defintion

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta 2016-08-26 15:41:29 -07:00
parent f507684637
commit 26c01c49d5
5 changed files with 23 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arc/include/asm/arcregs.h
View File

@ -95,7 +95,7 @@
/* Auxiliary registers */
#define AUX_IDENTITY 4
#define AUX_INTR_VEC_BASE 0x25
#define AUX_NON_VOL 0x5e
#define AUX_VOL 0x5e
/*
* Floating Pt Registers
@ -240,14 +240,6 @@ struct bcr_extn_xymem {
#endif
};
struct bcr_perip {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int start:8, pad2:8, sz:8, ver:8;
#else
unsigned int ver:8, sz:8, pad2:8, start:8;
#endif
};
struct bcr_iccm_arcompact {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int base:16, pad:5, sz:3, ver:8;

2
arch/arc/include/asm/cache.h
View File

@ -54,7 +54,7 @@ extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
extern void read_decode_cache_bcr(void);
extern int ioc_exists;
extern unsigned long perip_base;
extern unsigned long perip_base, perip_end;
#endif /* !__ASSEMBLY__ */

4
arch/arc/kernel/setup.c
View File

@ -273,8 +273,8 @@ static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
FIX_PTR(cpu);
n += scnprintf(buf + n, len - n,
"Vector Table\t: %#x\nUncached Base\t: %#lx\n",
cpu->vec_base, perip_base);
"Vector Table\t: %#x\nPeripherals\t: %#lx:%#lx\n",
cpu->vec_base, perip_base, perip_end);
if (cpu->extn.fpu_sp || cpu->extn.fpu_dp)
n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",

23
arch/arc/mm/cache.c
View File

@ -25,6 +25,7 @@ static int l2_line_sz;
int ioc_exists;
volatile int slc_enable = 1, ioc_enable = 1;
unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */
unsigned long perip_end = 0xFFFFFFFF; /* legacy value */
void (*_cache_line_loop_ic_fn)(phys_addr_t paddr, unsigned long vaddr,
unsigned long sz, const int cacheop);
@ -76,7 +77,6 @@ char *arc_cache_mumbojumbo(int c, char *buf, int len)
static void read_decode_cache_bcr_arcv2(int cpu)
{
struct cpuinfo_arc_cache *p_slc = &cpuinfo_arc700[cpu].slc;
struct bcr_generic uncached_space;
struct bcr_generic sbcr;
struct bcr_slc_cfg {
@ -95,6 +95,15 @@ static void read_decode_cache_bcr_arcv2(int cpu)
#endif
} cbcr;
struct bcr_volatile {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int start:4, limit:4, pad:22, order:1, disable:1;
#else
unsigned int disable:1, order:1, pad:22, limit:4, start:4;
#endif
} vol;
READ_BCR(ARC_REG_SLC_BCR, sbcr);
if (sbcr.ver) {
READ_BCR(ARC_REG_SLC_CFG, slc_cfg);
@ -107,10 +116,14 @@ static void read_decode_cache_bcr_arcv2(int cpu)
if (cbcr.c && ioc_enable)
ioc_exists = 1;
/* Legacy Data Uncached BCR is deprecated from v3 onwards */
READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
if (uncached_space.ver > 2)
perip_base = read_aux_reg(AUX_NON_VOL) & 0xF0000000;
/* HS 2.0 didn't have AUX_VOL */
if (cpuinfo_arc700[cpu].core.family > 0x51) {
READ_BCR(AUX_VOL, vol);
perip_base = vol.start << 28;
/* HS 3.0 has limit and strict-ordering fields */
if (cpuinfo_arc700[cpu].core.family > 0x52)
perip_end = (vol.limit << 28) - 1;
}
}
void read_decode_cache_bcr(void)

2
arch/arc/mm/ioremap.c
View File

@ -19,7 +19,7 @@ static inline bool arc_uncached_addr_space(phys_addr_t paddr)
if (is_isa_arcompact()) {
if (paddr >= ARC_UNCACHED_ADDR_SPACE)
return true;
} else if (paddr >= perip_base && paddr <= 0xFFFFFFFF) {
} else if (paddr >= perip_base && paddr <= perip_end) {
return true;
}