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clk: renesas: r8a7796: Add watchdog core clocks

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Add all core clocks related to the Watchdog Timer (WDT) controller on
the Renesas R-Car M3-W (r8a7796) SoC: OSC, Internal RCLK, and RCLK.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Geert Uytterhoeven 2016-06-27 16:48:07 +02:00
parent 29b4817d40
commit 2570d4005d
1 changed files with 6 additions and 0 deletions
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6
drivers/clk/renesas/r8a7796-cpg-mssr.c
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@ -45,6 +45,7 @@ enum clk_ids {
CLK_S3,
CLK_SDSRC,
CLK_SSPSRC,
CLK_RINT,
/* Module Clocks */
MOD_CLK_BASE
@ -94,6 +95,11 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {