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[SCSI] hpsa: use multiple reply queues
Smart Arrays can support multiple reply queues onto which command completions may be deposited. It can help performance quite a bit to arrange for command completions to be processed on the same CPU from which they were submitted to increase the likelihood of cache hits. Signed-off-by: Matt Gates <matthew.gates@hp.com> Signed-off-by: Stephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
Matt Gates
James Bottomley
parent
1d94f94d89
commit
254f796b9f
@ -172,7 +172,7 @@ static void check_ioctl_unit_attention(struct ctlr_info *h,
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static void calc_bucket_map(int *bucket, int num_buckets,
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int nsgs, int *bucket_map);
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static __devinit void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
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static inline u32 next_command(struct ctlr_info *h);
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static inline u32 next_command(struct ctlr_info *h, u8 q);
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static int __devinit hpsa_find_cfg_addrs(struct pci_dev *pdev,
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void __iomem *vaddr, u32 *cfg_base_addr, u64 *cfg_base_addr_index,
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u64 *cfg_offset);
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@ -529,24 +529,25 @@ static inline void addQ(struct list_head *list, struct CommandList *c)
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list_add_tail(&c->list, list);
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}
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static inline u32 next_command(struct ctlr_info *h)
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static inline u32 next_command(struct ctlr_info *h, u8 q)
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{
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u32 a;
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struct reply_pool *rq = &h->reply_queue[q];
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if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
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return h->access.command_completed(h);
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return h->access.command_completed(h, q);
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if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
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a = *(h->reply_pool_head); /* Next cmd in ring buffer */
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(h->reply_pool_head)++;
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if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
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a = rq->head[rq->current_entry];
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rq->current_entry++;
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h->commands_outstanding--;
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} else {
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a = FIFO_EMPTY;
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}
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/* Check for wraparound */
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if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
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h->reply_pool_head = h->reply_pool;
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h->reply_pool_wraparound ^= 1;
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if (rq->current_entry == h->max_commands) {
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rq->current_entry = 0;
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rq->wraparound ^= 1;
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}
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return a;
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}
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@ -557,8 +558,12 @@ static inline u32 next_command(struct ctlr_info *h)
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*/
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static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
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{
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if (likely(h->transMethod & CFGTBL_Trans_Performant))
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if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
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c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
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if (likely(h->msix_vector))
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c->Header.ReplyQueue =
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smp_processor_id() % h->nreply_queues;
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}
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}
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static void enqueue_cmd_and_start_io(struct ctlr_info *h,
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@ -3323,9 +3328,9 @@ static void start_io(struct ctlr_info *h)
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}
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}
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static inline unsigned long get_next_completion(struct ctlr_info *h)
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static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
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{
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return h->access.command_completed(h);
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return h->access.command_completed(h, q);
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}
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static inline bool interrupt_pending(struct ctlr_info *h)
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@ -3428,9 +3433,20 @@ static int ignore_bogus_interrupt(struct ctlr_info *h)
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return 1;
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}
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static irqreturn_t hpsa_intx_discard_completions(int irq, void *dev_id)
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/*
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* Convert &h->q[x] (passed to interrupt handlers) back to h.
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* Relies on (h-q[x] == x) being true for x such that
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* 0 <= x < MAX_REPLY_QUEUES.
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*/
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static struct ctlr_info *queue_to_hba(u8 *queue)
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{
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struct ctlr_info *h = dev_id;
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return container_of((queue - *queue), struct ctlr_info, q[0]);
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}
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static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
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{
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struct ctlr_info *h = queue_to_hba(queue);
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u8 q = *(u8 *) queue;
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unsigned long flags;
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u32 raw_tag;
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@ -3442,71 +3458,75 @@ static irqreturn_t hpsa_intx_discard_completions(int irq, void *dev_id)
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spin_lock_irqsave(&h->lock, flags);
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h->last_intr_timestamp = get_jiffies_64();
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while (interrupt_pending(h)) {
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raw_tag = get_next_completion(h);
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raw_tag = get_next_completion(h, q);
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while (raw_tag != FIFO_EMPTY)
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raw_tag = next_command(h);
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raw_tag = next_command(h, q);
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}
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spin_unlock_irqrestore(&h->lock, flags);
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return IRQ_HANDLED;
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}
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static irqreturn_t hpsa_msix_discard_completions(int irq, void *dev_id)
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static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
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{
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struct ctlr_info *h = dev_id;
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struct ctlr_info *h = queue_to_hba(queue);
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unsigned long flags;
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u32 raw_tag;
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u8 q = *(u8 *) queue;
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if (ignore_bogus_interrupt(h))
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return IRQ_NONE;
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spin_lock_irqsave(&h->lock, flags);
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h->last_intr_timestamp = get_jiffies_64();
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raw_tag = get_next_completion(h);
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raw_tag = get_next_completion(h, q);
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while (raw_tag != FIFO_EMPTY)
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raw_tag = next_command(h);
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raw_tag = next_command(h, q);
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spin_unlock_irqrestore(&h->lock, flags);
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return IRQ_HANDLED;
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}
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static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id)
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static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
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{
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struct ctlr_info *h = dev_id;
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struct ctlr_info *h = queue_to_hba((u8 *) queue);
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unsigned long flags;
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u32 raw_tag;
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u8 q = *(u8 *) queue;
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if (interrupt_not_for_us(h))
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return IRQ_NONE;
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spin_lock_irqsave(&h->lock, flags);
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h->last_intr_timestamp = get_jiffies_64();
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while (interrupt_pending(h)) {
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raw_tag = get_next_completion(h);
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raw_tag = get_next_completion(h, q);
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while (raw_tag != FIFO_EMPTY) {
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if (likely(hpsa_tag_contains_index(raw_tag)))
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process_indexed_cmd(h, raw_tag);
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else
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process_nonindexed_cmd(h, raw_tag);
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raw_tag = next_command(h);
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raw_tag = next_command(h, q);
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}
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}
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spin_unlock_irqrestore(&h->lock, flags);
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return IRQ_HANDLED;
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}
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static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id)
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static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
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{
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struct ctlr_info *h = dev_id;
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struct ctlr_info *h = queue_to_hba(queue);
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unsigned long flags;
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u32 raw_tag;
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u8 q = *(u8 *) queue;
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spin_lock_irqsave(&h->lock, flags);
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h->last_intr_timestamp = get_jiffies_64();
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raw_tag = get_next_completion(h);
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raw_tag = get_next_completion(h, q);
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while (raw_tag != FIFO_EMPTY) {
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if (likely(hpsa_tag_contains_index(raw_tag)))
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process_indexed_cmd(h, raw_tag);
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else
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process_nonindexed_cmd(h, raw_tag);
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raw_tag = next_command(h);
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raw_tag = next_command(h, q);
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}
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spin_unlock_irqrestore(&h->lock, flags);
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return IRQ_HANDLED;
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@ -3942,10 +3962,13 @@ static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
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static void __devinit hpsa_interrupt_mode(struct ctlr_info *h)
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{
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#ifdef CONFIG_PCI_MSI
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int err;
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struct msix_entry hpsa_msix_entries[4] = { {0, 0}, {0, 1},
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{0, 2}, {0, 3}
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};
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int err, i;
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struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
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for (i = 0; i < MAX_REPLY_QUEUES; i++) {
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hpsa_msix_entries[i].vector = 0;
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hpsa_msix_entries[i].entry = i;
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}
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/* Some boards advertise MSI but don't really support it */
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if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
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@ -3953,12 +3976,11 @@ static void __devinit hpsa_interrupt_mode(struct ctlr_info *h)
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goto default_int_mode;
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if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
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dev_info(&h->pdev->dev, "MSIX\n");
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err = pci_enable_msix(h->pdev, hpsa_msix_entries, 4);
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err = pci_enable_msix(h->pdev, hpsa_msix_entries,
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MAX_REPLY_QUEUES);
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if (!err) {
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h->intr[0] = hpsa_msix_entries[0].vector;
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h->intr[1] = hpsa_msix_entries[1].vector;
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h->intr[2] = hpsa_msix_entries[2].vector;
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h->intr[3] = hpsa_msix_entries[3].vector;
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for (i = 0; i < MAX_REPLY_QUEUES; i++)
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h->intr[i] = hpsa_msix_entries[i].vector;
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h->msix_vector = 1;
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return;
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}
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@ -4372,14 +4394,33 @@ static int hpsa_request_irq(struct ctlr_info *h,
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irqreturn_t (*msixhandler)(int, void *),
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irqreturn_t (*intxhandler)(int, void *))
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{
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int rc;
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int rc, i;
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if (h->msix_vector || h->msi_vector)
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rc = request_irq(h->intr[h->intr_mode], msixhandler,
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0, h->devname, h);
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else
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rc = request_irq(h->intr[h->intr_mode], intxhandler,
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IRQF_SHARED, h->devname, h);
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/*
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* initialize h->q[x] = x so that interrupt handlers know which
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* queue to process.
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*/
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for (i = 0; i < MAX_REPLY_QUEUES; i++)
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h->q[i] = (u8) i;
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if (h->intr_mode == PERF_MODE_INT && h->msix_vector) {
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/* If performant mode and MSI-X, use multiple reply queues */
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for (i = 0; i < MAX_REPLY_QUEUES; i++)
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rc = request_irq(h->intr[i], msixhandler,
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0, h->devname,
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&h->q[i]);
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} else {
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/* Use single reply pool */
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if (h->msix_vector || h->msi_vector) {
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rc = request_irq(h->intr[h->intr_mode],
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msixhandler, 0, h->devname,
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&h->q[h->intr_mode]);
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} else {
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rc = request_irq(h->intr[h->intr_mode],
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intxhandler, IRQF_SHARED, h->devname,
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&h->q[h->intr_mode]);
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}
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}
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if (rc) {
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dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
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h->intr[h->intr_mode], h->devname);
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@ -4412,9 +4453,24 @@ static int __devinit hpsa_kdump_soft_reset(struct ctlr_info *h)
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return 0;
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}
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static void free_irqs(struct ctlr_info *h)
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{
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int i;
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if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
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/* Single reply queue, only one irq to free */
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i = h->intr_mode;
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free_irq(h->intr[i], &h->q[i]);
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return;
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}
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for (i = 0; i < MAX_REPLY_QUEUES; i++)
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free_irq(h->intr[i], &h->q[i]);
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}
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static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
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{
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free_irq(h->intr[h->intr_mode], h);
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free_irqs(h);
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#ifdef CONFIG_PCI_MSI
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if (h->msix_vector)
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pci_disable_msix(h->pdev);
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@ -4682,7 +4738,7 @@ reinit_after_soft_reset:
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spin_lock_irqsave(&h->lock, flags);
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h->access.set_intr_mask(h, HPSA_INTR_OFF);
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spin_unlock_irqrestore(&h->lock, flags);
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free_irq(h->intr[h->intr_mode], h);
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free_irqs(h);
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rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
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hpsa_intx_discard_completions);
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if (rc) {
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@ -4732,7 +4788,7 @@ reinit_after_soft_reset:
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clean4:
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hpsa_free_sg_chain_blocks(h);
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hpsa_free_cmd_pool(h);
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free_irq(h->intr[h->intr_mode], h);
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free_irqs(h);
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clean2:
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clean1:
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kfree(h);
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@ -4775,7 +4831,7 @@ static void hpsa_shutdown(struct pci_dev *pdev)
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*/
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hpsa_flush_cache(h);
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h->access.set_intr_mask(h, HPSA_INTR_OFF);
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free_irq(h->intr[h->intr_mode], h);
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free_irqs(h);
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#ifdef CONFIG_PCI_MSI
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if (h->msix_vector)
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pci_disable_msix(h->pdev);
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@ -4915,11 +4971,8 @@ static __devinit void hpsa_enter_performant_mode(struct ctlr_info *h,
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* 10 = 6 s/g entry or 24k
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*/
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h->reply_pool_wraparound = 1; /* spec: init to 1 */
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/* Controller spec: zero out this buffer. */
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memset(h->reply_pool, 0, h->reply_pool_size);
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h->reply_pool_head = h->reply_pool;
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bft[7] = SG_ENTRIES_IN_CMD + 4;
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calc_bucket_map(bft, ARRAY_SIZE(bft),
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@ -4929,12 +4982,19 @@ static __devinit void hpsa_enter_performant_mode(struct ctlr_info *h,
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/* size of controller ring buffer */
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writel(h->max_commands, &h->transtable->RepQSize);
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writel(1, &h->transtable->RepQCount);
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writel(h->nreply_queues, &h->transtable->RepQCount);
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writel(0, &h->transtable->RepQCtrAddrLow32);
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writel(0, &h->transtable->RepQCtrAddrHigh32);
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writel(h->reply_pool_dhandle, &h->transtable->RepQAddr0Low32);
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writel(0, &h->transtable->RepQAddr0High32);
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writel(CFGTBL_Trans_Performant | use_short_tags,
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for (i = 0; i < h->nreply_queues; i++) {
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writel(0, &h->transtable->RepQAddr[i].upper);
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writel(h->reply_pool_dhandle +
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(h->max_commands * sizeof(u64) * i),
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&h->transtable->RepQAddr[i].lower);
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}
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writel(CFGTBL_Trans_Performant | use_short_tags |
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CFGTBL_Trans_enable_directed_msix,
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&(h->cfgtable->HostWrite.TransportRequest));
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writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
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hpsa_wait_for_mode_change_ack(h);
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@ -4952,6 +5012,7 @@ static __devinit void hpsa_enter_performant_mode(struct ctlr_info *h,
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static __devinit void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
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{
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u32 trans_support;
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int i;
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if (hpsa_simple_mode)
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return;
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@ -4960,12 +5021,20 @@ static __devinit void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
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if (!(trans_support & PERFORMANT_MODE))
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return;
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h->nreply_queues = h->msix_vector ? MAX_REPLY_QUEUES : 1;
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hpsa_get_max_perf_mode_cmds(h);
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/* Performant mode ring buffer and supporting data structures */
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h->reply_pool_size = h->max_commands * sizeof(u64);
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h->reply_pool_size = h->max_commands * sizeof(u64) * h->nreply_queues;
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h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
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&(h->reply_pool_dhandle));
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for (i = 0; i < h->nreply_queues; i++) {
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h->reply_queue[i].head = &h->reply_pool[h->max_commands * i];
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h->reply_queue[i].size = h->max_commands;
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h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
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h->reply_queue[i].current_entry = 0;
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}
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/* Need a block fetch table for performant mode */
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h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
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sizeof(u32)), GFP_KERNEL);
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@ -34,7 +34,7 @@ struct access_method {
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void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
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unsigned long (*fifo_full)(struct ctlr_info *h);
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bool (*intr_pending)(struct ctlr_info *h);
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unsigned long (*command_completed)(struct ctlr_info *h);
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||||
unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
|
||||
};
|
||||
|
||||
struct hpsa_scsi_dev_t {
|
||||
@ -48,6 +48,13 @@ struct hpsa_scsi_dev_t {
|
||||
unsigned char raid_level; /* from inquiry page 0xC1 */
|
||||
};
|
||||
|
||||
struct reply_pool {
|
||||
u64 *head;
|
||||
size_t size;
|
||||
u8 wraparound;
|
||||
u32 current_entry;
|
||||
};
|
||||
|
||||
struct ctlr_info {
|
||||
int ctlr;
|
||||
char devname[8];
|
||||
@ -68,7 +75,7 @@ struct ctlr_info {
|
||||
# define DOORBELL_INT 1
|
||||
# define SIMPLE_MODE_INT 2
|
||||
# define MEMQ_MODE_INT 3
|
||||
unsigned int intr[4];
|
||||
unsigned int intr[MAX_REPLY_QUEUES];
|
||||
unsigned int msix_vector;
|
||||
unsigned int msi_vector;
|
||||
int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
|
||||
@ -111,13 +118,13 @@ struct ctlr_info {
|
||||
unsigned long transMethod;
|
||||
|
||||
/*
|
||||
* Performant mode completion buffer
|
||||
* Performant mode completion buffers
|
||||
*/
|
||||
u64 *reply_pool;
|
||||
dma_addr_t reply_pool_dhandle;
|
||||
u64 *reply_pool_head;
|
||||
size_t reply_pool_size;
|
||||
unsigned char reply_pool_wraparound;
|
||||
struct reply_pool reply_queue[MAX_REPLY_QUEUES];
|
||||
u8 nreply_queues;
|
||||
dma_addr_t reply_pool_dhandle;
|
||||
u32 *blockFetchTable;
|
||||
unsigned char *hba_inquiry_data;
|
||||
u64 last_intr_timestamp;
|
||||
@ -125,6 +132,8 @@ struct ctlr_info {
|
||||
u64 last_heartbeat_timestamp;
|
||||
u32 lockup_detected;
|
||||
struct list_head lockup_list;
|
||||
/* Address of h->q[x] is passed to intr handler to know which queue */
|
||||
u8 q[MAX_REPLY_QUEUES];
|
||||
u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
|
||||
#define HPSATMF_BITS_SUPPORTED (1 << 0)
|
||||
#define HPSATMF_PHYS_LUN_RESET (1 << 1)
|
||||
@ -275,8 +284,9 @@ static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned long SA5_performant_completed(struct ctlr_info *h)
|
||||
static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
|
||||
{
|
||||
struct reply_pool *rq = &h->reply_queue[q];
|
||||
unsigned long register_value = FIFO_EMPTY;
|
||||
|
||||
/* msi auto clears the interrupt pending bit. */
|
||||
@ -292,19 +302,18 @@ static unsigned long SA5_performant_completed(struct ctlr_info *h)
|
||||
register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
|
||||
}
|
||||
|
||||
if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
|
||||
register_value = *(h->reply_pool_head);
|
||||
(h->reply_pool_head)++;
|
||||
if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
|
||||
register_value = rq->head[rq->current_entry];
|
||||
rq->current_entry++;
|
||||
h->commands_outstanding--;
|
||||
} else {
|
||||
register_value = FIFO_EMPTY;
|
||||
}
|
||||
/* Check for wraparound */
|
||||
if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
|
||||
h->reply_pool_head = h->reply_pool;
|
||||
h->reply_pool_wraparound ^= 1;
|
||||
if (rq->current_entry == h->max_commands) {
|
||||
rq->current_entry = 0;
|
||||
rq->wraparound ^= 1;
|
||||
}
|
||||
|
||||
return register_value;
|
||||
}
|
||||
|
||||
@ -324,7 +333,8 @@ static unsigned long SA5_fifo_full(struct ctlr_info *h)
|
||||
* returns value read from hardware.
|
||||
* returns FIFO_EMPTY if there is nothing to read
|
||||
*/
|
||||
static unsigned long SA5_completed(struct ctlr_info *h)
|
||||
static unsigned long SA5_completed(struct ctlr_info *h,
|
||||
__attribute__((unused)) u8 q)
|
||||
{
|
||||
unsigned long register_value
|
||||
= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
|
||||
|
||||
@ -129,6 +129,7 @@
|
||||
#define CFGTBL_Trans_Simple 0x00000002l
|
||||
#define CFGTBL_Trans_Performant 0x00000004l
|
||||
#define CFGTBL_Trans_use_short_tags 0x20000000l
|
||||
#define CFGTBL_Trans_enable_directed_msix (1 << 30)
|
||||
|
||||
#define CFGTBL_BusType_Ultra2 0x00000001l
|
||||
#define CFGTBL_BusType_Ultra3 0x00000002l
|
||||
@ -380,8 +381,8 @@ struct TransTable_struct {
|
||||
u32 RepQCount;
|
||||
u32 RepQCtrAddrLow32;
|
||||
u32 RepQCtrAddrHigh32;
|
||||
u32 RepQAddr0Low32;
|
||||
u32 RepQAddr0High32;
|
||||
#define MAX_REPLY_QUEUES 8
|
||||
struct vals32 RepQAddr[MAX_REPLY_QUEUES];
|
||||
};
|
||||
|
||||
struct hpsa_pci_info {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user