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ASoC: mediatek: mt8188: revise AFE driver

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Merge series from Trevor Wu <trevor.wu@mediatek.com>:

The series of patches consists of four major changes.
First, remove redundant supply for ADDA DAI dirver. Second, revise ETDM
control including APLL dynamic switch via DAPM, so APLL can be enabled
when it is really required. Third, update AFE probe function. Bus
protection change was dropped at the previous patch because the dependent
change was not accepted at that time. Finally, correct some binding errors
and add required clocks.
This commit is contained in:
Mark Brown 2023-05-16 00:30:08 +09:00
commit 25428a9da7
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
7 changed files with 799 additions and 506 deletions
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66
Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml
View File

@ -29,6 +29,10 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle
description: The phandle of the mediatek topckgen controller
mediatek,infracfg:
$ref: /schemas/types.yaml#/definitions/phandle
description: The phandle of the mediatek infracfg controller
power-domains:
maxItems: 1
@ -52,6 +56,11 @@ properties:
- description: mux for i2si1_mck
- description: mux for i2si2_mck
- description: audio 26m clock
- description: audio pll1 divide 4
- description: audio pll2 divide 4
- description: clock divider for iec
- description: mux for a2sys clock
- description: mux for aud_iec
clock-names:
items:
@ -63,16 +72,21 @@ properties:
- const: apll12_div2
- const: apll12_div3
- const: apll12_div9
- const: a1sys_hp_sel
- const: aud_intbus_sel
- const: audio_h_sel
- const: audio_local_bus_sel
- const: dptx_m_sel
- const: i2so1_m_sel
- const: i2so2_m_sel
- const: i2si1_m_sel
- const: i2si2_m_sel
- const: top_a1sys_hp
- const: top_aud_intbus
- const: top_audio_h
- const: top_audio_local_bus
- const: top_dptx
- const: top_i2so1
- const: top_i2so2
- const: top_i2si1
- const: top_i2si2
- const: adsp_audio_26m
- const: apll1_d4
- const: apll2_d4
- const: apll12_div4
- const: top_a2sys
- const: top_aud_iec
mediatek,etdm-in1-cowork-source:
$ref: /schemas/types.yaml#/definitions/uint32
@ -144,6 +158,7 @@ required:
- resets
- reset-names
- mediatek,topckgen
- mediatek,infracfg
- power-domains
- clocks
- clock-names
@ -162,6 +177,7 @@ examples:
resets = <&watchdog 14>;
reset-names = "audiosys";
mediatek,topckgen = <&topckgen>;
mediatek,infracfg = <&infracfg_ao>;
power-domains = <&spm 13>; //MT8188_POWER_DOMAIN_AUDIO
mediatek,etdm-in2-cowork-source = <2>;
mediatek,etdm-out2-cowork-source = <0>;
@ -184,7 +200,12 @@ examples:
<&topckgen 78>, //CLK_TOP_I2SO2
<&topckgen 79>, //CLK_TOP_I2SI1
<&topckgen 80>, //CLK_TOP_I2SI2
<&adsp_audio26m 0>; //CLK_AUDIODSP_AUDIO26M
<&adsp_audio26m 0>, //CLK_AUDIODSP_AUDIO26M
<&topckgen 132>, //CLK_TOP_APLL1_D4
<&topckgen 133>, //CLK_TOP_APLL2_D4
<&topckgen 183>, //CLK_TOP_APLL12_CK_DIV4
<&topckgen 84>, //CLK_TOP_A2SYS
<&topckgen 82>; //CLK_TOP_AUD_IEC>;
clock-names = "clk26m",
"apll1",
"apll2",
@ -193,16 +214,21 @@ examples:
"apll12_div2",
"apll12_div3",
"apll12_div9",
"a1sys_hp_sel",
"aud_intbus_sel",
"audio_h_sel",
"audio_local_bus_sel",
"dptx_m_sel",
"i2so1_m_sel",
"i2so2_m_sel",
"i2si1_m_sel",
"i2si2_m_sel",
"adsp_audio_26m";
"top_a1sys_hp",
"top_aud_intbus",
"top_audio_h",
"top_audio_local_bus",
"top_dptx",
"top_i2so1",
"top_i2so2",
"top_i2si1",
"top_i2si2",
"adsp_audio_26m",
"apll1_d4",
"apll2_d4",
"apll12_div4",
"top_a2sys",
"top_aud_iec";
};
...

150
sound/soc/mediatek/mt8188/mt8188-afe-clk.c
View File

@ -24,14 +24,19 @@ static const char *aud_clks[MT8188_CLK_NUM] = {
[MT8188_CLK_APMIXED_APLL2] = "apll2",
/* divider */
[MT8188_CLK_TOP_APLL1_D4] = "apll1_d4",
[MT8188_CLK_TOP_APLL2_D4] = "apll2_d4",
[MT8188_CLK_TOP_APLL12_DIV0] = "apll12_div0",
[MT8188_CLK_TOP_APLL12_DIV1] = "apll12_div1",
[MT8188_CLK_TOP_APLL12_DIV2] = "apll12_div2",
[MT8188_CLK_TOP_APLL12_DIV3] = "apll12_div3",
[MT8188_CLK_TOP_APLL12_DIV4] = "apll12_div4",
[MT8188_CLK_TOP_APLL12_DIV9] = "apll12_div9",
/* mux */
[MT8188_CLK_TOP_A1SYS_HP_SEL] = "top_a1sys_hp",
[MT8188_CLK_TOP_A2SYS_SEL] = "top_a2sys",
[MT8188_CLK_TOP_AUD_IEC_SEL] = "top_aud_iec",
[MT8188_CLK_TOP_AUD_INTBUS_SEL] = "top_aud_intbus",
[MT8188_CLK_TOP_AUDIO_H_SEL] = "top_audio_h",
[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "top_audio_local_bus",
@ -378,6 +383,19 @@ int mt8188_afe_get_default_mclk_source_by_rate(int rate)
MT8188_MCK_SEL_APLL1 : MT8188_MCK_SEL_APLL2;
}
int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
{
return ((rate % 8000) == 0) ? MT8188_AUD_PLL1 : MT8188_AUD_PLL2;
}
int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
{
if (strcmp(name, APLL1_W_NAME) == 0)
return MT8188_AUD_PLL1;
return MT8188_AUD_PLL2;
}
int mt8188_afe_init_clock(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
@ -477,8 +495,8 @@ int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
if (clk && parent) {
ret = clk_set_parent(clk, parent);
if (ret) {
dev_dbg(afe->dev, "%s(), failed to set clk parent\n",
__func__);
dev_dbg(afe->dev, "%s(), failed to set clk parent %d\n",
__func__, ret);
return ret;
}
}
@ -605,54 +623,132 @@ static int mt8188_afe_disable_afe_on(struct mtk_base_afe *afe)
return 0;
}
static int mt8188_afe_enable_timing_sys(struct mtk_base_afe *afe)
static int mt8188_afe_enable_a1sys(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
if (ret)
return ret;
return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);
}
static int mt8188_afe_disable_a1sys(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
return 0;
}
mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);
mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);
mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);
static int mt8188_afe_enable_a2sys(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
if (ret)
return ret;
return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);
}
static int mt8188_afe_disable_a2sys(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
return 0;
}
int mt8188_apll1_enable(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
if (ret)
return ret;
ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
if (ret)
goto err_clk_parent;
ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL1);
if (ret)
goto err_apll_tuner;
ret = mt8188_afe_enable_a1sys(afe);
if (ret)
goto err_a1sys;
return 0;
err_a1sys:
mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1);
err_apll_tuner:
mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
afe_priv->clk[MT8188_CLK_XTAL_26M]);
err_clk_parent:
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
return ret;
}
int mt8188_apll1_disable(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
mt8188_afe_disable_a1sys(afe);
mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1);
mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
afe_priv->clk[MT8188_CLK_XTAL_26M]);
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
return 0;
}
static int mt8188_afe_disable_timing_sys(struct mtk_base_afe *afe)
int mt8188_apll2_enable(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
int ret;
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL2);
if (ret)
return ret;
mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);
mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);
mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);
ret = mt8188_afe_enable_a2sys(afe);
if (ret)
goto err_a2sys;
return 0;
err_a2sys:
mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2);
return ret;
}
int mt8188_apll2_disable(struct mtk_base_afe *afe)
{
mt8188_afe_disable_a2sys(afe);
mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2);
return 0;
}
int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe)
{
mt8188_afe_enable_timing_sys(afe);
mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);
mt8188_afe_enable_afe_on(afe);
mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL1);
mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL2);
return 0;
}
int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe)
{
mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2);
mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1);
mt8188_afe_disable_afe_on(afe);
mt8188_afe_disable_timing_sys(afe);
mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);
return 0;
}

15
sound/soc/mediatek/mt8188/mt8188-afe-clk.h
View File

@ -11,6 +11,10 @@
#ifndef _MT8188_AFE_CLK_H_
#define _MT8188_AFE_CLK_H_
/* APLL */
#define APLL1_W_NAME "APLL1"
#define APLL2_W_NAME "APLL2"
enum {
/* xtal */
MT8188_CLK_XTAL_26M,
@ -18,13 +22,18 @@ enum {
MT8188_CLK_APMIXED_APLL1,
MT8188_CLK_APMIXED_APLL2,
/* divider */
MT8188_CLK_TOP_APLL1_D4,
MT8188_CLK_TOP_APLL2_D4,
MT8188_CLK_TOP_APLL12_DIV0,
MT8188_CLK_TOP_APLL12_DIV1,
MT8188_CLK_TOP_APLL12_DIV2,
MT8188_CLK_TOP_APLL12_DIV3,
MT8188_CLK_TOP_APLL12_DIV4,
MT8188_CLK_TOP_APLL12_DIV9,
/* mux */
MT8188_CLK_TOP_A1SYS_HP_SEL,
MT8188_CLK_TOP_A2SYS_SEL,
MT8188_CLK_TOP_AUD_IEC_SEL,
MT8188_CLK_TOP_AUD_INTBUS_SEL,
MT8188_CLK_TOP_AUDIO_H_SEL,
MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
@ -99,6 +108,8 @@ struct mtk_base_afe;
int mt8188_afe_get_mclk_source_clk_id(int sel);
int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll);
int mt8188_afe_get_default_mclk_source_by_rate(int rate);
int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
int mt8188_afe_init_clock(struct mtk_base_afe *afe);
void mt8188_afe_deinit_clock(void *priv);
int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
@ -107,6 +118,10 @@ int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
unsigned int rate);
int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
struct clk *parent);
int mt8188_apll1_enable(struct mtk_base_afe *afe);
int mt8188_apll1_disable(struct mtk_base_afe *afe);
int mt8188_apll2_enable(struct mtk_base_afe *afe);
int mt8188_apll2_disable(struct mtk_base_afe *afe);
int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe);
int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe);
int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);

113
sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
View File

@ -17,6 +17,7 @@
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/soc/mediatek/infracfg.h>
#include <linux/reset.h>
#include <sound/pcm_params.h>
#include "mt8188-afe-common.h"
@ -1898,10 +1899,6 @@ static const struct snd_kcontrol_new mt8188_memif_controls[] = {
MT8188_AFE_MEMIF_UL10),
};
static const struct snd_soc_component_driver mt8188_afe_pcm_dai_component = {
.name = "mt8188-afe-pcm-dai",
};
static const struct mtk_base_memif_data memif_data[MT8188_AFE_MEMIF_NUM] = {
[MT8188_AFE_MEMIF_DL2] = {
.name = "DL2",
@ -3137,14 +3134,69 @@ static int mt8188_afe_parse_of(struct mtk_base_afe *afe,
return 0;
}
#define MT8188_DELAY_US 10
#define MT8188_TIMEOUT_US USEC_PER_SEC
static int bus_protect_enable(struct regmap *regmap)
{
int ret;
u32 val;
u32 mask;
val = 0;
mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1;
regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_SET, mask);
ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA,
val, (val & mask) == mask,
MT8188_DELAY_US, MT8188_TIMEOUT_US);
if (ret)
return ret;
val = 0;
mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2;
regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_SET, mask);
ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA,
val, (val & mask) == mask,
MT8188_DELAY_US, MT8188_TIMEOUT_US);
return ret;
}
static int bus_protect_disable(struct regmap *regmap)
{
int ret;
u32 val;
u32 mask;
val = 0;
mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2;
regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_CLR, mask);
ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA,
val, !(val & mask),
MT8188_DELAY_US, MT8188_TIMEOUT_US);
if (ret)
return ret;
val = 0;
mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1;
regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_CLR, mask);
ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA,
val, !(val & mask),
MT8188_DELAY_US, MT8188_TIMEOUT_US);
return ret;
}
static int mt8188_afe_pcm_dev_probe(struct platform_device *pdev)
{
struct mtk_base_afe *afe;
struct mt8188_afe_private *afe_priv;
struct device *dev;
int i, irq_id, ret;
struct snd_soc_component *component;
struct reset_control *rstc;
struct regmap *infra_ao;
int i, irq_id, ret;
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33));
if (ret)
@ -3168,18 +3220,37 @@ static int mt8188_afe_pcm_dev_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(afe->base_addr),
"AFE base_addr not found\n");
infra_ao = syscon_regmap_lookup_by_phandle(dev->of_node,
"mediatek,infracfg");
if (IS_ERR(infra_ao))
return dev_err_probe(dev, PTR_ERR(infra_ao),
"%s() Cannot find infra_ao controller\n",
__func__);
/* reset controller to reset audio regs before regmap cache */
rstc = devm_reset_control_get_exclusive(dev, "audiosys");
if (IS_ERR(rstc))
return dev_err_probe(dev, PTR_ERR(rstc),
"could not get audiosys reset\n");
ret = bus_protect_enable(infra_ao);
if (ret) {
dev_err(dev, "bus_protect_enable failed\n");
return ret;
}
ret = reset_control_reset(rstc);
if (ret) {
dev_err(dev, "failed to trigger audio reset:%d\n", ret);
return ret;
}
ret = bus_protect_disable(infra_ao);
if (ret) {
dev_err(dev, "bus_protect_disable failed\n");
return ret;
}
/* initial audio related clock */
ret = mt8188_afe_init_clock(afe);
if (ret)
@ -3280,34 +3351,12 @@ static int mt8188_afe_pcm_dev_probe(struct platform_device *pdev)
/* register component */
ret = devm_snd_soc_register_component(dev, &mt8188_afe_component,
NULL, 0);
afe->dai_drivers, afe->num_dai_drivers);
if (ret) {
dev_warn(dev, "err_platform\n");
goto err_pm_put;
}
component = devm_kzalloc(&pdev->dev, sizeof(*component), GFP_KERNEL);
if (!component) {
ret = -ENOMEM;
goto err_pm_put;
}
ret = snd_soc_component_initialize(component,
&mt8188_afe_pcm_dai_component,
&pdev->dev);
if (ret)
goto err_pm_put;
#ifdef CONFIG_DEBUG_FS
component->debugfs_prefix = "pcm";
#endif
ret = snd_soc_add_component(component,
afe->dai_drivers,
afe->num_dai_drivers);
if (ret) {
dev_warn(dev, "err_add_component\n");
goto err_pm_put;
}
mt8188_afe_init_registers(afe);
pm_runtime_put_sync(&pdev->dev);
@ -3323,11 +3372,6 @@ err_pm_put:
return ret;
}
static void mt8188_afe_pcm_dev_remove(struct platform_device *pdev)
{
snd_soc_unregister_component(&pdev->dev);
}
static const struct of_device_id mt8188_afe_pcm_dt_match[] = {
{ .compatible = "mediatek,mt8188-afe", },
{},
@ -3346,7 +3390,6 @@ static struct platform_driver mt8188_afe_pcm_driver = {
.pm = &mt8188_afe_pm_ops,
},
.probe = mt8188_afe_pcm_dev_probe,
.remove_new = mt8188_afe_pcm_dev_remove,
};
module_platform_driver(mt8188_afe_pcm_driver);

37
sound/soc/mediatek/mt8188/mt8188-dai-adda.c
View File

@ -18,7 +18,6 @@
#define ADDA_HIRES_THRES 48000
enum {
SUPPLY_SEQ_CLOCK_SEL,
SUPPLY_SEQ_ADDA_DL_ON,
SUPPLY_SEQ_ADDA_MTKAIF_CFG,
SUPPLY_SEQ_ADDA_UL_ON,
@ -242,34 +241,6 @@ static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
return 0;
}
static int mtk_audio_hires_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct clk *clk = afe_priv->clk[MT8188_CLK_TOP_AUDIO_H_SEL];
struct clk *clk_parent;
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
clk_parent = afe_priv->clk[MT8188_CLK_APMIXED_APLL1];
break;
case SND_SOC_DAPM_POST_PMD:
clk_parent = afe_priv->clk[MT8188_CLK_XTAL_26M];
break;
default:
return 0;
}
mt8188_afe_set_clk_parent(afe, clk, clk_parent);
return 0;
}
static int mtk_afe_adc_hires_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
@ -364,12 +335,6 @@ static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
mtk_adda_ul_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("AUDIO_HIRES", SUPPLY_SEQ_CLOCK_SEL,
SND_SOC_NOPM,
0, 0,
mtk_audio_hires_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,
SND_SOC_NOPM,
0, 0,
@ -397,7 +362,6 @@ static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
{"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},
{"ADDA Capture", NULL, "aud_adc"},
{"ADDA Capture", NULL, "aud_adc_hires", mtk_afe_adc_hires_connect},
{"aud_adc_hires", NULL, "AUDIO_HIRES"},
{"I168", NULL, "ADDA Capture"},
{"I169", NULL, "ADDA Capture"},
@ -406,7 +370,6 @@ static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
{"ADDA Playback", NULL, "ADDA Playback Enable"},
{"ADDA Playback", NULL, "aud_dac"},
{"ADDA Playback", NULL, "aud_dac_hires", mtk_afe_dac_hires_connect},
{"aud_dac_hires", NULL, "AUDIO_HIRES"},
{"DL_GAIN", NULL, "O176"},
{"DL_GAIN", NULL, "O177"},

922
sound/soc/mediatek/mt8188/mt8188-dai-etdm.c
View File

File diff suppressed because it is too large Load Diff

2
sound/soc/mediatek/mt8188/mt8188-reg.h
View File

@ -3007,6 +3007,7 @@
#define ETDM_CON0_SLAVE_MODE BIT(5)
#define ETDM_CON0_SYNC_MODE BIT(1)
#define ETDM_CON0_EN BIT(0)
#define ETDM_CON0_EN_SHIFT 0
#define ETDM_OUT_CON0_RELATCH_DOMAIN_MASK GENMASK(29, 28)
@ -3108,6 +3109,7 @@
#define AFE_DPTX_CON_CH_NUM_8CH (0x1 << 1)
#define AFE_DPTX_CON_CH_NUM_MASK BIT(1)
#define AFE_DPTX_CON_ON BIT(0)
#define AFE_DPTX_CON_ON_SHIFT 0
/* AFE_ADDA_DL_SRC2_CON0 */
#define DL_2_INPUT_MODE_CTL_MASK GENMASK(31, 28)