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[MIPS] Remove unused R10000 performance counter definitions.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -545,62 +545,6 @@
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#define MIPS_FPIR_L (_ULCAST_(1) << 21)
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#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
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/*
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* R10000 performance counter definitions.
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*
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* FIXME: The R10000 performance counter opens a nice way to implement CPU
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* time accounting with a precission of one cycle. I don't have
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* R10000 silicon but just a manual, so ...
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*/
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/*
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* Events counted by counter #0
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*/
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#define CE0_CYCLES 0
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#define CE0_INSN_ISSUED 1
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#define CE0_LPSC_ISSUED 2
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#define CE0_S_ISSUED 3
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#define CE0_SC_ISSUED 4
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#define CE0_SC_FAILED 5
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#define CE0_BRANCH_DECODED 6
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#define CE0_QW_WB_SECONDARY 7
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#define CE0_CORRECTED_ECC_ERRORS 8
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#define CE0_ICACHE_MISSES 9
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#define CE0_SCACHE_I_MISSES 10
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#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
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#define CE0_EXT_INTERVENTIONS_REQ 12
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#define CE0_EXT_INVALIDATE_REQ 13
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#define CE0_VIRTUAL_COHERENCY_COND 14
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#define CE0_INSN_GRADUATED 15
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/*
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* Events counted by counter #1
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*/
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#define CE1_CYCLES 0
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#define CE1_INSN_GRADUATED 1
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#define CE1_LPSC_GRADUATED 2
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#define CE1_S_GRADUATED 3
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#define CE1_SC_GRADUATED 4
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#define CE1_FP_INSN_GRADUATED 5
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#define CE1_QW_WB_PRIMARY 6
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#define CE1_TLB_REFILL 7
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#define CE1_BRANCH_MISSPREDICTED 8
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#define CE1_DCACHE_MISS 9
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#define CE1_SCACHE_D_MISSES 10
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#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
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#define CE1_EXT_INTERVENTION_HITS 12
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#define CE1_EXT_INVALIDATE_REQ 13
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#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
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#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
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/*
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* These flags define in which privilege mode the counters count events
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*/
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#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
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#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
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#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
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#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
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#ifndef __ASSEMBLY__
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/*
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