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clocksource/drivers/sun4i: Switch to the timer-of common init
Previously a framework to factor out the drivers init function has been merged. Use this common framework in this driver, we get: Before: text data bss dec hex filename 1787 384 12 2183 887 drivers/clocksource/sun4i_timer.o After: text data bss dec hex filename 1407 512 0 1919 77f drivers/clocksource/sun4i_timer.o Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Tested-by: Chen-Yu Tsai <wens@csie.org>
This commit is contained in:
Daniel Lezcano
parent
22ece4e3df
commit
239751edad
@ -108,6 +108,7 @@ config SUN4I_TIMER
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depends on GENERIC_CLOCKEVENTS
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depends on HAS_IOMEM
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select CLKSRC_MMIO
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select TIMER_OF
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help
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Enables support for the Sun4i timer.
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@ -24,6 +24,8 @@
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include "timer-of.h"
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#define TIMER_IRQ_EN_REG 0x00
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#define TIMER_IRQ_EN(val) BIT(val)
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#define TIMER_IRQ_ST_REG 0x04
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@ -39,38 +41,37 @@
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#define TIMER_SYNC_TICKS 3
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static void __iomem *timer_base;
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static u32 ticks_per_jiffy;
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/*
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* When we disable a timer, we need to wait at least for 2 cycles of
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* the timer source clock. We will use for that the clocksource timer
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* that is already setup and runs at the same frequency than the other
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* timers, and we never will be disabled.
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*/
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static void sun4i_clkevt_sync(void)
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static void sun4i_clkevt_sync(void __iomem *base)
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{
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u32 old = readl(timer_base + TIMER_CNTVAL_REG(1));
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u32 old = readl(base + TIMER_CNTVAL_REG(1));
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while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS)
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while ((old - readl(base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS)
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cpu_relax();
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}
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static void sun4i_clkevt_time_stop(u8 timer)
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static void sun4i_clkevt_time_stop(void __iomem *base, u8 timer)
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{
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u32 val = readl(timer_base + TIMER_CTL_REG(timer));
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writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
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sun4i_clkevt_sync();
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u32 val = readl(base + TIMER_CTL_REG(timer));
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writel(val & ~TIMER_CTL_ENABLE, base + TIMER_CTL_REG(timer));
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sun4i_clkevt_sync(base);
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}
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static void sun4i_clkevt_time_setup(u8 timer, unsigned long delay)
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static void sun4i_clkevt_time_setup(void __iomem *base, u8 timer,
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unsigned long delay)
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{
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writel(delay, timer_base + TIMER_INTVAL_REG(timer));
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writel(delay, base + TIMER_INTVAL_REG(timer));
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}
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static void sun4i_clkevt_time_start(u8 timer, bool periodic)
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static void sun4i_clkevt_time_start(void __iomem *base, u8 timer,
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bool periodic)
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{
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u32 val = readl(timer_base + TIMER_CTL_REG(timer));
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u32 val = readl(base + TIMER_CTL_REG(timer));
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if (periodic)
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val &= ~TIMER_CTL_ONESHOT;
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@ -78,115 +79,106 @@ static void sun4i_clkevt_time_start(u8 timer, bool periodic)
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val |= TIMER_CTL_ONESHOT;
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writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
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timer_base + TIMER_CTL_REG(timer));
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base + TIMER_CTL_REG(timer));
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}
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static int sun4i_clkevt_shutdown(struct clock_event_device *evt)
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{
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sun4i_clkevt_time_stop(0);
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struct timer_of *to = to_timer_of(evt);
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sun4i_clkevt_time_stop(timer_of_base(to), 0);
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return 0;
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}
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static int sun4i_clkevt_set_oneshot(struct clock_event_device *evt)
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{
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sun4i_clkevt_time_stop(0);
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sun4i_clkevt_time_start(0, false);
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struct timer_of *to = to_timer_of(evt);
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sun4i_clkevt_time_stop(timer_of_base(to), 0);
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sun4i_clkevt_time_start(timer_of_base(to), 0, false);
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return 0;
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}
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static int sun4i_clkevt_set_periodic(struct clock_event_device *evt)
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{
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sun4i_clkevt_time_stop(0);
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sun4i_clkevt_time_setup(0, ticks_per_jiffy);
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sun4i_clkevt_time_start(0, true);
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struct timer_of *to = to_timer_of(evt);
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sun4i_clkevt_time_stop(timer_of_base(to), 0);
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sun4i_clkevt_time_setup(timer_of_base(to), 0, timer_of_period(to));
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sun4i_clkevt_time_start(timer_of_base(to), 0, true);
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return 0;
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}
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static int sun4i_clkevt_next_event(unsigned long evt,
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struct clock_event_device *unused)
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struct clock_event_device *clkevt)
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{
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sun4i_clkevt_time_stop(0);
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sun4i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
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sun4i_clkevt_time_start(0, false);
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struct timer_of *to = to_timer_of(clkevt);
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sun4i_clkevt_time_stop(timer_of_base(to), 0);
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sun4i_clkevt_time_setup(timer_of_base(to), 0, evt - TIMER_SYNC_TICKS);
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sun4i_clkevt_time_start(timer_of_base(to), 0, false);
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return 0;
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}
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static struct clock_event_device sun4i_clockevent = {
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.name = "sun4i_tick",
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.rating = 350,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_state_shutdown = sun4i_clkevt_shutdown,
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.set_state_periodic = sun4i_clkevt_set_periodic,
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.set_state_oneshot = sun4i_clkevt_set_oneshot,
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.tick_resume = sun4i_clkevt_shutdown,
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.set_next_event = sun4i_clkevt_next_event,
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};
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static void sun4i_timer_clear_interrupt(void)
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static void sun4i_timer_clear_interrupt(void __iomem *base)
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{
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writel(TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_ST_REG);
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writel(TIMER_IRQ_EN(0), base + TIMER_IRQ_ST_REG);
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}
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static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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struct timer_of *to = to_timer_of(evt);
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sun4i_timer_clear_interrupt();
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sun4i_timer_clear_interrupt(timer_of_base(to));
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction sun4i_timer_irq = {
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.name = "sun4i_timer0",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = sun4i_timer_interrupt,
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.dev_id = &sun4i_clockevent,
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static struct timer_of to = {
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.flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE,
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.clkevt = {
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.name = "sun4i_tick",
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.rating = 350,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_state_shutdown = sun4i_clkevt_shutdown,
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.set_state_periodic = sun4i_clkevt_set_periodic,
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.set_state_oneshot = sun4i_clkevt_set_oneshot,
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.tick_resume = sun4i_clkevt_shutdown,
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.set_next_event = sun4i_clkevt_next_event,
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.cpumask = cpu_possible_mask,
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},
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.of_irq = {
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.handler = sun4i_timer_interrupt,
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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},
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};
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static u64 notrace sun4i_timer_sched_read(void)
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{
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return ~readl(timer_base + TIMER_CNTVAL_REG(1));
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return ~readl(timer_of_base(&to) + TIMER_CNTVAL_REG(1));
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}
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static int __init sun4i_timer_init(struct device_node *node)
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{
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unsigned long rate = 0;
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struct clk *clk;
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int ret, irq;
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int ret;
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u32 val;
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timer_base = of_iomap(node, 0);
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if (!timer_base) {
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pr_crit("Can't map registers\n");
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return -ENXIO;
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}
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irq = irq_of_parse_and_map(node, 0);
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if (irq <= 0) {
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pr_crit("Can't parse IRQ\n");
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return -EINVAL;
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}
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_crit("Can't get timer clock\n");
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return PTR_ERR(clk);
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("Failed to prepare clock\n");
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ret = timer_of_init(node, &to);
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if (ret)
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return ret;
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}
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rate = clk_get_rate(clk);
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writel(~0, timer_base + TIMER_INTVAL_REG(1));
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writel(~0, timer_of_base(&to) + TIMER_INTVAL_REG(1));
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writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
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TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
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timer_base + TIMER_CTL_REG(1));
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timer_of_base(&to) + TIMER_CTL_REG(1));
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/*
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* sched_clock_register does not have priorities, and on sun6i and
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@ -195,41 +187,32 @@ static int __init sun4i_timer_init(struct device_node *node)
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if (of_machine_is_compatible("allwinner,sun4i-a10") ||
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of_machine_is_compatible("allwinner,sun5i-a13") ||
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of_machine_is_compatible("allwinner,sun5i-a10s"))
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sched_clock_register(sun4i_timer_sched_read, 32, rate);
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sched_clock_register(sun4i_timer_sched_read, 32,
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timer_of_rate(&to));
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ret = clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
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rate, 350, 32, clocksource_mmio_readl_down);
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ret = clocksource_mmio_init(timer_of_base(&to) + TIMER_CNTVAL_REG(1),
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node->name, timer_of_rate(&to), 350, 32,
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clocksource_mmio_readl_down);
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if (ret) {
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pr_err("Failed to register clocksource\n");
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return ret;
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}
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ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
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writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
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timer_base + TIMER_CTL_REG(0));
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timer_of_base(&to) + TIMER_CTL_REG(0));
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/* Make sure timer is stopped before playing with interrupts */
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sun4i_clkevt_time_stop(0);
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sun4i_clkevt_time_stop(timer_of_base(&to), 0);
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/* clear timer0 interrupt */
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sun4i_timer_clear_interrupt();
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sun4i_timer_clear_interrupt(timer_of_base(&to));
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sun4i_clockevent.cpumask = cpu_possible_mask;
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sun4i_clockevent.irq = irq;
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clockevents_config_and_register(&sun4i_clockevent, rate,
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clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
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TIMER_SYNC_TICKS, 0xffffffff);
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ret = setup_irq(irq, &sun4i_timer_irq);
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if (ret) {
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pr_err("failed to setup irq %d\n", irq);
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return ret;
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}
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/* Enable timer0 interrupt */
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val = readl(timer_base + TIMER_IRQ_EN_REG);
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writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
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val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG);
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writel(val | TIMER_IRQ_EN(0), timer_of_base(&to) + TIMER_IRQ_EN_REG);
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return ret;
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}
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