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phy: zynqmp: Only wait for PLL lock "primary" instances
For PCIe and DisplayPort, the phy instance represents the controller's logical lane. Wait for the instance 0 phy's PLL to lock as other instances will never lock. We do this in xpsgtr_wait_pll_lock so callers don't have to determine the correct lane themselves. The original comment is wrong about cumulative wait times. Since we are just polling a bit, all subsequent waiters will finish immediately. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-4-sean.anderson@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -294,10 +294,30 @@ static int xpsgtr_wait_pll_lock(struct phy *phy)
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struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
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struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
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unsigned int timeout = TIMEOUT_US;
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u8 protocol = gtr_phy->protocol;
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int ret;
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dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n");
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/*
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* For DP and PCIe, only the instance 0 PLL is used. Switch to that phy
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* so we wait on the right PLL.
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*/
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if ((protocol == ICM_PROTOCOL_DP || protocol == ICM_PROTOCOL_PCIE) &&
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gtr_phy->instance) {
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int i;
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for (i = 0; i < NUM_LANES; i++) {
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gtr_phy = >r_dev->phys[i];
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if (gtr_phy->protocol == protocol && !gtr_phy->instance)
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goto got_phy;
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}
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return -EBUSY;
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}
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got_phy:
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while (1) {
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u32 reg = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1);
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@ -625,15 +645,7 @@ static int xpsgtr_phy_power_on(struct phy *phy)
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/* Skip initialization if not required. */
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if (!xpsgtr_phy_init_required(gtr_phy))
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return ret;
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/*
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* Wait for the PLL to lock. For DP, only wait on DP0 to avoid
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* cumulating waits for both lanes. The user is expected to initialize
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* lane 0 last.
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*/
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if (gtr_phy->protocol != ICM_PROTOCOL_DP || !gtr_phy->instance)
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ret = xpsgtr_wait_pll_lock(phy);
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return ret;
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return xpsgtr_wait_pll_lock(phy);
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}
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static int xpsgtr_phy_configure(struct phy *phy, union phy_configure_opts *opts)
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