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drm/amd/display: DCN35 set min dispclk to 50Mhz
[Why] Causes hard hangs when resuming after display off on extended/duplicate modes [How] Set the min dispclk to 50Mhz for DCN35 Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Nicholas Susanto <Nicholas.Susanto@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -305,6 +305,9 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
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if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz)
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new_clocks->ref_dtbclk_khz = 600000;
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if (dc->debug.min_disp_clk_khz > 0 && new_clocks->dispclk_khz < dc->debug.min_disp_clk_khz)
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new_clocks->dispclk_khz = dc->debug.min_disp_clk_khz;
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/*
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* if it is safe to lower, but we are already in the lower state, we don't have to do anything
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* also if safe to lower is false, we just go in the higher state
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@ -786,6 +786,7 @@ static const struct dc_debug_options debug_defaults_drv = {
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.disable_dmub_reallow_idle = false,
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.static_screen_wait_frames = 2,
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.disable_timeout = true,
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.min_disp_clk_khz = 50000,
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};
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static const struct dc_panel_config panel_config_defaults = {
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