drm/amd/display: DCN35 set min dispclk to 50Mhz

[Why]

Causes hard hangs when resuming after display off on extended/duplicate
modes

[How]

Set the min dispclk to 50Mhz for DCN35

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Nicholas Susanto <Nicholas.Susanto@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Susanto 2024-08-15 18:45:21 -04:00 committed by Alex Deucher
parent ec9e2e7acc
commit 2344413205
2 changed files with 4 additions and 0 deletions

View File

@ -305,6 +305,9 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz)
new_clocks->ref_dtbclk_khz = 600000;
if (dc->debug.min_disp_clk_khz > 0 && new_clocks->dispclk_khz < dc->debug.min_disp_clk_khz)
new_clocks->dispclk_khz = dc->debug.min_disp_clk_khz;
/*
* if it is safe to lower, but we are already in the lower state, we don't have to do anything
* also if safe to lower is false, we just go in the higher state

View File

@ -786,6 +786,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_dmub_reallow_idle = false,
.static_screen_wait_frames = 2,
.disable_timeout = true,
.min_disp_clk_khz = 50000,
};
static const struct dc_panel_config panel_config_defaults = {