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ath5k: Misc hw_reset updates
* Update hw_reset to calculate some of the values we were using as static * Increase activation to rx delay Changes-licensed-under: ISC Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -847,7 +847,22 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
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else
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ath5k_hw_reg_write(ah, 0x00000000, 0x994c);
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ath5k_hw_reg_write(ah, 0x000009b5, 0xa228);
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/* Some bits are disabled here, we know nothing about
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* register 0xa228 yet, most of the times this ends up
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* with a value 0x9b5 -haven't seen any dump with
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* a different value- */
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/* Got this from decompiling binary HAL */
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data = ath5k_hw_reg_read(ah, 0xa228);
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data &= 0xfffffdff;
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ath5k_hw_reg_write(ah, data, 0xa228);
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data = ath5k_hw_reg_read(ah, 0xa228);
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data &= 0xfffe03ff;
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ath5k_hw_reg_write(ah, data, 0xa228);
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data = 0;
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/* Just write 0x9b5 ? */
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/* ath5k_hw_reg_write(ah, 0x000009b5, 0xa228); */
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ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
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ath5k_hw_reg_write(ah, 0x00000000, 0xa254);
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ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL);
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@ -864,6 +879,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
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else
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data = 0xffb80d20;
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ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
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data = 0;
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}
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/*
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@ -883,7 +899,6 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
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/*
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* Write RF registers
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* TODO:Does this work on 5211 (5111) ?
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*/
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ret = ath5k_hw_rfregs(ah, channel, mode);
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if (ret)
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@ -1048,7 +1063,8 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
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ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
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/*
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* 5111/5112 Specific
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* On 5211+ read activation -> rx delay
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* and use it.
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*/
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if (ah->ah_version != AR5K_AR5210) {
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data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
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@ -1056,7 +1072,8 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
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data = (channel->hw_value & CHANNEL_CCK) ?
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((data << 2) / 22) : (data / 10);
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udelay(100 + data);
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udelay(100 + (2 * data));
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data = 0;
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} else {
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mdelay(1);
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}
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@ -1139,6 +1156,12 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
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ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
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ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
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ath5k_hw_reg_write(ah, ah->ah_phy_spending, AR5K_PHY_SPENDING);
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data = ath5k_hw_reg_read(ah, AR5K_USEC_5211) & 0xffffc07f ;
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data |= (ah->ah_phy_spending == AR5K_PHY_SPENDING_18) ?
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0x00000f80 : 0x00001380 ;
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ath5k_hw_reg_write(ah, data, AR5K_USEC_5211);
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data = 0;
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}
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if (ah->ah_version == AR5K_AR5212) {
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