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ARM: SoC DT updates for 3.19, part 2

Browse Source 
This is a follow-up to the early ARM SoC DT changes, with additional
 content that has external dependencies:
 
 * The Tegra IOMMU DT support depends on changes from the iommu
   tree, plus the contents of the arm-soc drivers branch
 * The MVEBU PHY support depends on changes from the phy tree
 * The AT91 DT support depends on changes from the RTC and
   DMA-slave trees
 
 All of these changes just enable additional devices for
 existing platforms.
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Merge tag 'dt2-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC DT updates part 2 from Arnd Bergmann:
 "This is a follow-up to the early ARM SoC DT changes, with additional
  content that has external dependencies:

   - The Tegra IOMMU DT support depends on changes from the iommu tree,
     plus the contents of the arm-soc drivers branch
   - The MVEBU PHY support depends on changes from the phy tree
   - The AT91 DT support depends on changes from the RTC and DMA-slave
     trees

  All of these changes just enable additional devices for existing
  platforms"

* tag 'dt2-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: tegra: Enable IOMMU for display controllers on Tegra124
  ARM: tegra: Enable IOMMU for display controllers on Tegra114
  ARM: tegra: Enable IOMMU for display controllers on Tegra30
  ARM: tegra: Add memory controller support for Tegra124
  ARM: tegra: Add memory controller support for Tegra114
  ARM: tegra: Add memory controller support for Tegra30
  ARM: tegra: Add APB_MISC_GP as a MIPI pad control bank
  ARM: mvebu: add PHY support to the dts for the USB controllers on Armada 375
  ARM: mvebu: add Device Tree description of USB cluster controller on Armada 375
  ARM: at91/dt: at91sam9g45: add ISI node
  ARM: at91/dt: enable the RTT block on the at91sam9m10g45ek board
  ARM: at91/dt: enable the RTT block on the sam9g20ek board
  ARM: at91/dt: add GPBR nodes
  ARM: at91/dt: add RTT nodes to at91 dtsis
  ARM: at91/dt: at91sam9rl: add rtc
  ARM: at91: fix GPLv2 wording
  ARM: at91/dt: sama5d4: add DMA support
  ARM: at91/dt: sama5d4: use macro instead of numeric value
This commit is contained in:
Linus Torvalds 2014-12-16 14:26:26 -08:00
commit 205dc205ed
13 changed files with 268 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arm/boot/dts/armada-375.dtsi
View File

@ -14,6 +14,7 @@
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
@ -348,6 +349,12 @@
#clock-cells = <1>;
};
usbcluster: usb-cluster@18400 {
compatible = "marvell,armada-375-usb-cluster";
reg = <0x18400 0x4>;
#phy-cells = <1>;
};
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x100>, <0x20180 0x20>;
@ -398,6 +405,8 @@
reg = <0x50000 0x500>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 18>;
phys = <&usbcluster PHY_TYPE_USB2>;
phy-names = "usb";
status = "disabled";
};
@ -414,6 +423,8 @@
reg = <0x58000 0x20000>,<0x5b880 0x80>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 16>;
phys = <&usbcluster PHY_TYPE_USB3>;
phy-names = "usb";
status = "disabled";
};

4
arch/arm/boot/dts/at91-sama5d4ek.dts
View File

@ -9,12 +9,12 @@
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.

14
arch/arm/boot/dts/at91sam9260.dtsi
View File

@ -956,6 +956,14 @@
};
};
rtc@fffffd20 {
compatible = "atmel,at91sam9260-rtt";
reg = <0xfffffd20 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
status = "disabled";
};
watchdog@fffffd40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
@ -966,6 +974,12 @@
atmel,idle-halt;
status = "disabled";
};
gpbr: syscon@fffffd50 {
compatible = "atmel,at91sam9260-gpbr", "syscon";
reg = <0xfffffd50 0x10>;
status = "disabled";
};
};
nand0: nand@40000000 {

14
arch/arm/boot/dts/at91sam9261.dtsi
View File

@ -828,12 +828,26 @@
clocks = <&mck>;
};
rtc@fffffd20 {
compatible = "atmel,at91sam9260-rtt";
reg = <0xfffffd20 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&slow_xtal>;
status = "disabled";
};
watchdog@fffffd40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
status = "disabled";
};
gpbr: syscon@fffffd50 {
compatible = "atmel,at91sam9260-gpbr", "syscon";
reg = <0xfffffd50 0x10>;
status = "disabled";
};
};
};

21
arch/arm/boot/dts/at91sam9263.dtsi
View File

@ -922,6 +922,27 @@
pinctrl-0 = <&pinctrl_can_rx_tx>;
clocks = <&can_clk>;
clock-names = "can_clk";
};
rtc@fffffd20 {
compatible = "atmel,at91sam9260-rtt";
reg = <0xfffffd20 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&slow_xtal>;
status = "disabled";
};
rtc@fffffd50 {
compatible = "atmel,at91sam9260-rtt";
reg = <0xfffffd50 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&slow_xtal>;
status = "disabled";
};
gpbr: syscon@fffffd60 {
compatible = "atmel,at91sam9260-gpbr", "syscon";
reg = <0xfffffd60 0x50>;
status = "disabled";
};
};

14
arch/arm/boot/dts/at91sam9g20ek_common.dtsi
View File

@ -112,9 +112,23 @@
};
};
shdwc@fffffd10 {
atmel,wakeup-counter = <10>;
atmel,wakeup-rtt-timer;
};
rtc@fffffd20 {
atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
status = "okay";
};
watchdog@fffffd40 {
status = "okay";
};
gpbr: syscon@fffffd50 {
status = "okay";
};
};
nand0: nand@40000000 {

46
arch/arm/boot/dts/at91sam9g45.dtsi
View File

@ -492,6 +492,27 @@
};
};
isi {
pinctrl_isi: isi-0 {
atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */
AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* D9 */
AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */
AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* D11 */
AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */
AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */
AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */
AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */
AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */
AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */
AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */
AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */
AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */
AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */
AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* HSYNC */
AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* MCK */>;
};
};
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
@ -1035,6 +1056,17 @@
};
};
isi@fffb4000 {
compatible = "atmel,at91sam9g45-isi";
reg = <0xfffb4000 0x4000>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>;
clocks = <&isi_clk>;
clock-names = "isi_clk";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isi>;
status = "disabled";
};
pwm0: pwm@fffb8000 {
compatible = "atmel,at91sam9rl-pwm";
reg = <0xfffb8000 0x300>;
@ -1199,12 +1231,26 @@
};
};
rtc@fffffd20 {
compatible = "atmel,at91sam9260-rtt";
reg = <0xfffffd20 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
status = "disabled";
};
rtc@fffffdb0 {
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffdb0 0x30>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
status = "disabled";
};
gpbr: syscon@fffffd60 {
compatible = "atmel,at91sam9260-gpbr", "syscon";
reg = <0xfffffd60 0x10>;
status = "disabled";
};
};
fb0: fb@0x00500000 {

9
arch/arm/boot/dts/at91sam9m10g45ek.dts
View File

@ -161,6 +161,15 @@
pinctrl-0 = <&pinctrl_pwm_leds>;
};
rtc@fffffd20 {
atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
status = "okay";
};
gpbr: syscon@fffffd60 {
status = "okay";
};
rtc@fffffdb0 {
status = "okay";
};

21
arch/arm/boot/dts/at91sam9rl.dtsi
View File

@ -1059,6 +1059,27 @@
clocks = <&slow_rc_osc &slow_osc>;
};
};
rtc@fffffeb0 {
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffeb0 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
status = "disabled";
};
rtc@fffffd20 {
compatible = "atmel,at91sam9260-rtt";
reg = <0xfffffd20 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
status = "disabled";
};
gpbr: syscon@fffffd60 {
compatible = "atmel,at91sam9260-gpbr", "syscon";
reg = <0xfffffd60 0x10>;
status = "disabled";
};
};
};

75
arch/arm/boot/dts/sama5d4.dtsi
View File

@ -9,12 +9,12 @@
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
@ -45,6 +45,7 @@
#include "skeleton.dtsi"
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
@ -302,6 +303,15 @@
#size-cells = <1>;
ranges;
dma1: dma-controller@f0004000 {
compatible = "atmel,sama5d4-dma";
reg = <0xf0004000 0x200>;
interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <1>;
clocks = <&dma1_clk>;
clock-names = "dma_clk";
};
ramc0: ramc@f0010000 {
compatible = "atmel,sama5d3-ddramc";
reg = <0xf0010000 0x200>;
@ -309,6 +319,15 @@
clock-names = "ddrck", "mpddr";
};
dma0: dma-controller@f0014000 {
compatible = "atmel,sama5d4-dma";
reg = <0xf0014000 0x200>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <1>;
clocks = <&dma0_clk>;
clock-names = "dma_clk";
};
pmc: pmc@f0018000 {
compatible = "atmel,sama5d3-pmc";
reg = <0xf0018000 0x120>;
@ -761,6 +780,10 @@
compatible = "atmel,hsmci";
reg = <0xf8000000 0x600>;
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(0))>;
dma-names = "rxtx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
status = "disabled";
@ -776,6 +799,13 @@
compatible = "atmel,at91rm9200-spi";
reg = <0xf8010000 0x100>;
interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
dmas = <&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(10))>,
<&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(11))>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&spi0_clk>;
@ -787,6 +817,13 @@
compatible = "atmel,at91sam9x5-i2c";
reg = <0xf8014000 0x4000>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
dmas = <&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(2))>,
<&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(3))>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
#address-cells = <1>;
@ -817,7 +854,14 @@
i2c2: i2c@f8024000 {
compatible = "atmel,at91sam9x5-i2c";
reg = <0xf8024000 0x4000>;
interrupts = <34 4 6>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
dmas = <&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(6))>,
<&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(7))>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
#address-cells = <1>;
@ -830,6 +874,10 @@
compatible = "atmel,hsmci";
reg = <0xfc000000 0x600>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(1))>;
dma-names = "rxtx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
status = "disabled";
@ -843,6 +891,13 @@
compatible = "atmel,at91sam9260-usart";
reg = <0xfc008000 0x100>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
dmas = <&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(16))>,
<&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(17))>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
clocks = <&usart2_clk>;
@ -854,6 +909,13 @@
compatible = "atmel,at91sam9260-usart";
reg = <0xfc00c000 0x100>;
interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
dmas = <&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(18))>,
<&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(19))>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
clocks = <&usart3_clk>;
@ -865,6 +927,13 @@
compatible = "atmel,at91sam9260-usart";
reg = <0xfc010000 0x100>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
dmas = <&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(20))>,
<&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(21))>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart4>;
clocks = <&usart4_clk>;

23
arch/arm/boot/dts/tegra114.dtsi
View File

@ -1,5 +1,6 @@
#include <dt-bindings/clock/tegra114-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/memory/tegra114-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -50,6 +51,8 @@
resets = <&tegra_car 27>;
reset-names = "dc";
iommus = <&mc TEGRA_SWGROUP_DC>;
nvidia,head = <0>;
rgb {
@ -67,6 +70,8 @@
resets = <&tegra_car 26>;
reset-names = "dc";
iommus = <&mc TEGRA_SWGROUP_DCB>;
nvidia,head = <1>;
rgb {
@ -498,15 +503,15 @@
reset-names = "fuse";
};
iommu@70019010 {
compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
reg = <0x70019010 0x02c
0x700191f0 0x010
0x70019228 0x074>;
nvidia,#asids = <4>;
dma-window = <0 0x40000000>;
nvidia,swgroups = <0x18659fe>;
nvidia,ahb = <&ahb>;
mc: memory-controller@70019000 {
compatible = "nvidia,tegra114-mc";
reg = <0x70019000 0x1000>;
clocks = <&tegra_car TEGRA114_CLK_MC>;
clock-names = "mc";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
};
ahub@70080000 {

19
arch/arm/boot/dts/tegra124.dtsi
View File

@ -1,5 +1,6 @@
#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/memory/tegra124-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -102,6 +103,8 @@
resets = <&tegra_car 27>;
reset-names = "dc";
iommus = <&mc TEGRA_SWGROUP_DC>;
nvidia,head = <0>;
};
@ -115,6 +118,8 @@
resets = <&tegra_car 26>;
reset-names = "dc";
iommus = <&mc TEGRA_SWGROUP_DCB>;
nvidia,head = <1>;
};
@ -275,7 +280,8 @@
pinmux: pinmux@0,70000868 {
compatible = "nvidia,tegra124-pinmux";
reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
<0x0 0x70003000 0x0 0x434>; /* Mux registers */
<0x0 0x70003000 0x0 0x434>, /* Mux registers */
<0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
};
/*
@ -551,6 +557,17 @@
reset-names = "fuse";
};
mc: memory-controller@0,70019000 {
compatible = "nvidia,tegra124-mc";
reg = <0x0 0x70019000 0x0 0x1000>;
clocks = <&tegra_car TEGRA124_CLK_MC>;
clock-names = "mc";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
};
sata@0,70020000 {
compatible = "nvidia,tegra124-ahci";

27
arch/arm/boot/dts/tegra30.dtsi
View File

@ -1,5 +1,6 @@
#include <dt-bindings/clock/tegra30-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/memory/tegra30-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -166,6 +167,8 @@
resets = <&tegra_car 27>;
reset-names = "dc";
iommus = <&mc TEGRA_SWGROUP_DC>;
nvidia,head = <0>;
rgb {
@ -183,6 +186,8 @@
resets = <&tegra_car 26>;
reset-names = "dc";
iommus = <&mc TEGRA_SWGROUP_DCB>;
nvidia,head = <1>;
rgb {
@ -615,23 +620,15 @@
clock-names = "pclk", "clk32k_in";
};
memory-controller@7000f000 {
mc: memory-controller@7000f000 {
compatible = "nvidia,tegra30-mc";
reg = <0x7000f000 0x010
0x7000f03c 0x1b4
0x7000f200 0x028
0x7000f284 0x17c>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
};
reg = <0x7000f000 0x400>;
clocks = <&tegra_car TEGRA30_CLK_MC>;
clock-names = "mc";
iommu@7000f010 {
compatible = "nvidia,tegra30-smmu";
reg = <0x7000f010 0x02c
0x7000f1f0 0x010
0x7000f228 0x05c>;
nvidia,#asids = <4>; /* # of ASIDs */
dma-window = <0 0x40000000>; /* IOVA start & length */
nvidia,ahb = <&ahb>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
};
fuse@7000f800 {