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drm/xe/xe2: Introduce performance changes
Add Compression Performance Improvement Changes in Xe2 v2: Rebase v3: Rebase, updated as per latest changes on bspec, Removed unnecessary default actions (Matt) formatting nits (Tejas) v4: Formatting nits, removed default set action for bit 14 (Matt) Bspec: 72161 Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/c2dd753fdc55df6a6432026f2df9c2684a0d25c1.1722607628.git.akshata.jahagirdar@intel.com
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@ -367,6 +367,9 @@
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#define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4)
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#define XEHP_LNESPARE REG_BIT(19)
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#define L3SQCREG2 XE_REG_MCR(0xb104)
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#define COMPMEMRD256BOVRFETCHEN REG_BIT(20)
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#define L3SQCREG3 XE_REG_MCR(0xb108)
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#define COMPPWOVERFETCHEN REG_BIT(28)
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@ -45,6 +45,11 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
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XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
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},
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{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
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XE_RTP_ACTIONS(SET(L3SQCREG2,
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COMPMEMRD256BOVRFETCHEN))
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},
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{}
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};
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