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habanalabs: re-factor H/W queues initialization
We want to remove the following restrictions/assumptions in our driver: 1. The H/W queue index is also the completion queue index. 2. The H/W queue index is also the IRQ number of the completion queue. 3. All queues of the same type have consecutive indexes. Therefore we add the support for H/W queues of the same type with nonconsecutive indexes and completion queue index and IRQ number different than the H/W queue index. Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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@ -1062,7 +1062,7 @@ out_err:
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*/
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int hl_device_init(struct hl_device *hdev, struct class *hclass)
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{
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int i, rc, cq_ready_cnt;
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int i, rc, cq_cnt, cq_ready_cnt;
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char *name;
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bool add_cdev_sysfs_on_err = false;
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@ -1120,14 +1120,16 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass)
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goto sw_fini;
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}
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cq_cnt = hdev->asic_prop.completion_queues_count;
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/*
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* Initialize the completion queues. Must be done before hw_init,
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* because there the addresses of the completion queues are being
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* passed as arguments to request_irq
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*/
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hdev->completion_queue =
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kcalloc(hdev->asic_prop.completion_queues_count,
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sizeof(*hdev->completion_queue), GFP_KERNEL);
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hdev->completion_queue = kcalloc(cq_cnt,
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sizeof(*hdev->completion_queue),
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GFP_KERNEL);
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if (!hdev->completion_queue) {
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dev_err(hdev->dev, "failed to allocate completion queues\n");
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@ -1135,10 +1137,9 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass)
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goto hw_queues_destroy;
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}
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for (i = 0, cq_ready_cnt = 0;
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i < hdev->asic_prop.completion_queues_count;
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i++, cq_ready_cnt++) {
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rc = hl_cq_init(hdev, &hdev->completion_queue[i], i);
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for (i = 0, cq_ready_cnt = 0 ; i < cq_cnt ; i++, cq_ready_cnt++) {
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rc = hl_cq_init(hdev, &hdev->completion_queue[i],
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hdev->asic_funcs->get_queue_id_for_cq(hdev, i));
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if (rc) {
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dev_err(hdev->dev,
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"failed to initialize completion queue\n");
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@ -890,6 +890,7 @@ void goya_init_dma_qmans(struct hl_device *hdev)
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q = &hdev->kernel_queues[0];
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for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) {
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q->cq_id = q->msi_vec = i;
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goya_init_dma_qman(hdev, i, q->bus_address);
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goya_init_dma_ch(hdev, i);
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}
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@ -5273,6 +5274,11 @@ static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev)
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return RREG32(mmHW_STATE);
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}
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u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx)
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{
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return cq_idx;
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}
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static const struct hl_asic_funcs goya_funcs = {
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.early_init = goya_early_init,
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.early_fini = goya_early_fini,
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@ -5332,7 +5338,8 @@ static const struct hl_asic_funcs goya_funcs = {
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.rreg = hl_rreg,
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.wreg = hl_wreg,
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.halt_coresight = goya_halt_coresight,
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.get_clk_rate = goya_get_clk_rate
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.get_clk_rate = goya_get_clk_rate,
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.get_queue_id_for_cq = goya_get_queue_id_for_cq
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};
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/*
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@ -234,5 +234,6 @@ void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
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void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev);
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int goya_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
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u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx);
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#endif /* GOYAP_H_ */
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@ -365,6 +365,8 @@ struct hl_cs_job;
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* @pi: holds the queue's pi value.
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* @ci: holds the queue's ci value, AS CALCULATED BY THE DRIVER (not real ci).
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* @hw_queue_id: the id of the H/W queue.
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* @cq_id: the id for the corresponding CQ for this H/W queue.
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* @msi_vec: the IRQ number of the H/W queue.
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* @int_queue_len: length of internal queue (number of entries).
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* @valid: is the queue valid (we have array of 32 queues, not all of them
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* exists).
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@ -377,6 +379,8 @@ struct hl_hw_queue {
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u32 pi;
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u32 ci;
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u32 hw_queue_id;
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u32 cq_id;
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u32 msi_vec;
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u16 int_queue_len;
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u8 valid;
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};
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@ -534,6 +538,7 @@ enum hl_pll_frequency {
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* @wreg: Write a register. Needed for simulator support.
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* @halt_coresight: stop the ETF and ETR traces.
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* @get_clk_rate: Retrieve the ASIC current and maximum clock rate in MHz
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* @get_queue_id_for_cq: Get the H/W queue id related to the given CQ index.
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*/
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struct hl_asic_funcs {
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int (*early_init)(struct hl_device *hdev);
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@ -620,6 +625,7 @@ struct hl_asic_funcs {
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void (*wreg)(struct hl_device *hdev, u32 reg, u32 val);
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void (*halt_coresight)(struct hl_device *hdev);
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int (*get_clk_rate)(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
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u32 (*get_queue_id_for_cq)(struct hl_device *hdev, u32 cq_idx);
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};
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@ -111,7 +111,7 @@ static int ext_queue_sanity_checks(struct hl_device *hdev,
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bool reserve_cq_entry)
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{
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atomic_t *free_slots =
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&hdev->completion_queue[q->hw_queue_id].free_slots_cnt;
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&hdev->completion_queue[q->cq_id].free_slots_cnt;
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int free_slots_cnt;
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/* Check we have enough space in the queue */
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@ -194,7 +194,7 @@ static int hw_queue_sanity_checks(struct hl_device *hdev, struct hl_hw_queue *q,
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int num_of_entries)
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{
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atomic_t *free_slots =
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&hdev->completion_queue[q->hw_queue_id].free_slots_cnt;
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&hdev->completion_queue[q->cq_id].free_slots_cnt;
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/*
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* Check we have enough space in the completion queue.
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@ -308,13 +308,13 @@ static void ext_queue_schedule_job(struct hl_cs_job *job)
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* No need to check if CQ is full because it was already
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* checked in ext_queue_sanity_checks
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*/
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cq = &hdev->completion_queue[q->hw_queue_id];
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cq = &hdev->completion_queue[q->cq_id];
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cq_addr = cq->bus_address + cq->pi * sizeof(struct hl_cq_entry);
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hdev->asic_funcs->add_end_of_cb_packets(hdev, cb->kernel_address, len,
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cq_addr,
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le32_to_cpu(cq_pkt.data),
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q->hw_queue_id);
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q->msi_vec);
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q->shadow_queue[hl_pi_2_offset(q->pi)] = job;
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@ -401,7 +401,7 @@ static void hw_queue_schedule_job(struct hl_cs_job *job)
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* No need to check if CQ is full because it was already
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* checked in hw_queue_sanity_checks
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*/
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cq = &hdev->completion_queue[q->hw_queue_id];
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cq = &hdev->completion_queue[q->cq_id];
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cq->pi = hl_cq_inc_ptr(cq->pi);
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ext_and_hw_queue_submit_bd(hdev, q, ctl, len, ptr);
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