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drm/radeon: sun/hainan chips do not have UVD (v2)
Skip UVD handling on them. v2: split has_uvd tracking into separate patch Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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948bee3ff4
commit
1df0d523dd
@ -2635,9 +2635,11 @@ static void si_gpu_init(struct radeon_device *rdev)
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WREG32(HDP_ADDR_CONFIG, gb_addr_config);
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WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
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WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
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WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
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WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
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WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
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if (rdev->has_uvd) {
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WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
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WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
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WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
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}
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si_tiling_mode_table_init(rdev);
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@ -5213,15 +5215,17 @@ static int si_startup(struct radeon_device *rdev)
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return r;
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}
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r = rv770_uvd_resume(rdev);
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if (!r) {
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r = radeon_fence_driver_start_ring(rdev,
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R600_RING_TYPE_UVD_INDEX);
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if (rdev->has_uvd) {
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r = rv770_uvd_resume(rdev);
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if (!r) {
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r = radeon_fence_driver_start_ring(rdev,
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R600_RING_TYPE_UVD_INDEX);
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if (r)
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dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
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}
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if (r)
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dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
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rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
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}
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if (r)
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rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
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/* Enable IRQ */
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r = si_irq_init(rdev);
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@ -5280,16 +5284,18 @@ static int si_startup(struct radeon_device *rdev)
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if (r)
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return r;
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ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
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if (ring->ring_size) {
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r = radeon_ring_init(rdev, ring, ring->ring_size,
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R600_WB_UVD_RPTR_OFFSET,
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UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
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0, 0xfffff, RADEON_CP_PACKET2);
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if (!r)
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r = r600_uvd_init(rdev);
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if (r)
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DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
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if (rdev->has_uvd) {
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ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
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if (ring->ring_size) {
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r = radeon_ring_init(rdev, ring, ring->ring_size,
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R600_WB_UVD_RPTR_OFFSET,
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UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
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0, 0xfffff, RADEON_CP_PACKET2);
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if (!r)
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r = r600_uvd_init(rdev);
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if (r)
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DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
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}
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}
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r = radeon_ib_pool_init(rdev);
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@ -5338,8 +5344,10 @@ int si_suspend(struct radeon_device *rdev)
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radeon_vm_manager_fini(rdev);
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si_cp_enable(rdev, false);
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cayman_dma_stop(rdev);
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r600_uvd_rbc_stop(rdev);
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radeon_uvd_suspend(rdev);
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if (rdev->has_uvd) {
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r600_uvd_rbc_stop(rdev);
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radeon_uvd_suspend(rdev);
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}
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si_irq_suspend(rdev);
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radeon_wb_disable(rdev);
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si_pcie_gart_disable(rdev);
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@ -5427,11 +5435,13 @@ int si_init(struct radeon_device *rdev)
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ring->ring_obj = NULL;
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r600_ring_init(rdev, ring, 64 * 1024);
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r = radeon_uvd_init(rdev);
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if (!r) {
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ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
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ring->ring_obj = NULL;
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r600_ring_init(rdev, ring, 4096);
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if (rdev->has_uvd) {
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r = radeon_uvd_init(rdev);
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if (!r) {
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ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
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ring->ring_obj = NULL;
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r600_ring_init(rdev, ring, 4096);
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}
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}
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rdev->ih.ring_obj = NULL;
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@ -5479,7 +5489,8 @@ void si_fini(struct radeon_device *rdev)
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radeon_vm_manager_fini(rdev);
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radeon_ib_pool_fini(rdev);
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radeon_irq_kms_fini(rdev);
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radeon_uvd_fini(rdev);
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if (rdev->has_uvd)
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radeon_uvd_fini(rdev);
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si_pcie_gart_fini(rdev);
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r600_vram_scratch_fini(rdev);
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radeon_gem_fini(rdev);
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