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arm64: dts: imx8dxl: add adc0 support

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Add adc0 and adc1 node at imx8 common dma subsystem.
imx8dxl have only adc0. Change irq number for adc0.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Frank Li 2022-11-11 10:47:37 -05:00 committed by Shawn Guo
parent e59418a46c
commit 1db044b25d
2 changed files with 56 additions and 0 deletions
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52
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
View File

@ -156,6 +156,34 @@ dma_subsys: bus@5a000000 {
status = "disabled"; status = "disabled";
}; };
adc0: adc@5a880000 {
compatible = "nxp,imx8qxp-adc";
reg = <0x5a880000 0x10000>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adc0_lpcg 0>,
<&adc0_lpcg 1>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_ADC_0>;
status = "disabled";
};
adc1: adc@5a890000 {
compatible = "nxp,imx8qxp-adc";
reg = <0x5a890000 0x10000>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adc1_lpcg 0>,
<&adc1_lpcg 1>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_ADC_1>;
status = "disabled";
};
i2c0_lpcg: clock-controller@5ac00000 { i2c0_lpcg: clock-controller@5ac00000 {
compatible = "fsl,imx8qxp-lpcg"; compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac00000 0x10000>; reg = <0x5ac00000 0x10000>;
@ -203,4 +231,28 @@ dma_subsys: bus@5a000000 {
"i2c3_lpcg_ipg_clk"; "i2c3_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_I2C_3>; power-domains = <&pd IMX_SC_R_I2C_3>;
}; };
adc0_lpcg: clock-controller@5ac80000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac80000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "adc0_lpcg_clk",
"adc0_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_ADC_0>;
};
adc1_lpcg: clock-controller@5ac90000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac90000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "adc1_lpcg_clk",
"adc1_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_ADC_1>;
};
}; };

4
arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
View File

@ -11,6 +11,10 @@
clock-frequency = <160000000>; clock-frequency = <160000000>;
}; };
&adc0 {
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
};
&i2c0 { &i2c0 {
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;