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- mailbox api: allow direct registration to a channel

Browse Source 
Convert omap and pcc to use mbox_bind_client
 - omap and hi6220 : use of_property_read_bool
 - test: fix double-free and use spinlock header
 - rockchip and bcm-pdc: drop of_match_ptr
 - mpfs: change config symbol
 - mediatek gce: support MT6795
 - qcom apcs: consolidate of_device_id
 			 support IPQ9574
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Merge tag 'mailbox-v6.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration

Pull mailbox updates from Jassi Brar:

 - mailbox api: allow direct registration to a channel and convert omap
   and pcc to use mbox_bind_client

 - omap and hi6220 : use of_property_read_bool

 - test: fix double-free and use spinlock header

 - rockchip and bcm-pdc: drop of_match_ptr

 - mpfs: change config symbol

 - mediatek gce: support MT6795

 - qcom apcs: consolidate of_device_id and support IPQ9574

* tag 'mailbox-v6.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  dt-bindings: mailbox: qcom: add compatible for IPQ9574 SoC
  mailbox: qcom-apcs-ipc: do not grow the of_device_id
  dt-bindings: mailbox: qcom,apcs-kpss-global: use fallbacks for few variants
  dt-bindings: mailbox: mediatek,gce-mailbox: Add support for MT6795
  mailbox: mpfs: convert SOC_MICROCHIP_POLARFIRE to ARCH_MICROCHIP_POLARFIRE
  mailbox: bcm-pdc: drop of_match_ptr for ID table
  mailbox: rockchip: drop of_match_ptr for ID table
  mailbox: mailbox-test: Fix potential double-free in mbox_test_message_write()
  mailbox: mailbox-test: Explicitly include header for spinlock support
  mailbox: Use of_property_read_bool() for boolean properties
  mailbox: pcc: Use mbox_bind_client
  mailbox: omap: Use mbox_bind_client
  mailbox: Allow direct registration to a channel
This commit is contained in:
Linus Torvalds 2023-05-07 10:17:33 -07:00
commit 1c1094e47e
13 changed files with 288 additions and 122 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
View File

@ -16,14 +16,18 @@ description:
properties:
compatible:
enum:
- mediatek,mt6779-gce
- mediatek,mt8173-gce
- mediatek,mt8183-gce
- mediatek,mt8186-gce
- mediatek,mt8188-gce
- mediatek,mt8192-gce
- mediatek,mt8195-gce
oneOf:
- enum:
- mediatek,mt6779-gce
- mediatek,mt8173-gce
- mediatek,mt8183-gce
- mediatek,mt8186-gce
- mediatek,mt8188-gce
- mediatek,mt8192-gce
- mediatek,mt8195-gce
- items:
- const: mediatek,mt6795-gce
- const: mediatek,mt8173-gce
"#mbox-cells":
const: 2

31
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
View File

@ -19,22 +19,15 @@ properties:
- items:
- enum:
- qcom,ipq5332-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
- qcom,ipq9574-apcs-apps-global
- const: qcom,ipq6018-apcs-apps-global
- items:
- enum:
- qcom,ipq6018-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
- qcom,msm8996-apcs-hmss-global
- qcom,msm8998-apcs-hmss-global
- qcom,qcm2290-apcs-hmss-global
- qcom,sc7180-apss-shared
- qcom,sc8180x-apss-shared
- qcom,sdm660-apcs-hmss-global
- qcom,sdm845-apss-shared
- qcom,sm4250-apcs-hmss-global
- qcom,sm6125-apcs-hmss-global
- qcom,sm6115-apcs-hmss-global
- qcom,sm8150-apss-shared
- const: qcom,sdm845-apss-shared
- items:
- enum:
- qcom,msm8916-apcs-kpss-global
@ -45,6 +38,18 @@ properties:
- qcom,qcs404-apcs-apps-global
- qcom,sdx55-apcs-gcc
- const: syscon
- enum:
- qcom,ipq6018-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
- qcom,msm8996-apcs-hmss-global
- qcom,msm8998-apcs-hmss-global
- qcom,qcm2290-apcs-hmss-global
- qcom,sdm660-apcs-hmss-global
- qcom,sdm845-apss-shared
- qcom,sm4250-apcs-hmss-global
- qcom,sm6115-apcs-hmss-global
- qcom,sm6125-apcs-hmss-global
reg:
maxItems: 1
@ -88,6 +93,7 @@ allOf:
items:
- const: pll
- const: aux
- if:
properties:
compatible:
@ -112,7 +118,6 @@ allOf:
contains:
enum:
- qcom,ipq6018-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
then:
properties:
clocks:
@ -134,14 +139,11 @@ allOf:
- qcom,msm8996-apcs-hmss-global
- qcom,msm8998-apcs-hmss-global
- qcom,qcm2290-apcs-hmss-global
- qcom,sc7180-apss-shared
- qcom,sc8180x-apss-shared
- qcom,sdm660-apcs-hmss-global
- qcom,sdm845-apss-shared
- qcom,sm4250-apcs-hmss-global
- qcom,sm6115-apcs-hmss-global
- qcom,sm6125-apcs-hmss-global
- qcom,sm8150-apss-shared
then:
properties:
clocks: false
@ -153,7 +155,6 @@ allOf:
contains:
enum:
- qcom,ipq6018-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
then:
properties:
'#clock-cells':

2
drivers/mailbox/Kconfig
View File

@ -176,7 +176,7 @@ config MAILBOX_TEST
config POLARFIRE_SOC_MAILBOX
tristate "PolarFire SoC (MPFS) Mailbox"
depends on HAS_IOMEM
depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST
depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST
help
This driver adds support for the PolarFire SoC (MPFS) mailbox controller.

2
drivers/mailbox/bcm-pdc-mailbox.c
View File

@ -1635,7 +1635,7 @@ static struct platform_driver pdc_mbox_driver = {
.remove = pdc_remove,
.driver = {
.name = "brcm-iproc-pdc-mbox",
.of_match_table = of_match_ptr(pdc_mbox_of_match),
.of_match_table = pdc_mbox_of_match,
},
};
module_platform_driver(pdc_mbox_driver);

5
drivers/mailbox/hi6220-mailbox.c
View File

@ -325,10 +325,7 @@ static int hi6220_mbox_probe(struct platform_device *pdev)
writel(~0x0, ACK_INT_CLR_REG(mbox->ipc));
/* use interrupt for tx's ack */
if (of_find_property(node, "hi6220,mbox-tx-noirq", NULL))
mbox->tx_irq_mode = false;
else
mbox->tx_irq_mode = true;
mbox->tx_irq_mode = !of_property_read_bool(node, "hi6220,mbox-tx-noirq");
if (mbox->tx_irq_mode)
mbox->controller.txdone_irq = true;

8
drivers/mailbox/mailbox-test.c
View File

@ -12,10 +12,12 @@
#include <linux/kernel.h>
#include <linux/mailbox_client.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/poll.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/uaccess.h>
#include <linux/sched/signal.h>
@ -38,6 +40,7 @@ struct mbox_test_device {
char *signal;
char *message;
spinlock_t lock;
struct mutex mutex;
wait_queue_head_t waitq;
struct fasync_struct *async_queue;
struct dentry *root_debugfs_dir;
@ -110,6 +113,8 @@ static ssize_t mbox_test_message_write(struct file *filp,
return -EINVAL;
}
mutex_lock(&tdev->mutex);
tdev->message = kzalloc(MBOX_MAX_MSG_LEN, GFP_KERNEL);
if (!tdev->message)
return -ENOMEM;
@ -144,6 +149,8 @@ out:
kfree(tdev->message);
tdev->signal = NULL;
mutex_unlock(&tdev->mutex);
return ret < 0 ? ret : count;
}
@ -392,6 +399,7 @@ static int mbox_test_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, tdev);
spin_lock_init(&tdev->lock);
mutex_init(&tdev->mutex);
if (tdev->rx_channel) {
tdev->rx_buffer = devm_kzalloc(&pdev->dev,

96
drivers/mailbox/mailbox.c
View File

@ -317,6 +317,71 @@ int mbox_flush(struct mbox_chan *chan, unsigned long timeout)
}
EXPORT_SYMBOL_GPL(mbox_flush);
static int __mbox_bind_client(struct mbox_chan *chan, struct mbox_client *cl)
{
struct device *dev = cl->dev;
unsigned long flags;
int ret;
if (chan->cl || !try_module_get(chan->mbox->dev->driver->owner)) {
dev_dbg(dev, "%s: mailbox not free\n", __func__);
return -EBUSY;
}
spin_lock_irqsave(&chan->lock, flags);
chan->msg_free = 0;
chan->msg_count = 0;
chan->active_req = NULL;
chan->cl = cl;
init_completion(&chan->tx_complete);
if (chan->txdone_method == TXDONE_BY_POLL && cl->knows_txdone)
chan->txdone_method = TXDONE_BY_ACK;
spin_unlock_irqrestore(&chan->lock, flags);
if (chan->mbox->ops->startup) {
ret = chan->mbox->ops->startup(chan);
if (ret) {
dev_err(dev, "Unable to startup the chan (%d)\n", ret);
mbox_free_channel(chan);
return ret;
}
}
return 0;
}
/**
* mbox_bind_client - Request a mailbox channel.
* @chan: The mailbox channel to bind the client to.
* @cl: Identity of the client requesting the channel.
*
* The Client specifies its requirements and capabilities while asking for
* a mailbox channel. It can't be called from atomic context.
* The channel is exclusively allocated and can't be used by another
* client before the owner calls mbox_free_channel.
* After assignment, any packet received on this channel will be
* handed over to the client via the 'rx_callback'.
* The framework holds reference to the client, so the mbox_client
* structure shouldn't be modified until the mbox_free_channel returns.
*
* Return: 0 if the channel was assigned to the client successfully.
* <0 for request failure.
*/
int mbox_bind_client(struct mbox_chan *chan, struct mbox_client *cl)
{
int ret;
mutex_lock(&con_mutex);
ret = __mbox_bind_client(chan, cl);
mutex_unlock(&con_mutex);
return ret;
}
EXPORT_SYMBOL_GPL(mbox_bind_client);
/**
* mbox_request_channel - Request a mailbox channel.
* @cl: Identity of the client requesting the channel.
@ -340,7 +405,6 @@ struct mbox_chan *mbox_request_channel(struct mbox_client *cl, int index)
struct mbox_controller *mbox;
struct of_phandle_args spec;
struct mbox_chan *chan;
unsigned long flags;
int ret;
if (!dev || !dev->of_node) {
@ -372,33 +436,9 @@ struct mbox_chan *mbox_request_channel(struct mbox_client *cl, int index)
return chan;
}
if (chan->cl || !try_module_get(mbox->dev->driver->owner)) {
dev_dbg(dev, "%s: mailbox not free\n", __func__);
mutex_unlock(&con_mutex);
return ERR_PTR(-EBUSY);
}
spin_lock_irqsave(&chan->lock, flags);
chan->msg_free = 0;
chan->msg_count = 0;
chan->active_req = NULL;
chan->cl = cl;
init_completion(&chan->tx_complete);
if (chan->txdone_method == TXDONE_BY_POLL && cl->knows_txdone)
chan->txdone_method = TXDONE_BY_ACK;
spin_unlock_irqrestore(&chan->lock, flags);
if (chan->mbox->ops->startup) {
ret = chan->mbox->ops->startup(chan);
if (ret) {
dev_err(dev, "Unable to startup the chan (%d)\n", ret);
mbox_free_channel(chan);
chan = ERR_PTR(ret);
}
}
ret = __mbox_bind_client(chan, cl);
if (ret)
chan = ERR_PTR(ret);
mutex_unlock(&con_mutex);
return chan;

25
drivers/mailbox/omap-mailbox.c
View File

@ -417,8 +417,6 @@ struct mbox_chan *omap_mbox_request_channel(struct mbox_client *cl,
struct device *dev = cl->dev;
struct omap_mbox *mbox = NULL;
struct omap_mbox_device *mdev;
struct mbox_chan *chan;
unsigned long flags;
int ret;
if (!dev)
@ -441,23 +439,11 @@ struct mbox_chan *omap_mbox_request_channel(struct mbox_client *cl,
if (!mbox || !mbox->chan)
return ERR_PTR(-ENOENT);
chan = mbox->chan;
spin_lock_irqsave(&chan->lock, flags);
chan->msg_free = 0;
chan->msg_count = 0;
chan->active_req = NULL;
chan->cl = cl;
init_completion(&chan->tx_complete);
spin_unlock_irqrestore(&chan->lock, flags);
ret = mbox_bind_client(mbox->chan, cl);
if (ret)
return ERR_PTR(ret);
ret = chan->mbox->ops->startup(chan);
if (ret) {
pr_err("Unable to startup the chan (%d)\n", ret);
mbox_free_channel(chan);
chan = ERR_PTR(ret);
}
return chan;
return mbox->chan;
}
EXPORT_SYMBOL(omap_mbox_request_channel);
@ -763,8 +749,7 @@ static int omap_mbox_probe(struct platform_device *pdev)
finfo->name = child->name;
if (of_find_property(child, "ti,mbox-send-noirq", NULL))
finfo->send_no_irq = true;
finfo->send_no_irq = of_property_read_bool(child, "ti,mbox-send-noirq");
if (finfo->tx_id >= num_fifos || finfo->rx_id >= num_fifos ||
finfo->tx_usr >= num_users || finfo->rx_usr >= num_users)

84
drivers/mailbox/pcc.c
View File

@ -282,8 +282,7 @@ pcc_mbox_request_channel(struct mbox_client *cl, int subspace_id)
{
struct pcc_chan_info *pchan;
struct mbox_chan *chan;
struct device *dev;
unsigned long flags;
int rc;
if (subspace_id < 0 || subspace_id >= pcc_chan_count)
return ERR_PTR(-ENOENT);
@ -294,32 +293,10 @@ pcc_mbox_request_channel(struct mbox_client *cl, int subspace_id)
pr_err("Channel not found for idx: %d\n", subspace_id);
return ERR_PTR(-EBUSY);
}
dev = chan->mbox->dev;
spin_lock_irqsave(&chan->lock, flags);
chan->msg_free = 0;
chan->msg_count = 0;
chan->active_req = NULL;
chan->cl = cl;
init_completion(&chan->tx_complete);
if (chan->txdone_method == TXDONE_BY_POLL && cl->knows_txdone)
chan->txdone_method = TXDONE_BY_ACK;
spin_unlock_irqrestore(&chan->lock, flags);
if (pchan->plat_irq > 0) {
int rc;
rc = devm_request_irq(dev, pchan->plat_irq, pcc_mbox_irq, 0,
MBOX_IRQ_NAME, chan);
if (unlikely(rc)) {
dev_err(dev, "failed to register PCC interrupt %d\n",
pchan->plat_irq);
pcc_mbox_free_channel(&pchan->chan);
return ERR_PTR(rc);
}
}
rc = mbox_bind_client(chan, cl);
if (rc)
return ERR_PTR(rc);
return &pchan->chan;
}
@ -333,23 +310,12 @@ EXPORT_SYMBOL_GPL(pcc_mbox_request_channel);
*/
void pcc_mbox_free_channel(struct pcc_mbox_chan *pchan)
{
struct pcc_chan_info *pchan_info = to_pcc_chan_info(pchan);
struct mbox_chan *chan = pchan->mchan;
unsigned long flags;
if (!chan || !chan->cl)
return;
if (pchan_info->plat_irq > 0)
devm_free_irq(chan->mbox->dev, pchan_info->plat_irq, chan);
spin_lock_irqsave(&chan->lock, flags);
chan->cl = NULL;
chan->active_req = NULL;
if (chan->txdone_method == TXDONE_BY_ACK)
chan->txdone_method = TXDONE_BY_POLL;
spin_unlock_irqrestore(&chan->lock, flags);
mbox_free_channel(chan);
}
EXPORT_SYMBOL_GPL(pcc_mbox_free_channel);
@ -377,8 +343,48 @@ static int pcc_send_data(struct mbox_chan *chan, void *data)
return pcc_chan_reg_read_modify_write(&pchan->db);
}
/**
* pcc_startup - Called from Mailbox Controller code. Used here
* to request the interrupt.
* @chan: Pointer to Mailbox channel to startup.
*
* Return: Err if something failed else 0 for success.
*/
static int pcc_startup(struct mbox_chan *chan)
{
struct pcc_chan_info *pchan = chan->con_priv;
int rc;
if (pchan->plat_irq > 0) {
rc = devm_request_irq(chan->mbox->dev, pchan->plat_irq, pcc_mbox_irq, 0,
MBOX_IRQ_NAME, chan);
if (unlikely(rc)) {
dev_err(chan->mbox->dev, "failed to register PCC interrupt %d\n",
pchan->plat_irq);
return rc;
}
}
return 0;
}
/**
* pcc_shutdown - Called from Mailbox Controller code. Used here
* to free the interrupt.
* @chan: Pointer to Mailbox channel to shutdown.
*/
static void pcc_shutdown(struct mbox_chan *chan)
{
struct pcc_chan_info *pchan = chan->con_priv;
if (pchan->plat_irq > 0)
devm_free_irq(chan->mbox->dev, pchan->plat_irq, chan);
}
static const struct mbox_chan_ops pcc_chan_ops = {
.send_data = pcc_send_data,
.startup = pcc_startup,
.shutdown = pcc_shutdown,
};
/**

11
drivers/mailbox/qcom-apcs-ipc-mailbox.c
View File

@ -141,9 +141,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)
/* .data is the offset of the ipc register within the global block */
static const struct of_device_id qcom_apcs_ipc_of_match[] = {
{ .compatible = "qcom,ipq5332-apcs-apps-global", .data = &ipq6018_apcs_data },
{ .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data },
{ .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq6018_apcs_data },
{ .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data },
{ .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data },
{ .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data },
@ -153,15 +151,18 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {
{ .compatible = "qcom,msm8998-apcs-hmss-global", .data = &msm8994_apcs_data },
{ .compatible = "qcom,qcm2290-apcs-hmss-global", .data = &msm8994_apcs_data },
{ .compatible = "qcom,qcs404-apcs-apps-global", .data = &msm8916_apcs_data },
{ .compatible = "qcom,sc7180-apss-shared", .data = &apps_shared_apcs_data },
{ .compatible = "qcom,sc8180x-apss-shared", .data = &apps_shared_apcs_data },
{ .compatible = "qcom,sdm660-apcs-hmss-global", .data = &msm8994_apcs_data },
{ .compatible = "qcom,sdm845-apss-shared", .data = &apps_shared_apcs_data },
{ .compatible = "qcom,sm4250-apcs-hmss-global", .data = &msm8994_apcs_data },
{ .compatible = "qcom,sm6125-apcs-hmss-global", .data = &msm8994_apcs_data },
{ .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data },
{ .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data },
{ .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data },
/* Do not add any more entries using existing driver data */
{ .compatible = "qcom,ipq5332-apcs-apps-global", .data = &ipq6018_apcs_data },
{ .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq6018_apcs_data },
{ .compatible = "qcom,sc7180-apss-shared", .data = &apps_shared_apcs_data },
{ .compatible = "qcom,sc8180x-apss-shared", .data = &apps_shared_apcs_data },
{ .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data },
{}
};
MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);

2
drivers/mailbox/rockchip-mailbox.c
View File

@ -248,7 +248,7 @@ static struct platform_driver rockchip_mbox_driver = {
.probe = rockchip_mbox_probe,
.driver = {
.name = "rockchip-mailbox",
.of_match_table = of_match_ptr(rockchip_mbox_of_match),
.of_match_table = rockchip_mbox_of_match,
},
};

123
include/dt-bindings/gce/mediatek,mt6795-gce.h Normal file
View File

@ -0,0 +1,123 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#ifndef _DT_BINDINGS_GCE_MT6795_H
#define _DT_BINDINGS_GCE_MT6795_H
/* GCE HW thread priority */
#define CMDQ_THR_PRIO_LOWEST 0
#define CMDQ_THR_PRIO_NORMAL 1
#define CMDQ_THR_PRIO_NORMAL_2 2
#define CMDQ_THR_PRIO_MEDIUM 3
#define CMDQ_THR_PRIO_MEDIUM_2 4
#define CMDQ_THR_PRIO_HIGH 5
#define CMDQ_THR_PRIO_HIGHER 6
#define CMDQ_THR_PRIO_HIGHEST 7
/* GCE SUBSYS */
#define SUBSYS_1300XXXX 0
#define SUBSYS_1400XXXX 1
#define SUBSYS_1401XXXX 2
#define SUBSYS_1402XXXX 3
#define SUBSYS_1500XXXX 4
#define SUBSYS_1600XXXX 5
#define SUBSYS_1700XXXX 6
#define SUBSYS_1800XXXX 7
#define SUBSYS_1000XXXX 8
#define SUBSYS_1001XXXX 9
#define SUBSYS_1002XXXX 10
#define SUBSYS_1003XXXX 11
#define SUBSYS_1004XXXX 12
#define SUBSYS_1005XXXX 13
#define SUBSYS_1020XXXX 14
#define SUBSYS_1021XXXX 15
#define SUBSYS_1120XXXX 16
#define SUBSYS_1121XXXX 17
#define SUBSYS_1122XXXX 18
#define SUBSYS_1123XXXX 19
#define SUBSYS_1124XXXX 20
#define SUBSYS_1125XXXX 21
#define SUBSYS_1126XXXX 22
/* GCE HW EVENT */
#define CMDQ_EVENT_MDP_RDMA0_SOF 0
#define CMDQ_EVENT_MDP_RDMA1_SOF 1
#define CMDQ_EVENT_MDP_DSI0_TE_SOF 2
#define CMDQ_EVENT_MDP_DSI1_TE_SOF 3
#define CMDQ_EVENT_MDP_MVW_SOF 4
#define CMDQ_EVENT_MDP_TDSHP0_SOF 5
#define CMDQ_EVENT_MDP_TDSHP1_SOF 6
#define CMDQ_EVENT_MDP_WDMA_SOF 7
#define CMDQ_EVENT_MDP_WROT0_SOF 8
#define CMDQ_EVENT_MDP_WROT1_SOF 9
#define CMDQ_EVENT_MDP_CROP_SOF 10
#define CMDQ_EVENT_DISP_OVL0_SOF 11
#define CMDQ_EVENT_DISP_OVL1_SOF 12
#define CMDQ_EVENT_DISP_RDMA0_SOF 13
#define CMDQ_EVENT_DISP_RDMA1_SOF 14
#define CMDQ_EVENT_DISP_RDMA2_SOF 15
#define CMDQ_EVENT_DISP_WDMA0_SOF 16
#define CMDQ_EVENT_DISP_WDMA1_SOF 17
#define CMDQ_EVENT_DISP_COLOR0_SOF 18
#define CMDQ_EVENT_DISP_COLOR1_SOF 19
#define CMDQ_EVENT_DISP_AAL_SOF 20
#define CMDQ_EVENT_DISP_GAMMA_SOF 21
#define CMDQ_EVENT_DISP_UFOE_SOF 22
#define CMDQ_EVENT_DISP_PWM0_SOF 23
#define CMDQ_EVENT_DISP_PWM1_SOF 24
#define CMDQ_EVENT_DISP_OD_SOF 25
#define CMDQ_EVENT_MDP_RDMA0_EOF 26
#define CMDQ_EVENT_MDP_RDMA1_EOF 27
#define CMDQ_EVENT_MDP_RSZ0_EOF 28
#define CMDQ_EVENT_MDP_RSZ1_EOF 29
#define CMDQ_EVENT_MDP_RSZ2_EOF 30
#define CMDQ_EVENT_MDP_TDSHP0_EOF 31
#define CMDQ_EVENT_MDP_TDSHP1_EOF 32
#define CMDQ_EVENT_MDP_WDMA_EOF 33
#define CMDQ_EVENT_MDP_WROT0_WRITE_EOF 34
#define CMDQ_EVENT_MDP_WROT0_READ_EOF 35
#define CMDQ_EVENT_MDP_WROT1_WRITE_EOF 36
#define CMDQ_EVENT_MDP_WROT1_READ_EOF 37
#define CMDQ_EVENT_MDP_CROP_EOF 38
#define CMDQ_EVENT_DISP_OVL0_EOF 39
#define CMDQ_EVENT_DISP_OVL1_EOF 40
#define CMDQ_EVENT_DISP_RDMA0_EOF 41
#define CMDQ_EVENT_DISP_RDMA1_EOF 42
#define CMDQ_EVENT_DISP_RDMA2_EOF 43
#define CMDQ_EVENT_DISP_WDMA0_EOF 44
#define CMDQ_EVENT_DISP_WDMA1_EOF 45
#define CMDQ_EVENT_DISP_COLOR0_EOF 46
#define CMDQ_EVENT_DISP_COLOR1_EOF 47
#define CMDQ_EVENT_DISP_AAL_EOF 48
#define CMDQ_EVENT_DISP_GAMMA_EOF 49
#define CMDQ_EVENT_DISP_UFOE_EOF 50
#define CMDQ_EVENT_DISP_DPI0_EOF 51
#define CMDQ_EVENT_MUTEX0_STREAM_EOF 52
#define CMDQ_EVENT_MUTEX1_STREAM_EOF 53
#define CMDQ_EVENT_MUTEX2_STREAM_EOF 54
#define CMDQ_EVENT_MUTEX3_STREAM_EOF 55
#define CMDQ_EVENT_MUTEX4_STREAM_EOF 56
#define CMDQ_EVENT_MUTEX5_STREAM_EOF 57
#define CMDQ_EVENT_MUTEX6_STREAM_EOF 58
#define CMDQ_EVENT_MUTEX7_STREAM_EOF 59
#define CMDQ_EVENT_MUTEX8_STREAM_EOF 60
#define CMDQ_EVENT_MUTEX9_STREAM_EOF 61
#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 62
#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 63
#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 64
#define CMDQ_EVENT_ISP_PASS2_2_EOF 129
#define CMDQ_EVENT_ISP_PASS2_1_EOF 130
#define CMDQ_EVENT_ISP_PASS2_0_EOF 131
#define CMDQ_EVENT_ISP_PASS1_1_EOF 132
#define CMDQ_EVENT_ISP_PASS1_0_EOF 133
#define CMDQ_EVENT_CAMSV_2_PASS1_EOF 134
#define CMDQ_EVENT_CAMSV_1_PASS1_EOF 135
#define CMDQ_EVENT_SENINF_CAM1_2_3_FIFO_FULL 136
#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 137
#define CMDQ_EVENT_JPGENC_PASS2_EOF 257
#define CMDQ_EVENT_JPGENC_PASS1_EOF 258
#define CMDQ_EVENT_JPGDEC_EOF 259
#endif

1
include/linux/mailbox_client.h
View File

@ -37,6 +37,7 @@ struct mbox_client {
void (*tx_done)(struct mbox_client *cl, void *mssg, int r);
};
int mbox_bind_client(struct mbox_chan *chan, struct mbox_client *cl);
struct mbox_chan *mbox_request_channel_byname(struct mbox_client *cl,
const char *name);
struct mbox_chan *mbox_request_channel(struct mbox_client *cl, int index);