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spi: tegra210-quad: combined sequence mode
Add combined sequence mode supported by Tegra QSPI controller. For commands which contain cmd, addr, data parts to it, controller can accept all 3 transfers at once and avoid interrupt for each transfer. This would improve read & write performance. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20220307165519.38380-3-kyarlagadda@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Krishna Yarlagadda
Mark Brown
parent
75a1b44a54
commit
1b8342cc4a
@ -121,14 +121,39 @@
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#define QSPI_NUM_DUMMY_CYCLE(x) (((x) & 0xff) << 0)
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#define QSPI_DUMMY_CYCLES_MAX 0xff
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#define QSPI_CMB_SEQ_CMD 0x19c
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#define QSPI_COMMAND_VALUE_SET(X) (((x) & 0xFF) << 0)
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#define QSPI_CMB_SEQ_CMD_CFG 0x1a0
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#define QSPI_COMMAND_X1_X2_X4(x) (((x) & 0x3) << 13)
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#define QSPI_COMMAND_X1_X2_X4_MASK (0x03 << 13)
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#define QSPI_COMMAND_SDR_DDR BIT(12)
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#define QSPI_COMMAND_SIZE_SET(x) (((x) & 0xFF) << 0)
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#define QSPI_GLOBAL_CONFIG 0X1a4
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#define QSPI_CMB_SEQ_EN BIT(0)
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#define QSPI_CMB_SEQ_ADDR 0x1a8
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#define QSPI_ADDRESS_VALUE_SET(X) (((x) & 0xFFFF) << 0)
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#define QSPI_CMB_SEQ_ADDR_CFG 0x1ac
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#define QSPI_ADDRESS_X1_X2_X4(x) (((x) & 0x3) << 13)
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#define QSPI_ADDRESS_X1_X2_X4_MASK (0x03 << 13)
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#define QSPI_ADDRESS_SDR_DDR BIT(12)
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#define QSPI_ADDRESS_SIZE_SET(x) (((x) & 0xFF) << 0)
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#define DATA_DIR_TX BIT(0)
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#define DATA_DIR_RX BIT(1)
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#define QSPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
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#define DEFAULT_QSPI_DMA_BUF_LEN (64 * 1024)
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#define CMD_TRANSFER 0
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#define ADDR_TRANSFER 1
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#define DATA_TRANSFER 2
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struct tegra_qspi_soc_data {
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bool has_dma;
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bool cmb_xfer_capable;
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};
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struct tegra_qspi_client_data {
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@ -912,7 +937,6 @@ static int tegra_qspi_setup(struct spi_device *spi)
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cdata = tegra_qspi_parse_cdata_dt(spi);
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spi->controller_data = cdata;
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}
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spin_lock_irqsave(&tqspi->lock, flags);
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/* keep default cs state to inactive */
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@ -971,19 +995,179 @@ static void tegra_qspi_transfer_end(struct spi_device *spi)
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tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1);
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}
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static int tegra_qspi_transfer_one_message(struct spi_master *master, struct spi_message *msg)
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static u32 tegra_qspi_cmd_config(bool is_ddr, u8 bus_width, u8 len)
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{
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u32 cmd_config = 0;
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/* Extract Command configuration and value */
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if (is_ddr)
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cmd_config |= QSPI_COMMAND_SDR_DDR;
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else
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cmd_config &= ~QSPI_COMMAND_SDR_DDR;
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cmd_config |= QSPI_COMMAND_X1_X2_X4(bus_width);
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cmd_config |= QSPI_COMMAND_SIZE_SET((len * 8) - 1);
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return cmd_config;
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}
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static u32 tegra_qspi_addr_config(bool is_ddr, u8 bus_width, u8 len)
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{
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u32 addr_config = 0;
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/* Extract Address configuration and value */
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is_ddr = 0; //Only SDR mode supported
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bus_width = 0; //X1 mode
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if (is_ddr)
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addr_config |= QSPI_ADDRESS_SDR_DDR;
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else
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addr_config &= ~QSPI_ADDRESS_SDR_DDR;
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addr_config |= QSPI_ADDRESS_X1_X2_X4(bus_width);
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addr_config |= QSPI_ADDRESS_SIZE_SET((len * 8) - 1);
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return addr_config;
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}
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static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
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struct spi_message *msg)
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{
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bool is_first_msg = true;
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struct spi_transfer *xfer;
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struct spi_device *spi = msg->spi;
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u8 transfer_phase = 0;
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u32 cmd1 = 0, dma_ctl = 0;
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int ret = 0;
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u32 address_value = 0;
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u32 cmd_config = 0, addr_config = 0;
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u8 cmd_value = 0, val = 0;
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/* Enable Combined sequence mode */
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val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
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val |= QSPI_CMB_SEQ_EN;
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tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
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/* Process individual transfer list */
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list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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switch (transfer_phase) {
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case CMD_TRANSFER:
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/* X1 SDR mode */
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cmd_config = tegra_qspi_cmd_config(false, 0,
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xfer->len);
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cmd_value = *((const u8 *)(xfer->tx_buf));
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break;
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case ADDR_TRANSFER:
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/* X1 SDR mode */
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addr_config = tegra_qspi_addr_config(false, 0,
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xfer->len);
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address_value = *((const u32 *)(xfer->tx_buf));
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break;
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case DATA_TRANSFER:
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/* Program Command, Address value in register */
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tegra_qspi_writel(tqspi, cmd_value, QSPI_CMB_SEQ_CMD);
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tegra_qspi_writel(tqspi, address_value,
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QSPI_CMB_SEQ_ADDR);
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/* Program Command and Address config in register */
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tegra_qspi_writel(tqspi, cmd_config,
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QSPI_CMB_SEQ_CMD_CFG);
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tegra_qspi_writel(tqspi, addr_config,
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QSPI_CMB_SEQ_ADDR_CFG);
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reinit_completion(&tqspi->xfer_completion);
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cmd1 = tegra_qspi_setup_transfer_one(spi, xfer,
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is_first_msg);
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ret = tegra_qspi_start_transfer_one(spi, xfer,
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cmd1);
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if (ret < 0) {
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dev_err(tqspi->dev, "Failed to start transfer-one: %d\n",
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ret);
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return ret;
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}
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is_first_msg = false;
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ret = wait_for_completion_timeout
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(&tqspi->xfer_completion,
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QSPI_DMA_TIMEOUT);
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if (WARN_ON(ret == 0)) {
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dev_err(tqspi->dev, "QSPI Transfer failed with timeout: %d\n",
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ret);
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if (tqspi->is_curr_dma_xfer &&
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(tqspi->cur_direction & DATA_DIR_TX))
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dmaengine_terminate_all
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(tqspi->tx_dma_chan);
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if (tqspi->is_curr_dma_xfer &&
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(tqspi->cur_direction & DATA_DIR_RX))
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dmaengine_terminate_all
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(tqspi->rx_dma_chan);
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/* Abort transfer by resetting pio/dma bit */
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if (!tqspi->is_curr_dma_xfer) {
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cmd1 = tegra_qspi_readl
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(tqspi,
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QSPI_COMMAND1);
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cmd1 &= ~QSPI_PIO;
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tegra_qspi_writel
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(tqspi, cmd1,
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QSPI_COMMAND1);
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} else {
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dma_ctl = tegra_qspi_readl
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(tqspi,
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QSPI_DMA_CTL);
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dma_ctl &= ~QSPI_DMA_EN;
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tegra_qspi_writel(tqspi, dma_ctl,
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QSPI_DMA_CTL);
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}
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/* Reset controller if timeout happens */
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if (device_reset(tqspi->dev) < 0)
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dev_warn_once(tqspi->dev,
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"device reset failed\n");
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ret = -EIO;
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goto exit;
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}
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if (tqspi->tx_status || tqspi->rx_status) {
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dev_err(tqspi->dev, "QSPI Transfer failed\n");
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tqspi->tx_status = 0;
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tqspi->rx_status = 0;
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ret = -EIO;
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goto exit;
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}
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break;
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default:
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ret = -EINVAL;
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goto exit;
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}
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msg->actual_length += xfer->len;
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transfer_phase++;
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}
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exit:
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msg->status = ret;
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return ret;
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}
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static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi,
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struct spi_message *msg)
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{
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struct tegra_qspi *tqspi = spi_master_get_devdata(master);
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struct spi_device *spi = msg->spi;
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struct spi_transfer *transfer;
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bool is_first_msg = true;
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int ret;
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int ret = 0, val = 0;
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msg->status = 0;
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msg->actual_length = 0;
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tqspi->tx_status = 0;
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tqspi->rx_status = 0;
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/* Disable Combined sequence mode */
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val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
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val &= ~QSPI_CMB_SEQ_EN;
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tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
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list_for_each_entry(transfer, &msg->transfers, transfer_list) {
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struct spi_transfer *xfer = transfer;
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u8 dummy_bytes = 0;
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@ -1021,7 +1205,6 @@ static int tegra_qspi_transfer_one_message(struct spi_master *master, struct spi
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goto complete_xfer;
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}
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is_first_msg = false;
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ret = wait_for_completion_timeout(&tqspi->xfer_completion,
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QSPI_DMA_TIMEOUT);
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if (WARN_ON(ret == 0)) {
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@ -1066,7 +1249,48 @@ complete_xfer:
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ret = 0;
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exit:
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msg->status = ret;
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return ret;
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}
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static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi,
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struct spi_message *msg)
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{
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int transfer_count = 0;
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struct spi_transfer *xfer;
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list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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transfer_count++;
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}
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if (!tqspi->soc_data->cmb_xfer_capable || transfer_count != 3)
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return false;
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xfer = list_first_entry(&msg->transfers, typeof(*xfer),
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transfer_list);
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if (xfer->len > 2)
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return false;
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xfer = list_next_entry(xfer, transfer_list);
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if (xfer->len > 4 || xfer->len < 3)
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return false;
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xfer = list_next_entry(xfer, transfer_list);
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if (!tqspi->soc_data->has_dma || xfer->len > (QSPI_FIFO_DEPTH << 2))
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return false;
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return true;
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}
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static int tegra_qspi_transfer_one_message(struct spi_master *master,
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struct spi_message *msg)
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{
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struct tegra_qspi *tqspi = spi_master_get_devdata(master);
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int ret;
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if (tegra_qspi_validate_cmb_seq(tqspi, msg))
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ret = tegra_qspi_combined_seq_xfer(tqspi, msg);
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else
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ret = tegra_qspi_non_combined_seq_xfer(tqspi, msg);
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spi_finalize_current_message(master);
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return ret;
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}
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@ -1200,14 +1424,17 @@ static irqreturn_t tegra_qspi_isr_thread(int irq, void *context_data)
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static struct tegra_qspi_soc_data tegra210_qspi_soc_data = {
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.has_dma = true,
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.cmb_xfer_capable = false,
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};
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static struct tegra_qspi_soc_data tegra186_qspi_soc_data = {
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.has_dma = true,
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.cmb_xfer_capable = true,
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};
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static struct tegra_qspi_soc_data tegra234_qspi_soc_data = {
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.has_dma = false,
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.cmb_xfer_capable = true,
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};
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static const struct of_device_id tegra_qspi_of_match[] = {
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@ -1278,6 +1505,7 @@ static int tegra_qspi_probe(struct platform_device *pdev)
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tqspi->dev = &pdev->dev;
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spin_lock_init(&tqspi->lock);
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tqspi->soc_data = device_get_match_data(&pdev->dev);
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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tqspi->base = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(tqspi->base))
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