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gpio: Add GPIO support for the ACCES 104-DIO-48E
The ACCES 104-DIO-48E device provides 48 lines digital I/O via two Programmable Peripheral Interface (PPI) chips of type 82C55. Bit C3 at each 24-bit Group can be used as an external interrupt, triggered by a rising edge. This driver provides GPIO and IRQ support for these 48 channels of digital I/O. The base port address for the device may be configured via the dio_48e_base module parameter. The interrupt line number for the device may be configured via the dio_48e_irq module parameter. Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
William Breathitt Gray
Linus Walleij
parent
9c26df9b27
commit
1b06d64f73
@ -240,6 +240,12 @@ L: lm-sensors@lm-sensors.org
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S: Maintained
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F: drivers/hwmon/abituguru3.c
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ACCES 104-DIO-48E GPIO DRIVER
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M: William Breathitt Gray <vilhelm.gray@gmail.com>
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L: linux-gpio@vger.kernel.org
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S: Maintained
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F: drivers/gpio/gpio-104-dio-48e.c
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ACCES 104-IDI-48 GPIO DRIVER
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M: "William Breathitt Gray" <vilhelm.gray@gmail.com>
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L: linux-gpio@vger.kernel.org
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@ -487,6 +487,15 @@ endmenu
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menu "Port-mapped I/O GPIO drivers"
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depends on X86 # Unconditional I/O space access
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config GPIO_104_DIO_48E
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tristate "ACCES 104-DIO-48E GPIO support"
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select GPIOLIB_IRQCHIP
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help
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Enables GPIO support for the ACCES 104-DIO-48E family. The base port
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address for the device may be configured via the dio_48e_base module
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parameter. The interrupt line number for the device may be configured
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via the dio_48e_irq module parameter.
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config GPIO_104_IDIO_16
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tristate "ACCES 104-IDIO-16 GPIO support"
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select GPIOLIB_IRQCHIP
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@ -12,6 +12,7 @@ obj-$(CONFIG_GPIO_ACPI) += gpiolib-acpi.o
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# Device drivers. Generally keep list sorted alphabetically
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obj-$(CONFIG_GPIO_GENERIC) += gpio-generic.o
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obj-$(CONFIG_GPIO_104_DIO_48E) += gpio-104-dio-48e.o
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obj-$(CONFIG_GPIO_104_IDIO_16) += gpio-104-idio-16.o
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obj-$(CONFIG_GPIO_104_IDI_48) += gpio-104-idi-48.o
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obj-$(CONFIG_GPIO_74X164) += gpio-74x164.o
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439
drivers/gpio/gpio-104-dio-48e.c
Normal file
439
drivers/gpio/gpio-104-dio-48e.c
Normal file
@ -0,0 +1,439 @@
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/*
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* GPIO driver for the ACCES 104-DIO-48E
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* Copyright (C) 2016 William Breathitt Gray
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/irqdesc.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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static unsigned dio_48e_base;
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module_param(dio_48e_base, uint, 0);
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MODULE_PARM_DESC(dio_48e_base, "ACCES 104-DIO-48E base address");
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static unsigned dio_48e_irq;
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module_param(dio_48e_irq, uint, 0);
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MODULE_PARM_DESC(dio_48e_irq, "ACCES 104-DIO-48E interrupt line number");
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/**
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* struct dio48e_gpio - GPIO device private data structure
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* @chip: instance of the gpio_chip
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* @io_state: bit I/O state (whether bit is set to input or output)
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* @out_state: output bits state
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* @control: Control registers state
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* @lock: synchronization lock to prevent I/O race conditions
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* @base: base port address of the GPIO device
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* @extent: extent of port address region of the GPIO device
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* @irq: Interrupt line number
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* @irq_mask: I/O bits affected by interrupts
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*/
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struct dio48e_gpio {
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struct gpio_chip chip;
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unsigned char io_state[6];
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unsigned char out_state[6];
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unsigned char control[2];
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spinlock_t lock;
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unsigned base;
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unsigned extent;
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unsigned irq;
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unsigned char irq_mask;
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};
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static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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return !!(dio48egpio->io_state[port] & mask);
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}
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static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned io_port = offset / 8;
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const unsigned control_port = io_port / 2;
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const unsigned control_addr = dio48egpio->base + 3 + control_port*4;
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unsigned long flags;
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unsigned control;
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spin_lock_irqsave(&dio48egpio->lock, flags);
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/* Check if configuring Port C */
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if (io_port == 2 || io_port == 5) {
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/* Port C can be configured by nibble */
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if (offset % 8 > 3) {
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dio48egpio->io_state[io_port] |= 0xF0;
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dio48egpio->control[control_port] |= BIT(3);
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} else {
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dio48egpio->io_state[io_port] |= 0x0F;
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dio48egpio->control[control_port] |= BIT(0);
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}
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} else {
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dio48egpio->io_state[io_port] |= 0xFF;
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if (io_port == 0 || io_port == 3)
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dio48egpio->control[control_port] |= BIT(4);
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else
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dio48egpio->control[control_port] |= BIT(1);
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}
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control = BIT(7) | dio48egpio->control[control_port];
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outb(control, control_addr);
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control &= ~BIT(7);
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outb(control, control_addr);
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spin_unlock_irqrestore(&dio48egpio->lock, flags);
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return 0;
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}
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static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned io_port = offset / 8;
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const unsigned control_port = io_port / 2;
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const unsigned mask = BIT(offset % 8);
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const unsigned control_addr = dio48egpio->base + 3 + control_port*4;
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const unsigned out_port = (io_port > 2) ? io_port + 1 : io_port;
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unsigned long flags;
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unsigned control;
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spin_lock_irqsave(&dio48egpio->lock, flags);
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/* Check if configuring Port C */
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if (io_port == 2 || io_port == 5) {
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/* Port C can be configured by nibble */
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if (offset % 8 > 3) {
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dio48egpio->io_state[io_port] &= 0x0F;
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dio48egpio->control[control_port] &= ~BIT(3);
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} else {
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dio48egpio->io_state[io_port] &= 0xF0;
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dio48egpio->control[control_port] &= ~BIT(0);
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}
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} else {
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dio48egpio->io_state[io_port] &= 0x00;
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if (io_port == 0 || io_port == 3)
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dio48egpio->control[control_port] &= ~BIT(4);
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else
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dio48egpio->control[control_port] &= ~BIT(1);
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}
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if (value)
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dio48egpio->out_state[io_port] |= mask;
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else
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dio48egpio->out_state[io_port] &= ~mask;
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control = BIT(7) | dio48egpio->control[control_port];
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outb(control, control_addr);
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outb(dio48egpio->out_state[io_port], dio48egpio->base + out_port);
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control &= ~BIT(7);
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outb(control, control_addr);
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spin_unlock_irqrestore(&dio48egpio->lock, flags);
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return 0;
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}
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static int dio48e_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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const unsigned in_port = (port > 2) ? port + 1 : port;
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unsigned long flags;
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unsigned port_state;
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spin_lock_irqsave(&dio48egpio->lock, flags);
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/* ensure that GPIO is set for input */
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if (!(dio48egpio->io_state[port] & mask)) {
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spin_unlock_irqrestore(&dio48egpio->lock, flags);
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return -EINVAL;
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}
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port_state = inb(dio48egpio->base + in_port);
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spin_unlock_irqrestore(&dio48egpio->lock, flags);
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return !!(port_state & mask);
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}
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static void dio48e_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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const unsigned out_port = (port > 2) ? port + 1 : port;
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unsigned long flags;
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spin_lock_irqsave(&dio48egpio->lock, flags);
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if (value)
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dio48egpio->out_state[port] |= mask;
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else
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dio48egpio->out_state[port] &= ~mask;
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outb(dio48egpio->out_state[port], dio48egpio->base + out_port);
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spin_unlock_irqrestore(&dio48egpio->lock, flags);
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}
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static void dio48e_irq_ack(struct irq_data *data)
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{
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}
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static void dio48e_irq_mask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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unsigned long flags;
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/* only bit 3 on each respective Port C supports interrupts */
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if (offset != 19 && offset != 43)
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return;
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spin_lock_irqsave(&dio48egpio->lock, flags);
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if (offset == 19)
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dio48egpio->irq_mask &= ~BIT(0);
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else
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dio48egpio->irq_mask &= ~BIT(1);
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if (!dio48egpio->irq_mask)
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/* disable interrupts */
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inb(dio48egpio->base + 0xB);
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spin_unlock_irqrestore(&dio48egpio->lock, flags);
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}
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static void dio48e_irq_unmask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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unsigned long flags;
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/* only bit 3 on each respective Port C supports interrupts */
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if (offset != 19 && offset != 43)
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return;
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spin_lock_irqsave(&dio48egpio->lock, flags);
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if (!dio48egpio->irq_mask) {
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/* enable interrupts */
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outb(0x00, dio48egpio->base + 0xF);
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outb(0x00, dio48egpio->base + 0xB);
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}
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if (offset == 19)
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dio48egpio->irq_mask |= BIT(0);
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else
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dio48egpio->irq_mask |= BIT(1);
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spin_unlock_irqrestore(&dio48egpio->lock, flags);
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}
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static int dio48e_irq_set_type(struct irq_data *data, unsigned flow_type)
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{
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const unsigned long offset = irqd_to_hwirq(data);
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/* only bit 3 on each respective Port C supports interrupts */
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if (offset != 19 && offset != 43)
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return -EINVAL;
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if (flow_type != IRQ_TYPE_NONE && flow_type != IRQ_TYPE_EDGE_RISING)
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return -EINVAL;
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return 0;
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}
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static struct irq_chip dio48e_irqchip = {
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.name = "104-dio-48e",
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.irq_ack = dio48e_irq_ack,
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.irq_mask = dio48e_irq_mask,
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.irq_unmask = dio48e_irq_unmask,
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.irq_set_type = dio48e_irq_set_type
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};
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static irqreturn_t dio48e_irq_handler(int irq, void *dev_id)
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{
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struct dio48e_gpio *const dio48egpio = dev_id;
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struct gpio_chip *const chip = &dio48egpio->chip;
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const unsigned long irq_mask = dio48egpio->irq_mask;
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unsigned long gpio;
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for_each_set_bit(gpio, &irq_mask, 2)
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generic_handle_irq(irq_find_mapping(chip->irqdomain,
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19 + gpio*24));
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spin_lock(&dio48egpio->lock);
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outb(0x00, dio48egpio->base + 0xF);
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spin_unlock(&dio48egpio->lock);
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return IRQ_HANDLED;
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}
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static int __init dio48e_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct dio48e_gpio *dio48egpio;
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const unsigned base = dio_48e_base;
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const unsigned extent = 16;
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const char *const name = dev_name(dev);
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int err;
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const unsigned irq = dio_48e_irq;
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dio48egpio = devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL);
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if (!dio48egpio)
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return -ENOMEM;
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if (!request_region(base, extent, name)) {
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dev_err(dev, "Unable to lock %s port addresses (0x%X-0x%X)\n",
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name, base, base + extent);
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err = -EBUSY;
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goto err_lock_io_port;
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}
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dio48egpio->chip.label = name;
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dio48egpio->chip.parent = dev;
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dio48egpio->chip.owner = THIS_MODULE;
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dio48egpio->chip.base = -1;
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dio48egpio->chip.ngpio = 48;
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dio48egpio->chip.get_direction = dio48e_gpio_get_direction;
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dio48egpio->chip.direction_input = dio48e_gpio_direction_input;
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dio48egpio->chip.direction_output = dio48e_gpio_direction_output;
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dio48egpio->chip.get = dio48e_gpio_get;
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dio48egpio->chip.set = dio48e_gpio_set;
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dio48egpio->base = base;
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dio48egpio->extent = extent;
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dio48egpio->irq = irq;
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spin_lock_init(&dio48egpio->lock);
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dev_set_drvdata(dev, dio48egpio);
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err = gpiochip_add_data(&dio48egpio->chip, dio48egpio);
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if (err) {
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dev_err(dev, "GPIO registering failed (%d)\n", err);
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goto err_gpio_register;
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}
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/* initialize all GPIO as output */
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outb(0x80, base + 3);
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outb(0x00, base);
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outb(0x00, base + 1);
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outb(0x00, base + 2);
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outb(0x00, base + 3);
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outb(0x80, base + 7);
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outb(0x00, base + 4);
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outb(0x00, base + 5);
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outb(0x00, base + 6);
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outb(0x00, base + 7);
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/* disable IRQ by default */
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inb(base + 0xB);
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err = gpiochip_irqchip_add(&dio48egpio->chip, &dio48e_irqchip, 0,
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handle_edge_irq, IRQ_TYPE_NONE);
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if (err) {
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dev_err(dev, "Could not add irqchip (%d)\n", err);
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goto err_gpiochip_irqchip_add;
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}
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err = request_irq(irq, dio48e_irq_handler, 0, name, dio48egpio);
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if (err) {
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dev_err(dev, "IRQ handler registering failed (%d)\n", err);
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goto err_request_irq;
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}
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return 0;
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err_request_irq:
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err_gpiochip_irqchip_add:
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gpiochip_remove(&dio48egpio->chip);
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err_gpio_register:
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release_region(base, extent);
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err_lock_io_port:
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return err;
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}
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static int dio48e_remove(struct platform_device *pdev)
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{
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struct dio48e_gpio *const dio48egpio = platform_get_drvdata(pdev);
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free_irq(dio48egpio->irq, dio48egpio);
|
||||
gpiochip_remove(&dio48egpio->chip);
|
||||
release_region(dio48egpio->base, dio48egpio->extent);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_device *dio48e_device;
|
||||
|
||||
static struct platform_driver dio48e_driver = {
|
||||
.driver = {
|
||||
.name = "104-dio-48e"
|
||||
},
|
||||
.remove = dio48e_remove
|
||||
};
|
||||
|
||||
static void __exit dio48e_exit(void)
|
||||
{
|
||||
platform_device_unregister(dio48e_device);
|
||||
platform_driver_unregister(&dio48e_driver);
|
||||
}
|
||||
|
||||
static int __init dio48e_init(void)
|
||||
{
|
||||
int err;
|
||||
|
||||
dio48e_device = platform_device_alloc(dio48e_driver.driver.name, -1);
|
||||
if (!dio48e_device)
|
||||
return -ENOMEM;
|
||||
|
||||
err = platform_device_add(dio48e_device);
|
||||
if (err)
|
||||
goto err_platform_device;
|
||||
|
||||
err = platform_driver_probe(&dio48e_driver, dio48e_probe);
|
||||
if (err)
|
||||
goto err_platform_driver;
|
||||
|
||||
return 0;
|
||||
|
||||
err_platform_driver:
|
||||
platform_device_del(dio48e_device);
|
||||
err_platform_device:
|
||||
platform_device_put(dio48e_device);
|
||||
return err;
|
||||
}
|
||||
|
||||
module_init(dio48e_init);
|
||||
module_exit(dio48e_exit);
|
||||
|
||||
MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
|
||||
MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user