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ARM: qcom: Re-organize platsmp to make it extensible
This makes it easy to add SMP support for new devices by keying on a device node for the release sequence. We add the enable-method property for the cpus property to specify that we want to use the gcc-msm8660 release sequence (which is going to look for the global clock controller device node to map some Scorpion specific power and control registers). We also remove the nr_cpus detection code as that is done generically in the DT CPU detection code. Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org> [sboyd: Port to CPU_METHOD_OF_DECLARE] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
This commit is contained in:
Rohit Vaswani
Kumar Gala
parent
6c3ff8b11a
commit
188611af42
@ -23,8 +23,6 @@ extern void msm_map_qsd8x50_io(void);
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extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
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unsigned int mtype, void *caller);
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extern struct smp_operations msm_smp_ops;
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struct msm_mmc_platform_data;
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extern void msm_add_devices(void);
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@ -11,30 +11,16 @@
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*/
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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extern struct smp_operations qcom_smp_ops;
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static const char * const qcom_dt_match[] __initconst = {
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"qcom,msm8660-surf",
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"qcom,msm8960-cdp",
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NULL
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};
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static const char * const apq8074_dt_match[] __initconst = {
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"qcom,apq8074-dragonboard",
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NULL
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};
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DT_MACHINE_START(QCOM_DT, "Qualcomm (Flattened Device Tree)")
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.smp = smp_ops(qcom_smp_ops),
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.dt_compat = qcom_dt_match,
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MACHINE_END
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DT_MACHINE_START(APQ_DT, "Qualcomm (Flattened Device Tree)")
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.dt_compat = apq8074_dt_match,
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MACHINE_END
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@ -13,17 +13,18 @@
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/cputype.h>
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#include <asm/smp_plat.h>
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#include "scm-boot.h"
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#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
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#define SCSS_CPU1CORE_RESET 0xD80
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#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
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#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x35a0
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#define SCSS_CPU1CORE_RESET 0x2d80
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#define SCSS_DBG_STATUS_CORE_PWRDUP 0x2e64
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extern void secondary_startup(void);
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@ -36,12 +37,6 @@ static void __ref qcom_cpu_die(unsigned int cpu)
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}
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#endif
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static inline int get_core_count(void)
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{
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/* 1 + the PART[1:0] field of MIDR */
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return ((read_cpuid_id() >> 4) & 3) + 1;
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}
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static void qcom_secondary_init(unsigned int cpu)
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{
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/*
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@ -51,33 +46,41 @@ static void qcom_secondary_init(unsigned int cpu)
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spin_unlock(&boot_lock);
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}
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static void prepare_cold_cpu(unsigned int cpu)
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static int scss_release_secondary(unsigned int cpu)
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{
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int ret;
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ret = scm_set_boot_addr(virt_to_phys(secondary_startup),
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SCM_FLAG_COLDBOOT_CPU1);
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if (ret == 0) {
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void __iomem *sc1_base_ptr;
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sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
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if (sc1_base_ptr) {
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writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
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writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET);
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writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP);
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iounmap(sc1_base_ptr);
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}
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} else
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printk(KERN_DEBUG "Failed to set secondary core boot "
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"address\n");
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struct device_node *node;
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void __iomem *base;
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node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660");
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if (!node) {
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pr_err("%s: can't find node\n", __func__);
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return -ENXIO;
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}
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base = of_iomap(node, 0);
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of_node_put(node);
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if (!base)
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return -ENOMEM;
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writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
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writel_relaxed(0, base + SCSS_CPU1CORE_RESET);
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writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP);
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mb();
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iounmap(base);
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return 0;
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}
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static int qcom_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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static int cold_boot_done;
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static DEFINE_PER_CPU(int, cold_boot_done);
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/* Only need to bring cpu out of reset this way once */
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if (cold_boot_done == false) {
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prepare_cold_cpu(cpu);
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cold_boot_done = true;
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static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
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{
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int ret = 0;
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if (!per_cpu(cold_boot_done, cpu)) {
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ret = func(cpu);
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if (!ret)
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per_cpu(cold_boot_done, cpu) = true;
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}
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/*
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@ -99,39 +102,48 @@ static int qcom_boot_secondary(unsigned int cpu, struct task_struct *idle)
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*/
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spin_unlock(&boot_lock);
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return 0;
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return ret;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system. The msm8x60
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* does not support the ARM SCU, so just set the possible cpu mask to
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* NR_CPUS.
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*/
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static void __init qcom_smp_init_cpus(void)
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static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned int i, ncores = get_core_count();
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if (ncores > nr_cpu_ids) {
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pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
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ncores, nr_cpu_ids);
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ncores = nr_cpu_ids;
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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return qcom_boot_secondary(cpu, scss_release_secondary);
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}
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static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
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{
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int cpu, map;
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unsigned int flags = 0;
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static const int cold_boot_flags[] = {
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0,
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SCM_FLAG_COLDBOOT_CPU1,
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};
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for_each_present_cpu(cpu) {
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map = cpu_logical_map(cpu);
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if (WARN_ON(map >= ARRAY_SIZE(cold_boot_flags))) {
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set_cpu_present(cpu, false);
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continue;
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}
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flags |= cold_boot_flags[map];
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}
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if (scm_set_boot_addr(virt_to_phys(secondary_startup), flags)) {
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for_each_present_cpu(cpu) {
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if (cpu == smp_processor_id())
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continue;
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set_cpu_present(cpu, false);
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}
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pr_warn("Failed to set CPU boot address, disabling SMP\n");
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}
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}
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struct smp_operations qcom_smp_ops __initdata = {
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.smp_init_cpus = qcom_smp_init_cpus,
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static struct smp_operations smp_msm8660_ops __initdata = {
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.smp_prepare_cpus = qcom_smp_prepare_cpus,
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.smp_secondary_init = qcom_secondary_init,
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.smp_boot_secondary = qcom_boot_secondary,
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.smp_boot_secondary = msm8660_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = qcom_cpu_die,
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#endif
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};
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CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
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