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ARM: SoC fixes for 6.4

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There have not been a lot of fixes for for the soc tree in 6.4, but
 these have been sitting here for too long.
 
 For the devicetree side, there is one minor warning fix for vexpress,
 the rest all all for the the NXP i.MX platforms: SoC specific bugfixes
 for the iMX8 clocks and its USB-3.0 gadget device, as well as board
 specific fixes for regulators and the phy on some of the i.MX boards.
 
 The microchip risc-v and arm32 maintainers now also add a shared
 maintainer file entry for the arm64 parts.
 
 The remaining fixes are all for firmware drivers, addressing mistakes in
 the optee, scmi and ff-a firmware driver implementation, mostly in the
 error handling code, incorrect use of the alloc_workqueue() interface in
 SCMI, and compatibility with corner cases of the firmware implementation.
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Merge tag 'arm-fixes-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
 "There have not been a lot of fixes for for the soc tree in 6.4, but
  these have been sitting here for too long.

  For the devicetree side, there is one minor warning fix for vexpress,
  the rest all all for the the NXP i.MX platforms: SoC specific bugfixes
  for the iMX8 clocks and its USB-3.0 gadget device, as well as board
  specific fixes for regulators and the phy on some of the i.MX boards.

  The microchip risc-v and arm32 maintainers now also add a shared
  maintainer file entry for the arm64 parts.

  The remaining fixes are all for firmware drivers, addressing mistakes
  in the optee, scmi and ff-a firmware driver implementation, mostly in
  the error handling code, incorrect use of the alloc_workqueue()
  interface in SCMI, and compatibility with corner cases of the firmware
  implementation"

* tag 'arm-fixes-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  MAINTAINERS: update arm64 Microchip entries
  arm64: dts: imx8: fix USB 3.0 Gadget Failure in QM & QXPB0 at super speed
  dt-binding: cdns,usb3: Fix cdns,on-chip-buff-size type
  arm64: dts: colibri-imx8x: delete adc1 and dsp
  arm64: dts: colibri-imx8x: fix iris pinctrl configuration
  arm64: dts: colibri-imx8x: move pinctrl property from SoM to eval board
  arm64: dts: colibri-imx8x: fix eval board pin configuration
  arm64: dts: imx8mp: Fix video clock parents
  ARM: dts: imx6qdl-mba6: Add missing pvcie-supply regulator
  ARM: dts: imx6ull-dhcor: Set and limit the mode for PMIC buck 1, 2 and 3
  arm64: dts: imx8mn-var-som: fix PHY detection bug by adding deassert delay
  arm64: dts: imx8mn: Fix video clock parents
  firmware: arm_ffa: Set reserved/MBZ fields to zero in the memory descriptors
  firmware: arm_ffa: Fix FFA device names for logical partitions
  firmware: arm_ffa: Fix usage of partition info get count flag
  firmware: arm_ffa: Check if ffa_driver remove is present before executing
  arm64: dts: arm: add missing cache properties
  ARM: dts: vexpress: add missing cache properties
  firmware: arm_scmi: Fix incorrect alloc_workqueue() invocation
  optee: fix uninited async notif value
This commit is contained in:
Linus Torvalds 2023-05-26 16:17:56 -07:00
commit 18713e8a68
20 changed files with 99 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/usb/cdns,usb3.yaml
View File

@ -64,7 +64,7 @@ properties:
description: description:
size of memory intended as internal memory for endpoints size of memory intended as internal memory for endpoints
buffers expressed in KB buffers expressed in KB
$ref: /schemas/types.yaml#/definitions/uint32 $ref: /schemas/types.yaml#/definitions/uint16
cdns,phyrst-a-enable: cdns,phyrst-a-enable:
description: Enable resetting of PHY if Rx fail is detected description: Enable resetting of PHY if Rx fail is detected

12
MAINTAINERS
View File

@ -2429,6 +2429,15 @@ X: drivers/net/wireless/atmel/
N: at91 N: at91
N: atmel N: atmel
ARM/MICROCHIP (ARM64) SoC support
M: Conor Dooley <conor@kernel.org>
M: Nicolas Ferre <nicolas.ferre@microchip.com>
M: Claudiu Beznea <claudiu.beznea@microchip.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported
T: git https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git
F: arch/arm64/boot/dts/microchip/
ARM/Microchip Sparx5 SoC support ARM/Microchip Sparx5 SoC support
M: Lars Povlsen <lars.povlsen@microchip.com> M: Lars Povlsen <lars.povlsen@microchip.com>
M: Steen Hegelund <Steen.Hegelund@microchip.com> M: Steen Hegelund <Steen.Hegelund@microchip.com>
@ -2436,8 +2445,7 @@ M: Daniel Machon <daniel.machon@microchip.com>
M: UNGLinuxDriver@microchip.com M: UNGLinuxDriver@microchip.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported S: Supported
T: git git://github.com/microchip-ung/linux-upstream.git F: arch/arm64/boot/dts/microchip/sparx*
F: arch/arm64/boot/dts/microchip/
F: drivers/net/ethernet/microchip/vcap/ F: drivers/net/ethernet/microchip/vcap/
F: drivers/pinctrl/pinctrl-microchip-sgpio.c F: drivers/pinctrl/pinctrl-microchip-sgpio.c
N: sparx5 N: sparx5

1
arch/arm/boot/dts/imx6qdl-mba6.dtsi
View File

@ -209,6 +209,7 @@
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>; pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>; reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcie>;
status = "okay"; status = "okay";
}; };

7
arch/arm/boot/dts/imx6ull-dhcor-som.dtsi
View File

@ -8,6 +8,7 @@
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h> #include <dt-bindings/leds/common.h>
#include <dt-bindings/pwm/pwm.h> #include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/regulator/dlg,da9063-regulator.h>
#include "imx6ull.dtsi" #include "imx6ull.dtsi"
/ { / {
@ -84,16 +85,20 @@
regulators { regulators {
vdd_soc_in_1v4: buck1 { vdd_soc_in_1v4: buck1 {
regulator-allowed-modes = <DA9063_BUCK_MODE_SLEEP>; /* PFM */
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-initial-mode = <DA9063_BUCK_MODE_SLEEP>;
regulator-max-microvolt = <1400000>; regulator-max-microvolt = <1400000>;
regulator-min-microvolt = <1400000>; regulator-min-microvolt = <1400000>;
regulator-name = "vdd_soc_in_1v4"; regulator-name = "vdd_soc_in_1v4";
}; };
vcc_3v3: buck2 { vcc_3v3: buck2 {
regulator-allowed-modes = <DA9063_BUCK_MODE_SYNC>; /* PWM */
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-name = "vcc_3v3"; regulator-name = "vcc_3v3";
@ -106,8 +111,10 @@
* the voltage is set to 1.5V. * the voltage is set to 1.5V.
*/ */
vcc_ddr_1v35: buck3 { vcc_ddr_1v35: buck3 {
regulator-allowed-modes = <DA9063_BUCK_MODE_SYNC>; /* PWM */
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
regulator-max-microvolt = <1500000>; regulator-max-microvolt = <1500000>;
regulator-min-microvolt = <1500000>; regulator-min-microvolt = <1500000>;
regulator-name = "vcc_ddr_1v35"; regulator-name = "vcc_ddr_1v35";

1
arch/arm/boot/dts/vexpress-v2p-ca5s.dts
View File

@ -132,6 +132,7 @@
reg = <0x2c0f0000 0x1000>; reg = <0x2c0f0000 0x1000>;
interrupts = <0 84 4>; interrupts = <0 84 4>;
cache-level = <2>; cache-level = <2>;
cache-unified;
}; };
pmu { pmu {

1
arch/arm64/boot/dts/arm/foundation-v8.dtsi
View File

@ -59,6 +59,7 @@
L2_0: l2-cache0 { L2_0: l2-cache0 {
compatible = "cache"; compatible = "cache";
cache-level = <2>; cache-level = <2>;
cache-unified;
}; };
}; };

1
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
View File

@ -72,6 +72,7 @@
L2_0: l2-cache0 { L2_0: l2-cache0 {
compatible = "cache"; compatible = "cache";
cache-level = <2>; cache-level = <2>;
cache-unified;
}; };
}; };

1
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
View File

@ -58,6 +58,7 @@
L2_0: l2-cache0 { L2_0: l2-cache0 {
compatible = "cache"; compatible = "cache";
cache-level = <2>; cache-level = <2>;
cache-unified;
}; };
}; };

1
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
View File

@ -171,6 +171,7 @@ conn_subsys: bus@5b000000 {
interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupt-names = "host", "peripheral", "otg", "wakeup";
phys = <&usb3_phy>; phys = <&usb3_phy>;
phy-names = "cdns3,usb3-phy"; phy-names = "cdns3,usb3-phy";
cdns,on-chip-buff-size = /bits/ 16 <18>;
status = "disabled"; status = "disabled";
}; };
}; };

8
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi
View File

@ -98,11 +98,17 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
ethphy: ethernet-phy@4 { ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
compatible = "ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>; reg = <4>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>; reset-assert-us = <10000>;
/*
* Deassert delay:
* ADIN1300 requires 5ms.
* AR8033 requires 1ms.
*/
reset-deassert-us = <20000>;
}; };
}; };
}; };

28
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@ -1069,13 +1069,6 @@
<&clk IMX8MN_CLK_DISP_APB_ROOT>, <&clk IMX8MN_CLK_DISP_APB_ROOT>,
<&clk IMX8MN_CLK_DISP_AXI_ROOT>; <&clk IMX8MN_CLK_DISP_AXI_ROOT>;
clock-names = "pix", "axi", "disp_axi"; clock-names = "pix", "axi", "disp_axi";
assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
<&clk IMX8MN_CLK_DISP_AXI>,
<&clk IMX8MN_CLK_DISP_APB>;
assigned-clock-parents = <&clk IMX8MN_CLK_DISP_PIXEL>,
<&clk IMX8MN_SYS_PLL2_1000M>,
<&clk IMX8MN_SYS_PLL1_800M>;
assigned-clock-rates = <594000000>, <500000000>, <200000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>; power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>;
status = "disabled"; status = "disabled";
@ -1093,12 +1086,6 @@
clocks = <&clk IMX8MN_CLK_DSI_CORE>, clocks = <&clk IMX8MN_CLK_DSI_CORE>,
<&clk IMX8MN_CLK_DSI_PHY_REF>; <&clk IMX8MN_CLK_DSI_PHY_REF>;
clock-names = "bus_clk", "sclk_mipi"; clock-names = "bus_clk", "sclk_mipi";
assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
<&clk IMX8MN_CLK_DSI_PHY_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
<&clk IMX8MN_CLK_24M>;
assigned-clock-rates = <266000000>, <24000000>;
samsung,pll-clock-frequency = <24000000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>; power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
status = "disabled"; status = "disabled";
@ -1142,6 +1129,21 @@
"lcdif-axi", "lcdif-apb", "lcdif-pix", "lcdif-axi", "lcdif-apb", "lcdif-pix",
"dsi-pclk", "dsi-ref", "dsi-pclk", "dsi-ref",
"csi-aclk", "csi-pclk"; "csi-aclk", "csi-pclk";
assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
<&clk IMX8MN_CLK_DSI_PHY_REF>,
<&clk IMX8MN_CLK_DISP_PIXEL>,
<&clk IMX8MN_CLK_DISP_AXI>,
<&clk IMX8MN_CLK_DISP_APB>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
<&clk IMX8MN_CLK_24M>,
<&clk IMX8MN_VIDEO_PLL1_OUT>,
<&clk IMX8MN_SYS_PLL2_1000M>,
<&clk IMX8MN_SYS_PLL1_800M>;
assigned-clock-rates = <266000000>,
<24000000>,
<594000000>,
<500000000>,
<200000000>;
#power-domain-cells = <1>; #power-domain-cells = <1>;
}; };

25
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -1211,13 +1211,6 @@
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>, <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pix", "axi", "disp_axi"; clock-names = "pix", "axi", "disp_axi";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
assigned-clock-parents = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
<&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <594000000>, <500000000>, <200000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
status = "disabled"; status = "disabled";
@ -1237,11 +1230,6 @@
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>, <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pix", "axi", "disp_axi"; clock-names = "pix", "axi", "disp_axi";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
<&clk IMX8MP_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>,
<&clk IMX8MP_VIDEO_PLL1_REF_SEL>;
assigned-clock-rates = <0>, <1039500000>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;
status = "disabled"; status = "disabled";
@ -1296,11 +1284,16 @@
"disp1", "disp2", "isp", "phy"; "disp1", "disp2", "isp", "phy";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>; <&clk IMX8MP_CLK_MEDIA_APB>,
<&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
<&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
<&clk IMX8MP_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>; <&clk IMX8MP_SYS_PLL1_800M>,
assigned-clock-rates = <500000000>, <200000000>; <&clk IMX8MP_VIDEO_PLL1_OUT>,
<&clk IMX8MP_VIDEO_PLL1_OUT>;
assigned-clock-rates = <500000000>, <200000000>,
<0>, <0>, <1039500000>;
#power-domain-cells = <1>; #power-domain-cells = <1>;
lvds_bridge: bridge@5c { lvds_bridge: bridge@5c {

6
arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
View File

@ -33,6 +33,12 @@
}; };
}; };
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>,
<&pinctrl_lpspi2_cs2>;
};
/* Colibri SPI */ /* Colibri SPI */
&lpspi2 { &lpspi2 {
status = "okay"; status = "okay";

3
arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi
View File

@ -48,8 +48,7 @@
<IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20>, /* SODIMM 101 */ <IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20>, /* SODIMM 101 */
<IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20>, /* SODIMM 97 */ <IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20>, /* SODIMM 97 */
<IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020>, /* SODIMM 85 */ <IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020>, /* SODIMM 85 */
<IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20>, /* SODIMM 79 */ <IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20>; /* SODIMM 79 */
<IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041>; /* SODIMM 45 */
}; };
pinctrl_uart1_forceoff: uart1forceoffgrp { pinctrl_uart1_forceoff: uart1forceoffgrp {

14
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
View File

@ -363,10 +363,6 @@
/* TODO VPU Encoder/Decoder */ /* TODO VPU Encoder/Decoder */
&iomuxc { &iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>,
<&pinctrl_hog2>, <&pinctrl_lpspi2_cs2>;
/* On-module touch pen-down interrupt */ /* On-module touch pen-down interrupt */
pinctrl_ad7879_int: ad7879intgrp { pinctrl_ad7879_int: ad7879intgrp {
fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21>; fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21>;
@ -499,8 +495,7 @@
}; };
pinctrl_hog1: hog1grp { pinctrl_hog1: hog1grp {
fsl,pins = <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20>, /* SODIMM 75 */ fsl,pins = <IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20>; /* SODIMM 93 */
<IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20>; /* SODIMM 93 */
}; };
pinctrl_hog2: hog2grp { pinctrl_hog2: hog2grp {
@ -774,3 +769,10 @@
fsl,pins = <IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20>; fsl,pins = <IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20>;
}; };
}; };
/* Delete peripherals which are not present on SOC, but are defined in imx8-ss-*.dtsi */
/delete-node/ &adc1;
/delete-node/ &adc1_lpcg;
/delete-node/ &dsp;
/delete-node/ &dsp_lpcg;

21
drivers/firmware/arm_ffa/bus.c
View File

@ -15,6 +15,8 @@
#include "common.h" #include "common.h"
static DEFINE_IDA(ffa_bus_id);
static int ffa_device_match(struct device *dev, struct device_driver *drv) static int ffa_device_match(struct device *dev, struct device_driver *drv)
{ {
const struct ffa_device_id *id_table; const struct ffa_device_id *id_table;
@ -53,7 +55,8 @@ static void ffa_device_remove(struct device *dev)
{ {
struct ffa_driver *ffa_drv = to_ffa_driver(dev->driver); struct ffa_driver *ffa_drv = to_ffa_driver(dev->driver);
ffa_drv->remove(to_ffa_dev(dev)); if (ffa_drv->remove)
ffa_drv->remove(to_ffa_dev(dev));
} }
static int ffa_device_uevent(const struct device *dev, struct kobj_uevent_env *env) static int ffa_device_uevent(const struct device *dev, struct kobj_uevent_env *env)
@ -130,6 +133,7 @@ static void ffa_release_device(struct device *dev)
{ {
struct ffa_device *ffa_dev = to_ffa_dev(dev); struct ffa_device *ffa_dev = to_ffa_dev(dev);
ida_free(&ffa_bus_id, ffa_dev->id);
kfree(ffa_dev); kfree(ffa_dev);
} }
@ -170,18 +174,24 @@ bool ffa_device_is_valid(struct ffa_device *ffa_dev)
struct ffa_device *ffa_device_register(const uuid_t *uuid, int vm_id, struct ffa_device *ffa_device_register(const uuid_t *uuid, int vm_id,
const struct ffa_ops *ops) const struct ffa_ops *ops)
{ {
int ret; int id, ret;
struct device *dev; struct device *dev;
struct ffa_device *ffa_dev; struct ffa_device *ffa_dev;
ffa_dev = kzalloc(sizeof(*ffa_dev), GFP_KERNEL); id = ida_alloc_min(&ffa_bus_id, 1, GFP_KERNEL);
if (!ffa_dev) if (id < 0)
return NULL; return NULL;
ffa_dev = kzalloc(sizeof(*ffa_dev), GFP_KERNEL);
if (!ffa_dev) {
ida_free(&ffa_bus_id, id);
return NULL;
}
dev = &ffa_dev->dev; dev = &ffa_dev->dev;
dev->bus = &ffa_bus_type; dev->bus = &ffa_bus_type;
dev->release = ffa_release_device; dev->release = ffa_release_device;
dev_set_name(&ffa_dev->dev, "arm-ffa-%04x", vm_id); dev_set_name(&ffa_dev->dev, "arm-ffa-%d", id);
ffa_dev->vm_id = vm_id; ffa_dev->vm_id = vm_id;
ffa_dev->ops = ops; ffa_dev->ops = ops;
@ -217,4 +227,5 @@ void arm_ffa_bus_exit(void)
{ {
ffa_devices_unregister(); ffa_devices_unregister();
bus_unregister(&ffa_bus_type); bus_unregister(&ffa_bus_type);
ida_destroy(&ffa_bus_id);
} }

9
drivers/firmware/arm_ffa/driver.c
View File

@ -193,7 +193,8 @@ __ffa_partition_info_get(u32 uuid0, u32 uuid1, u32 uuid2, u32 uuid3,
int idx, count, flags = 0, sz, buf_sz; int idx, count, flags = 0, sz, buf_sz;
ffa_value_t partition_info; ffa_value_t partition_info;
if (!buffer || !num_partitions) /* Just get the count for now */ if (drv_info->version > FFA_VERSION_1_0 &&
(!buffer || !num_partitions)) /* Just get the count for now */
flags = PARTITION_INFO_GET_RETURN_COUNT_ONLY; flags = PARTITION_INFO_GET_RETURN_COUNT_ONLY;
mutex_lock(&drv_info->rx_lock); mutex_lock(&drv_info->rx_lock);
@ -420,12 +421,17 @@ ffa_setup_and_transmit(u32 func_id, void *buffer, u32 max_fragsize,
ep_mem_access->receiver = args->attrs[idx].receiver; ep_mem_access->receiver = args->attrs[idx].receiver;
ep_mem_access->attrs = args->attrs[idx].attrs; ep_mem_access->attrs = args->attrs[idx].attrs;
ep_mem_access->composite_off = COMPOSITE_OFFSET(args->nattrs); ep_mem_access->composite_off = COMPOSITE_OFFSET(args->nattrs);
ep_mem_access->flag = 0;
ep_mem_access->reserved = 0;
} }
mem_region->reserved_0 = 0;
mem_region->reserved_1 = 0;
mem_region->ep_count = args->nattrs; mem_region->ep_count = args->nattrs;
composite = buffer + COMPOSITE_OFFSET(args->nattrs); composite = buffer + COMPOSITE_OFFSET(args->nattrs);
composite->total_pg_cnt = ffa_get_num_pages_sg(args->sg); composite->total_pg_cnt = ffa_get_num_pages_sg(args->sg);
composite->addr_range_cnt = num_entries; composite->addr_range_cnt = num_entries;
composite->reserved = 0;
length = COMPOSITE_CONSTITUENTS_OFFSET(args->nattrs, num_entries); length = COMPOSITE_CONSTITUENTS_OFFSET(args->nattrs, num_entries);
frag_len = COMPOSITE_CONSTITUENTS_OFFSET(args->nattrs, 0); frag_len = COMPOSITE_CONSTITUENTS_OFFSET(args->nattrs, 0);
@ -460,6 +466,7 @@ ffa_setup_and_transmit(u32 func_id, void *buffer, u32 max_fragsize,
constituents->address = sg_phys(args->sg); constituents->address = sg_phys(args->sg);
constituents->pg_cnt = args->sg->length / FFA_PAGE_SIZE; constituents->pg_cnt = args->sg->length / FFA_PAGE_SIZE;
constituents->reserved = 0;
constituents++; constituents++;
frag_len += sizeof(struct ffa_mem_region_addr_range); frag_len += sizeof(struct ffa_mem_region_addr_range);
} while ((args->sg = sg_next(args->sg))); } while ((args->sg = sg_next(args->sg)));

2
drivers/firmware/arm_scmi/raw_mode.c
View File

@ -1066,7 +1066,7 @@ static int scmi_xfer_raw_worker_init(struct scmi_raw_mode_info *raw)
raw->wait_wq = alloc_workqueue("scmi-raw-wait-wq-%d", raw->wait_wq = alloc_workqueue("scmi-raw-wait-wq-%d",
WQ_UNBOUND | WQ_FREEZABLE | WQ_UNBOUND | WQ_FREEZABLE |
WQ_HIGHPRI, WQ_SYSFS, raw->id); WQ_HIGHPRI | WQ_SYSFS, 0, raw->id);
if (!raw->wait_wq) if (!raw->wait_wq)
return -ENOMEM; return -ENOMEM;

4
drivers/tee/optee/smc_abi.c
View File

@ -1004,8 +1004,10 @@ static u32 get_async_notif_value(optee_invoke_fn *invoke_fn, bool *value_valid,
invoke_fn(OPTEE_SMC_GET_ASYNC_NOTIF_VALUE, 0, 0, 0, 0, 0, 0, 0, &res); invoke_fn(OPTEE_SMC_GET_ASYNC_NOTIF_VALUE, 0, 0, 0, 0, 0, 0, 0, &res);
if (res.a0) if (res.a0) {
*value_valid = false;
return 0; return 0;
}
*value_valid = (res.a2 & OPTEE_SMC_ASYNC_NOTIF_VALUE_VALID); *value_valid = (res.a2 & OPTEE_SMC_ASYNC_NOTIF_VALUE_VALID);
*value_pending = (res.a2 & OPTEE_SMC_ASYNC_NOTIF_VALUE_PENDING); *value_pending = (res.a2 & OPTEE_SMC_ASYNC_NOTIF_VALUE_PENDING);
return res.a1; return res.a1;

1
include/linux/arm_ffa.h
View File

@ -96,6 +96,7 @@
/* FFA Bus/Device/Driver related */ /* FFA Bus/Device/Driver related */
struct ffa_device { struct ffa_device {
u32 id;
int vm_id; int vm_id;
bool mode_32bit; bool mode_32bit;
uuid_t uuid; uuid_t uuid;