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net: mvpp2: software tso support
The patch uses the tso API to implement the tso functionality in Marvell PPv2 driver. Using iperf and 10G ports, using TSO shows a significant performance improvement by a factor 2 to reach around 9.5Gbps in TX; as well as a significant CPU usage drop (from 25% to 15%). Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Antoine Ténart
David S. Miller
parent
85affd7e29
commit
186cd4d4e4
@ -35,6 +35,7 @@
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#include <uapi/linux/ppp_defs.h>
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#include <net/ip.h>
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#include <net/ipv6.h>
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#include <net/tso.h>
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/* RX Fifo Registers */
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#define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
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@ -1010,6 +1011,10 @@ struct mvpp2_txq_pcpu {
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/* Index of the TX DMA descriptor to be cleaned up */
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int txq_get_index;
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/* DMA buffer for TSO headers */
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char *tso_headers;
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dma_addr_t tso_headers_dma;
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};
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struct mvpp2_tx_queue {
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@ -5494,6 +5499,14 @@ static int mvpp2_txq_init(struct mvpp2_port *port,
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txq_pcpu->reserved_num = 0;
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txq_pcpu->txq_put_index = 0;
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txq_pcpu->txq_get_index = 0;
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txq_pcpu->tso_headers =
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dma_alloc_coherent(port->dev->dev.parent,
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MVPP2_AGGR_TXQ_SIZE * TSO_HEADER_SIZE,
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&txq_pcpu->tso_headers_dma,
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GFP_KERNEL);
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if (!txq_pcpu->tso_headers)
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goto cleanup;
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}
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return 0;
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@ -5501,6 +5514,11 @@ cleanup:
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for_each_present_cpu(cpu) {
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txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
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kfree(txq_pcpu->buffs);
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dma_free_coherent(port->dev->dev.parent,
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MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
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txq_pcpu->tso_headers,
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txq_pcpu->tso_headers_dma);
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}
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dma_free_coherent(port->dev->dev.parent,
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@ -5520,6 +5538,11 @@ static void mvpp2_txq_deinit(struct mvpp2_port *port,
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for_each_present_cpu(cpu) {
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txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
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kfree(txq_pcpu->buffs);
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dma_free_coherent(port->dev->dev.parent,
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MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
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txq_pcpu->tso_headers,
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txq_pcpu->tso_headers_dma);
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}
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if (txq->descs)
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@ -6049,6 +6072,123 @@ cleanup:
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return -ENOMEM;
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}
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static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
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struct net_device *dev,
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struct mvpp2_tx_queue *txq,
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struct mvpp2_tx_queue *aggr_txq,
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struct mvpp2_txq_pcpu *txq_pcpu,
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int hdr_sz)
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{
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struct mvpp2_port *port = netdev_priv(dev);
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struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
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dma_addr_t addr;
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mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
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mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
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addr = txq_pcpu->tso_headers_dma +
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txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
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mvpp2_txdesc_offset_set(port, tx_desc, addr & MVPP2_TX_DESC_ALIGN);
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mvpp2_txdesc_dma_addr_set(port, tx_desc, addr & ~MVPP2_TX_DESC_ALIGN);
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mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
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MVPP2_TXD_F_DESC |
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MVPP2_TXD_PADDING_DISABLE);
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mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
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}
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static inline int mvpp2_tso_put_data(struct sk_buff *skb,
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struct net_device *dev, struct tso_t *tso,
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struct mvpp2_tx_queue *txq,
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struct mvpp2_tx_queue *aggr_txq,
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struct mvpp2_txq_pcpu *txq_pcpu,
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int sz, bool left, bool last)
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{
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struct mvpp2_port *port = netdev_priv(dev);
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struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
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dma_addr_t buf_dma_addr;
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mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
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mvpp2_txdesc_size_set(port, tx_desc, sz);
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buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz,
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DMA_TO_DEVICE);
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if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
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mvpp2_txq_desc_put(txq);
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return -ENOMEM;
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}
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mvpp2_txdesc_offset_set(port, tx_desc,
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buf_dma_addr & MVPP2_TX_DESC_ALIGN);
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mvpp2_txdesc_dma_addr_set(port, tx_desc,
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buf_dma_addr & ~MVPP2_TX_DESC_ALIGN);
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if (!left) {
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mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
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if (last) {
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mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
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return 0;
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}
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} else {
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mvpp2_txdesc_cmd_set(port, tx_desc, 0);
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}
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mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
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return 0;
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}
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static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev,
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struct mvpp2_tx_queue *txq,
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struct mvpp2_tx_queue *aggr_txq,
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struct mvpp2_txq_pcpu *txq_pcpu)
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{
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struct mvpp2_port *port = netdev_priv(dev);
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struct tso_t tso;
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int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb);
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int i, len, descs = 0;
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/* Check number of available descriptors */
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if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq,
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tso_count_descs(skb)) ||
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mvpp2_txq_reserved_desc_num_proc(port->priv, txq, txq_pcpu,
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tso_count_descs(skb)))
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return 0;
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tso_start(skb, &tso);
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len = skb->len - hdr_sz;
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while (len > 0) {
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int left = min_t(int, skb_shinfo(skb)->gso_size, len);
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char *hdr = txq_pcpu->tso_headers +
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txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
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len -= left;
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descs++;
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tso_build_hdr(skb, hdr, &tso, left, len == 0);
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mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz);
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while (left > 0) {
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int sz = min_t(int, tso.size, left);
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left -= sz;
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descs++;
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if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq,
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txq_pcpu, sz, left, len == 0))
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goto release;
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tso_build_data(skb, &tso, sz);
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}
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}
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return descs;
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release:
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for (i = descs - 1; i >= 0; i--) {
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struct mvpp2_tx_desc *tx_desc = txq->descs + i;
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tx_desc_unmap_put(port, txq, tx_desc);
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}
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return 0;
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}
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/* Main tx processing */
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static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
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{
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@ -6066,6 +6206,10 @@ static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
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txq_pcpu = this_cpu_ptr(txq->pcpu);
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aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
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if (skb_is_gso(skb)) {
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frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu);
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goto out;
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}
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frags = skb_shinfo(skb)->nr_frags + 1;
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/* Check number of available descriptors */
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@ -6115,22 +6259,21 @@ static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
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}
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}
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txq_pcpu->reserved_num -= frags;
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txq_pcpu->count += frags;
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aggr_txq->count += frags;
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/* Enable transmit */
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wmb();
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mvpp2_aggr_txq_pend_desc_add(port, frags);
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if (txq_pcpu->size - txq_pcpu->count < MAX_SKB_FRAGS + 1) {
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struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
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netif_tx_stop_queue(nq);
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}
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out:
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if (frags > 0) {
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struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
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struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
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txq_pcpu->reserved_num -= frags;
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txq_pcpu->count += frags;
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aggr_txq->count += frags;
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/* Enable transmit */
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wmb();
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mvpp2_aggr_txq_pend_desc_add(port, frags);
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if (txq_pcpu->size - txq_pcpu->count < MAX_SKB_FRAGS + 1)
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netif_tx_stop_queue(nq);
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u64_stats_update_begin(&stats->syncp);
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stats->tx_packets++;
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@ -7255,7 +7398,7 @@ static int mvpp2_port_probe(struct platform_device *pdev,
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}
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}
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features = NETIF_F_SG | NETIF_F_IP_CSUM;
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features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
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dev->features = features | NETIF_F_RXCSUM;
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dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO;
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dev->vlan_features |= features;
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