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siimage: add sil_* I/O ops
Add sil_iowrite{8,16,32}() and sil_ioread{8,16}() helpers, then use them to
merge code accessing configuration registers through PCI and MMIO together.
[ because of this SATA initialization bits from setup_mmio_siimage() are
moved to init_chipset_siimage() ]
This also cuts code size a bit:
text data bss dec hex filename
4437 164 0 4601 11f9 drivers/ide/pci/siimage.o.before
3979 164 0 4143 102f drivers/ide/pci/siimage.o.after
While at it:
* Use I/O ops directly instead of using ->IN{B,W} and ->OUT{B,W}.
* Fixup CodingStyle in setup_mmio_siimage().
* Rename 'tmpbyte' variable to 'tmp' in init_chipset_siimage().
There should be no functional changes caused by this patch.
Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Bartlomiej Zolnierkiewicz
parent
24a96ae0e3
commit
165701d9fc
@ -2,7 +2,7 @@
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* Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2003 Red Hat <alan@redhat.com>
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
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* Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
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*
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* May be copied or modified under the terms of the GNU General Public License
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*
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@ -124,6 +124,54 @@ static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
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return base;
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}
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static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr)
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{
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u8 tmp = 0;
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if (pci_get_drvdata(dev))
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tmp = readb((void __iomem *)addr);
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else
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pci_read_config_byte(dev, addr, &tmp);
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return tmp;
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}
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static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr)
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{
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u16 tmp = 0;
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if (pci_get_drvdata(dev))
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tmp = readw((void __iomem *)addr);
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else
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pci_read_config_word(dev, addr, &tmp);
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return tmp;
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}
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static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr)
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{
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if (pci_get_drvdata(dev))
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writeb(val, (void __iomem *)addr);
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else
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pci_write_config_byte(dev, addr, val);
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}
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static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr)
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{
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if (pci_get_drvdata(dev))
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writew(val, (void __iomem *)addr);
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else
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pci_write_config_word(dev, addr, val);
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}
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static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr)
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{
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if (pci_get_drvdata(dev))
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writel(val, (void __iomem *)addr);
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else
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pci_write_config_dword(dev, addr, val);
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}
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/**
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* sil_udma_filter - compute UDMA mask
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* @drive: IDE device
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@ -139,12 +187,9 @@ static u8 sil_pata_udma_filter(ide_drive_t *drive)
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ide_hwif_t *hwif = drive->hwif;
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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unsigned long base = (unsigned long) hwif->hwif_data;
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u8 mask = 0, scsc = 0;
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u8 mask = 0, scsc;
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if (hwif->mmio)
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scsc = hwif->INB(base + 0x4A);
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else
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pci_read_config_byte(dev, 0x8A, &scsc);
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scsc = sil_ioread8(dev, base + (hwif->mmio ? 0x4A : 0x8A));
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if ((scsc & 0x30) == 0x10) /* 133 */
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mask = ATA_UDMA6;
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@ -179,6 +224,7 @@ static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
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const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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ide_drive_t *pair = ide_get_paired_drive(drive);
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u32 speedt = 0;
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u16 speedp = 0;
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@ -203,36 +249,20 @@ static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
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speedp = data_speed[pio];
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speedt = tf_speed[tf_pio];
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if (hwif->mmio) {
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hwif->OUTW(speedp, addr);
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hwif->OUTW(speedt, tfaddr);
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/* Now set up IORDY */
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if (pio > 2)
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hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
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else
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hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
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sil_iowrite16(dev, speedp, addr);
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sil_iowrite16(dev, speedt, tfaddr);
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mode = hwif->INB(base + addr_mask);
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mode &= ~(unit ? 0x30 : 0x03);
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mode |= (unit ? 0x10 : 0x01);
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hwif->OUTB(mode, base + addr_mask);
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} else {
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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/* now set up IORDY */
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speedp = sil_ioread16(dev, tfaddr - 2);
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speedp &= ~0x200;
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if (pio > 2)
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speedp |= 0x200;
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sil_iowrite16(dev, speedp, tfaddr - 2);
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pci_write_config_word(dev, addr, speedp);
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pci_write_config_word(dev, tfaddr, speedt);
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pci_read_config_word(dev, tfaddr - 2, &speedp);
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speedp &= ~0x200;
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/* Set IORDY for mode 3 or 4 */
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if (pio > 2)
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speedp |= 0x200;
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pci_write_config_word(dev, tfaddr - 2, speedp);
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pci_read_config_byte(dev, addr_mask, &mode);
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mode &= ~(unit ? 0x30 : 0x03);
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mode |= (unit ? 0x10 : 0x01);
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pci_write_config_byte(dev, addr_mask, mode);
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}
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mode = sil_ioread8(dev, base + addr_mask);
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mode &= ~(unit ? 0x30 : 0x03);
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mode |= (unit ? 0x10 : 0x01);
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sil_iowrite8(dev, mode, base + addr_mask);
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}
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/**
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@ -261,17 +291,10 @@ static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
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unsigned long ma = siimage_seldev(drive, 0x08);
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unsigned long ua = siimage_seldev(drive, 0x0C);
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if (hwif->mmio) {
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scsc = hwif->INB(base + 0x4A);
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mode = hwif->INB(base + addr_mask);
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multi = hwif->INW(ma);
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ultra = hwif->INW(ua);
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} else {
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pci_read_config_byte(dev, 0x8A, &scsc);
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pci_read_config_byte(dev, addr_mask, &mode);
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pci_read_config_word(dev, ma, &multi);
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pci_read_config_word(dev, ua, &ultra);
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}
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scsc = sil_ioread8(dev, base + (hwif->mmio ? 0x4A : 0x8A));
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mode = sil_ioread8(dev, base + addr_mask);
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multi = sil_ioread16(dev, ma);
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ultra = sil_ioread16(dev, ua);
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mode &= ~((unit) ? 0x30 : 0x03);
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ultra &= ~0x3F;
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@ -289,15 +312,9 @@ static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
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mode |= (unit ? 0x20 : 0x02);
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}
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if (hwif->mmio) {
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hwif->OUTB(mode, base + addr_mask);
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hwif->OUTW(multi, ma);
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hwif->OUTW(ultra, ua);
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} else {
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pci_write_config_byte(dev, addr_mask, mode);
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pci_write_config_word(dev, ma, multi);
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pci_write_config_word(dev, ua, ultra);
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}
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sil_iowrite8(dev, mode, base + addr_mask);
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sil_iowrite16(dev, multi, ma);
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sil_iowrite16(dev, ultra, ua);
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}
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/* returns 1 if dma irq issued, 0 otherwise */
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@ -460,26 +477,21 @@ static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
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{
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resource_size_t bar5 = pci_resource_start(dev, 5);
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unsigned long barsize = pci_resource_len(dev, 5);
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u8 tmpbyte = 0;
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void __iomem *ioaddr;
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u32 tmp, irq_mask;
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/*
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* Drop back to PIO if we can't map the mmio. Some
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* systems seem to get terminally confused in the PCI
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* spaces.
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*/
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if(!request_mem_region(bar5, barsize, name))
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{
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if (!request_mem_region(bar5, barsize, name)) {
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printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
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return 0;
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}
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ioaddr = ioremap(bar5, barsize);
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if (ioaddr == NULL)
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{
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if (ioaddr == NULL) {
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release_mem_region(bar5, barsize);
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return 0;
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}
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@ -487,62 +499,6 @@ static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
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pci_set_master(dev);
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pci_set_drvdata(dev, (void *) ioaddr);
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if (pdev_is_sata(dev)) {
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/* make sure IDE0/1 interrupts are not masked */
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irq_mask = (1 << 22) | (1 << 23);
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tmp = readl(ioaddr + 0x48);
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if (tmp & irq_mask) {
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tmp &= ~irq_mask;
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writel(tmp, ioaddr + 0x48);
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readl(ioaddr + 0x48); /* flush */
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}
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writel(0, ioaddr + 0x148);
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writel(0, ioaddr + 0x1C8);
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}
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writeb(0, ioaddr + 0xB4);
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writeb(0, ioaddr + 0xF4);
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tmpbyte = readb(ioaddr + 0x4A);
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switch(tmpbyte & 0x30) {
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case 0x00:
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/* In 100 MHz clocking, try and switch to 133 */
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writeb(tmpbyte|0x10, ioaddr + 0x4A);
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break;
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case 0x10:
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/* On 133Mhz clocking */
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break;
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case 0x20:
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/* On PCIx2 clocking */
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break;
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case 0x30:
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/* Clocking is disabled */
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/* 133 clock attempt to force it on */
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writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
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break;
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}
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tmpbyte = readb(ioaddr + 0x4A);
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writeb( 0x72, ioaddr + 0xA1);
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writew( 0x328A, ioaddr + 0xA2);
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writel(0x62DD62DD, ioaddr + 0xA4);
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writel(0x43924392, ioaddr + 0xA8);
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writel(0x40094009, ioaddr + 0xAC);
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writeb( 0x72, ioaddr + 0xE1);
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writew( 0x328A, ioaddr + 0xE2);
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writel(0x62DD62DD, ioaddr + 0xE4);
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writel(0x43924392, ioaddr + 0xE8);
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writel(0x40094009, ioaddr + 0xEC);
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if (pdev_is_sata(dev)) {
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writel(0xFFFF0000, ioaddr + 0x108);
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writel(0xFFFF0000, ioaddr + 0x188);
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writel(0x00680000, ioaddr + 0x148);
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writel(0x00680000, ioaddr + 0x1C8);
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}
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proc_reports_siimage(dev, (tmpbyte>>4), name);
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return 1;
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}
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@ -557,50 +513,80 @@ static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
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static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
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{
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u8 rev = dev->revision, tmpbyte = 0, BA5_EN = 0;
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unsigned long base, scsc_addr;
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void __iomem *ioaddr = NULL;
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u8 rev = dev->revision, tmp = 0, BA5_EN = 0;
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
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pci_read_config_byte(dev, 0x8A, &BA5_EN);
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if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
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if (setup_mmio_siimage(dev, name)) {
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return 0;
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if ((BA5_EN & 0x01) || pci_resource_start(dev, 5)) {
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if (setup_mmio_siimage(dev, name))
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ioaddr = pci_get_drvdata(dev);
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}
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base = (unsigned long)ioaddr;
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if (ioaddr && pdev_is_sata(dev)) {
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u32 tmp32, irq_mask;
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/* make sure IDE0/1 interrupts are not masked */
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irq_mask = (1 << 22) | (1 << 23);
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tmp32 = readl(ioaddr + 0x48);
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if (tmp32 & irq_mask) {
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tmp32 &= ~irq_mask;
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writel(tmp32, ioaddr + 0x48);
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readl(ioaddr + 0x48); /* flush */
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}
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writel(0, ioaddr + 0x148);
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writel(0, ioaddr + 0x1C8);
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}
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pci_write_config_byte(dev, 0x80, 0x00);
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pci_write_config_byte(dev, 0x84, 0x00);
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pci_read_config_byte(dev, 0x8A, &tmpbyte);
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switch(tmpbyte & 0x30) {
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case 0x00:
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/* 133 clock attempt to force it on */
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pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
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case 0x30:
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/* if clocking is disabled */
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/* 133 clock attempt to force it on */
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pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
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case 0x10:
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/* 133 already */
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break;
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case 0x20:
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/* BIOS set PCI x2 clocking */
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break;
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sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
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sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
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scsc_addr = base ? (base + 0x4A) : 0x8A;
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tmp = sil_ioread8(dev, scsc_addr);
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switch (tmp & 0x30) {
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case 0x00:
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/* On 100MHz clocking, try and switch to 133MHz */
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sil_iowrite8(dev, tmp | 0x10, scsc_addr);
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break;
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case 0x30:
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/* Clocking is disabled, attempt to force 133MHz clocking. */
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sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
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case 0x10:
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/* On 133Mhz clocking. */
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break;
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case 0x20:
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/* On PCIx2 clocking. */
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break;
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}
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pci_read_config_byte(dev, 0x8A, &tmpbyte);
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tmp = sil_ioread8(dev, scsc_addr);
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pci_write_config_byte(dev, 0xA1, 0x72);
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pci_write_config_word(dev, 0xA2, 0x328A);
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pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
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pci_write_config_dword(dev, 0xA8, 0x43924392);
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pci_write_config_dword(dev, 0xAC, 0x40094009);
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pci_write_config_byte(dev, 0xB1, 0x72);
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pci_write_config_word(dev, 0xB2, 0x328A);
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pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
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pci_write_config_dword(dev, 0xB8, 0x43924392);
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pci_write_config_dword(dev, 0xBC, 0x40094009);
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sil_iowrite8(dev, 0x72, base + 0xA1);
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sil_iowrite16(dev, 0x328A, base + 0xA2);
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sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
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sil_iowrite32(dev, 0x43924392, base + 0xA8);
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sil_iowrite32(dev, 0x40094009, base + 0xAC);
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sil_iowrite8(dev, 0x72, base ? (base + 0xE1) : 0xB1);
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sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2);
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sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
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sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
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sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
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if (base && pdev_is_sata(dev)) {
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writel(0xFFFF0000, ioaddr + 0x108);
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writel(0xFFFF0000, ioaddr + 0x188);
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writel(0x00680000, ioaddr + 0x148);
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writel(0x00680000, ioaddr + 0x1C8);
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}
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proc_reports_siimage(dev, tmp >> 4, name);
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proc_reports_siimage(dev, (tmpbyte>>4), name);
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return 0;
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}
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@ -752,12 +738,7 @@ static u8 __devinit sil_cable_detect(ide_hwif_t *hwif)
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{
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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unsigned long addr = siimage_selreg(hwif, 0);
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u8 ata66 = 0;
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if (pci_get_drvdata(dev) == NULL)
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pci_read_config_byte(dev, addr, &ata66);
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else
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ata66 = hwif->INB(addr);
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u8 ata66 = sil_ioread8(dev, addr);
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return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
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}
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