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perf vendor events arm64 AmpereOneX: Add core PMU events and metrics
Add JSON files for AmpereOneX core PMU events and metrics. Reviewed-by: Ian Rogers <irogers@google.com> Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20231201021550.1109196-4-ilkka@os.amperecomputing.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ilkka Koskinen
Arnaldo Carvalho de Melo
parent
10a149e4b4
commit
16438b652b
125
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/branch.json
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125
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/branch.json
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[
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{
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"ArchStdEvent": "BR_IMMED_SPEC"
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},
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{
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"ArchStdEvent": "BR_RETURN_SPEC"
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},
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{
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"ArchStdEvent": "BR_INDIRECT_SPEC"
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},
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{
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"ArchStdEvent": "BR_MIS_PRED"
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},
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{
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"ArchStdEvent": "BR_PRED"
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},
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{
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"PublicDescription": "Instruction architecturally executed, branch not taken",
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"EventCode": "0x8107",
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"EventName": "BR_SKIP_RETIRED",
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"BriefDescription": "Instruction architecturally executed, branch not taken"
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},
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{
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"PublicDescription": "Instruction architecturally executed, immediate branch taken",
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"EventCode": "0x8108",
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"EventName": "BR_IMMED_TAKEN_RETIRED",
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"BriefDescription": "Instruction architecturally executed, immediate branch taken"
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},
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{
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"PublicDescription": "Instruction architecturally executed, indirect branch excluding return retired",
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"EventCode": "0x810c",
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"EventName": "BR_INDNR_TAKEN_RETIRED",
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"BriefDescription": "Instruction architecturally executed, indirect branch excluding return retired"
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},
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{
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"PublicDescription": "Instruction architecturally executed, predicted immediate branch",
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"EventCode": "0x8110",
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"EventName": "BR_IMMED_PRED_RETIRED",
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"BriefDescription": "Instruction architecturally executed, predicted immediate branch"
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},
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{
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"PublicDescription": "Instruction architecturally executed, mispredicted immediate branch",
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"EventCode": "0x8111",
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"EventName": "BR_IMMED_MIS_PRED_RETIRED",
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"BriefDescription": "Instruction architecturally executed, mispredicted immediate branch"
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},
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{
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"PublicDescription": "Instruction architecturally executed, predicted indirect branch",
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"EventCode": "0x8112",
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"EventName": "BR_IND_PRED_RETIRED",
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"BriefDescription": "Instruction architecturally executed, predicted indirect branch"
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},
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{
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"PublicDescription": "Instruction architecturally executed, mispredicted indirect branch",
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"EventCode": "0x8113",
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"EventName": "BR_IND_MIS_PRED_RETIRED",
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"BriefDescription": "Instruction architecturally executed, mispredicted indirect branch"
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},
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{
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"PublicDescription": "Instruction architecturally executed, predicted procedure return",
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"EventCode": "0x8114",
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"EventName": "BR_RETURN_PRED_RETIRED",
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"BriefDescription": "Instruction architecturally executed, predicted procedure return"
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},
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{
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"PublicDescription": "Instruction architecturally executed, mispredicted procedure return",
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"EventCode": "0x8115",
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"EventName": "BR_RETURN_MIS_PRED_RETIRED",
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"BriefDescription": "Instruction architecturally executed, mispredicted procedure return"
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},
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{
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"PublicDescription": "Instruction architecturally executed, predicted indirect branch excluding return",
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"EventCode": "0x8116",
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"EventName": "BR_INDNR_PRED_RETIRED",
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"BriefDescription": "Instruction architecturally executed, predicted indirect branch excluding return"
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},
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{
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"PublicDescription": "Instruction architecturally executed, mispredicted indirect branch excluding return",
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"EventCode": "0x8117",
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"EventName": "BR_INDNR_MIS_PRED_RETIRED",
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"BriefDescription": "Instruction architecturally executed, mispredicted indirect branch excluding return"
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},
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{
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"PublicDescription": "Instruction architecturally executed, predicted branch, taken",
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"EventCode": "0x8118",
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"EventName": "BR_TAKEN_PRED_RETIRED",
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"BriefDescription": "Instruction architecturally executed, predicted branch, taken"
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},
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{
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"PublicDescription": "Instruction architecturally executed, mispredicted branch, taken",
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"EventCode": "0x8119",
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"EventName": "BR_TAKEN_MIS_PRED_RETIRED",
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"BriefDescription": "Instruction architecturally executed, mispredicted branch, taken"
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},
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{
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"PublicDescription": "Instruction architecturally executed, predicted branch, not taken",
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"EventCode": "0x811a",
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"EventName": "BR_SKIP_PRED_RETIRED",
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"BriefDescription": "Instruction architecturally executed, predicted branch, not taken"
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},
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{
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"PublicDescription": "Instruction architecturally executed, mispredicted branch, not taken",
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"EventCode": "0x811b",
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"EventName": "BR_SKIP_MIS_PRED_RETIRED",
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"BriefDescription": "Instruction architecturally executed, mispredicted branch, not taken"
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},
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{
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"PublicDescription": "Instruction architecturally executed, predicted branch",
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"EventCode": "0x811c",
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"EventName": "BR_PRED_RETIRED",
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"BriefDescription": "Instruction architecturally executed, predicted branch"
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},
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{
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"PublicDescription": "Instruction architecturally executed, indirect branch",
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"EventCode": "0x811d",
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"EventName": "BR_IND_RETIRED",
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"BriefDescription": "Instruction architecturally executed, indirect branch"
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},
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{
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"PublicDescription": "Branch Record captured.",
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"EventCode": "0x811f",
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"EventName": "BRB_FILTRATE",
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"BriefDescription": "Branch Record captured."
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}
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]
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20
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/bus.json
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20
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/bus.json
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@ -0,0 +1,20 @@
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[
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{
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"ArchStdEvent": "CPU_CYCLES"
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},
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{
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"ArchStdEvent": "BUS_CYCLES"
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},
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{
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"ArchStdEvent": "BUS_ACCESS_RD"
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},
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{
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"ArchStdEvent": "BUS_ACCESS_WR"
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},
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{
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"ArchStdEvent": "BUS_ACCESS"
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},
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{
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"ArchStdEvent": "CNT_CYCLES"
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}
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]
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206
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json
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206
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json
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[
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{
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"ArchStdEvent": "L1D_CACHE_RD"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WR"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_RD"
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},
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{
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"ArchStdEvent": "L1D_CACHE_INVAL"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL_RD"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_RD"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL_RD"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
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},
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{
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"ArchStdEvent": "L2D_CACHE_INVAL"
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},
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{
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"ArchStdEvent": "L1I_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L1I_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L1D_CACHE"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L1I_CACHE"
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},
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{
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"ArchStdEvent": "L2D_CACHE"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB"
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},
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{
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"ArchStdEvent": "L1D_TLB"
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},
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{
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"ArchStdEvent": "L1I_TLB"
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},
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{
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"ArchStdEvent": "L2D_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L2I_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L2D_TLB"
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},
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{
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"ArchStdEvent": "L2I_TLB"
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},
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{
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"ArchStdEvent": "DTLB_WALK"
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},
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{
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"ArchStdEvent": "ITLB_WALK"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_WR"
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},
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{
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"ArchStdEvent": "L1D_CACHE_LMISS_RD"
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},
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{
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"ArchStdEvent": "L1I_CACHE_LMISS"
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},
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{
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"ArchStdEvent": "L2D_CACHE_LMISS_RD"
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},
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{
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"PublicDescription": "Level 1 data or unified cache demand access",
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"EventCode": "0x8140",
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"EventName": "L1D_CACHE_RW",
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"BriefDescription": "Level 1 data or unified cache demand access"
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},
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{
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"PublicDescription": "Level 1 data or unified cache preload or prefetch",
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"EventCode": "0x8142",
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"EventName": "L1D_CACHE_PRFM",
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"BriefDescription": "Level 1 data or unified cache preload or prefetch"
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},
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{
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"PublicDescription": "Level 1 data or unified cache refill, preload or prefetch",
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"EventCode": "0x8146",
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"EventName": "L1D_CACHE_REFILL_PRFM",
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"BriefDescription": "Level 1 data or unified cache refill, preload or prefetch"
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},
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{
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"ArchStdEvent": "L1D_TLB_RD"
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},
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{
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"ArchStdEvent": "L1D_TLB_WR"
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},
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{
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"ArchStdEvent": "L2D_TLB_REFILL_RD"
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},
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{
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"ArchStdEvent": "L2D_TLB_REFILL_WR"
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},
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{
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"ArchStdEvent": "L2D_TLB_RD"
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},
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{
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"ArchStdEvent": "L2D_TLB_WR"
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},
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{
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"PublicDescription": "L1D TLB miss",
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"EventCode": "0xD600",
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"EventName": "L1D_TLB_MISS",
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"BriefDescription": "L1D TLB miss"
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},
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{
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"PublicDescription": "Level 1 prefetcher, load prefetch requests generated",
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"EventCode": "0xd606",
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"EventName": "L1_PREFETCH_LD_GEN",
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"BriefDescription": "Level 1 prefetcher, load prefetch requests generated"
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},
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{
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"PublicDescription": "Level 1 prefetcher, load prefetch fills into the level 1 cache",
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"EventCode": "0xd607",
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"EventName": "L1_PREFETCH_LD_FILL",
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"BriefDescription": "Level 1 prefetcher, load prefetch fills into the level 1 cache"
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},
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{
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"PublicDescription": "Level 1 prefetcher, load prefetch to level 2 generated",
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"EventCode": "0xd608",
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"EventName": "L1_PREFETCH_L2_REQ",
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"BriefDescription": "Level 1 prefetcher, load prefetch to level 2 generated"
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},
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{
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"PublicDescription": "L1 prefetcher, distance was reset",
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"EventCode": "0xd609",
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"EventName": "L1_PREFETCH_DIST_RST",
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"BriefDescription": "L1 prefetcher, distance was reset"
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},
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{
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"PublicDescription": "L1 prefetcher, distance was increased",
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"EventCode": "0xd60a",
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"EventName": "L1_PREFETCH_DIST_INC",
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"BriefDescription": "L1 prefetcher, distance was increased"
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},
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{
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"PublicDescription": "Level 1 prefetcher, table entry is trained",
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"EventCode": "0xd60b",
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"EventName": "L1_PREFETCH_ENTRY_TRAINED",
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"BriefDescription": "Level 1 prefetcher, table entry is trained"
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},
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{
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"PublicDescription": "L1 data cache refill - Read or Write",
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"EventCode": "0xd60e",
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"EventName": "L1D_CACHE_REFILL_RW",
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"BriefDescription": "L1 data cache refill - Read or Write"
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},
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{
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"PublicDescription": "Level 2 cache refill from instruction-side miss, including IMMU refills",
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"EventCode": "0xD701",
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"EventName": "L2C_INST_REFILL",
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"BriefDescription": "Level 2 cache refill from instruction-side miss, including IMMU refills"
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},
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{
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"PublicDescription": "Level 2 cache refill from data-side miss, including DMMU refills",
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"EventCode": "0xD702",
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"EventName": "L2C_DATA_REFILL",
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"BriefDescription": "Level 2 cache refill from data-side miss, including DMMU refills"
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},
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{
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"PublicDescription": "Level 2 cache prefetcher, load prefetch requests generated",
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"EventCode": "0xD703",
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"EventName": "L2_PREFETCH_REQ",
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"BriefDescription": "Level 2 cache prefetcher, load prefetch requests generated"
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}
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]
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[
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{
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"PublicDescription": "Level 2 prefetch requests, refilled to L2 cache",
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"EventCode": "0x10A",
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"EventName": "L2_PREFETCH_REFILL",
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"BriefDescription": "Level 2 prefetch requests, refilled to L2 cache"
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},
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{
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"PublicDescription": "Level 2 prefetch requests, late",
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"EventCode": "0x10B",
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"EventName": "L2_PREFETCH_UPGRADE",
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"BriefDescription": "Level 2 prefetch requests, late"
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},
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{
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"PublicDescription": "Predictable branch speculatively executed that hit any level of BTB",
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"EventCode": "0x110",
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"EventName": "BPU_HIT_BTB",
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"BriefDescription": "Predictable branch speculatively executed that hit any level of BTB"
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},
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{
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"PublicDescription": "Predictable conditional branch speculatively executed that hit any level of BTB",
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"EventCode": "0x111",
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"EventName": "BPU_CONDITIONAL_BRANCH_HIT_BTB",
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"BriefDescription": "Predictable conditional branch speculatively executed that hit any level of BTB"
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},
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{
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"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor",
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"EventCode": "0x112",
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"EventName": "BPU_HIT_INDIRECT_PREDICTOR",
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"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor"
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},
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{
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"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor",
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"EventCode": "0x113",
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"EventName": "BPU_HIT_RSB",
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"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor"
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},
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{
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"PublicDescription": "Predictable unconditional branch speculatively executed that did not hit any level of BTB",
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"EventCode": "0x114",
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"EventName": "BPU_UNCONDITIONAL_BRANCH_MISS_BTB",
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"BriefDescription": "Predictable unconditional branch speculatively executed that did not hit any level of BTB"
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},
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{
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"PublicDescription": "Predictable branch speculatively executed, unpredicted",
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"EventCode": "0x115",
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"EventName": "BPU_BRANCH_NO_HIT",
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"BriefDescription": "Predictable branch speculatively executed, unpredicted"
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},
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{
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"PublicDescription": "Predictable branch speculatively executed that hit any level of BTB that mispredict",
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"EventCode": "0x116",
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"EventName": "BPU_HIT_BTB_AND_MISPREDICT",
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"BriefDescription": "Predictable branch speculatively executed that hit any level of BTB that mispredict"
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},
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{
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"PublicDescription": "Predictable conditional branch speculatively executed that hit any level of BTB that (direction) mispredict",
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"EventCode": "0x117",
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"EventName": "BPU_CONDITIONAL_BRANCH_HIT_BTB_AND_MISPREDICT",
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"BriefDescription": "Predictable conditional branch speculatively executed that hit any level of BTB that (direction) mispredict"
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},
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{
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"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor that mispredict",
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"EventCode": "0x118",
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"EventName": "BPU_INDIRECT_BRANCH_HIT_BTB_AND_MISPREDICT",
|
||||
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor that mispredict"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor that mispredict",
|
||||
"EventCode": "0x119",
|
||||
"EventName": "BPU_HIT_RSB_AND_MISPREDICT",
|
||||
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor that mispredict"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the overflow/underflow return predictor that mispredict",
|
||||
"EventCode": "0x11a",
|
||||
"EventName": "BPU_MISS_RSB_AND_MISPREDICT",
|
||||
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the overflow/underflow return predictor that mispredict"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Predictable branch speculatively executed, unpredicted, that mispredict",
|
||||
"EventCode": "0x11b",
|
||||
"EventName": "BPU_NO_PREDICTION_MISPREDICT",
|
||||
"BriefDescription": "Predictable branch speculatively executed, unpredicted, that mispredict"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Preditable branch update the BTB region buffer entry",
|
||||
"EventCode": "0x11c",
|
||||
"EventName": "BPU_BTB_UPDATE",
|
||||
"BriefDescription": "Preditable branch update the BTB region buffer entry"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Count predict pipe stalls due to speculative return address predictor full",
|
||||
"EventCode": "0x11d",
|
||||
"EventName": "BPU_RSB_FULL_STALL",
|
||||
"BriefDescription": "Count predict pipe stalls due to speculative return address predictor full"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Macro-ops speculatively decoded",
|
||||
"EventCode": "0x11f",
|
||||
"EventName": "ICF_INST_SPEC_DECODE",
|
||||
"BriefDescription": "Macro-ops speculatively decoded"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Flushes",
|
||||
"EventCode": "0x120",
|
||||
"EventName": "GPC_FLUSH",
|
||||
"BriefDescription": "Flushes"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Flushes due to memory hazards",
|
||||
"EventCode": "0x121",
|
||||
"EventName": "GPC_FLUSH_MEM_FAULT",
|
||||
"BriefDescription": "Flushes due to memory hazards"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "ETM extout bit 0",
|
||||
"EventCode": "0x141",
|
||||
"EventName": "MSC_ETM_EXTOUT0",
|
||||
"BriefDescription": "ETM extout bit 0"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "ETM extout bit 1",
|
||||
"EventCode": "0x142",
|
||||
"EventName": "MSC_ETM_EXTOUT1",
|
||||
"BriefDescription": "ETM extout bit 1"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "ETM extout bit 2",
|
||||
"EventCode": "0x143",
|
||||
"EventName": "MSC_ETM_EXTOUT2",
|
||||
"BriefDescription": "ETM extout bit 2"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "ETM extout bit 3",
|
||||
"EventCode": "0x144",
|
||||
"EventName": "MSC_ETM_EXTOUT3",
|
||||
"BriefDescription": "ETM extout bit 3"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Bus request sn",
|
||||
"EventCode": "0x156",
|
||||
"EventName": "L2C_SNOOP",
|
||||
"BriefDescription": "Bus request sn"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "L2 TXDAT LCRD blocked",
|
||||
"EventCode": "0x169",
|
||||
"EventName": "L2C_DAT_CRD_STALL",
|
||||
"BriefDescription": "L2 TXDAT LCRD blocked"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "L2 TXRSP LCRD blocked",
|
||||
"EventCode": "0x16a",
|
||||
"EventName": "L2C_RSP_CRD_STALL",
|
||||
"BriefDescription": "L2 TXRSP LCRD blocked"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "L2 TXREQ LCRD blocked",
|
||||
"EventCode": "0x16b",
|
||||
"EventName": "L2C_REQ_CRD_STALL",
|
||||
"BriefDescription": "L2 TXREQ LCRD blocked"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Early mispredict",
|
||||
"EventCode": "0xD100",
|
||||
"EventName": "ICF_EARLY_MIS_PRED",
|
||||
"BriefDescription": "Early mispredict"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "FEQ full cycles",
|
||||
"EventCode": "0xD101",
|
||||
"EventName": "ICF_FEQ_FULL",
|
||||
"BriefDescription": "FEQ full cycles"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Instruction FIFO Full",
|
||||
"EventCode": "0xD102",
|
||||
"EventName": "ICF_INST_FIFO_FULL",
|
||||
"BriefDescription": "Instruction FIFO Full"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "L1I TLB miss",
|
||||
"EventCode": "0xD103",
|
||||
"EventName": "L1I_TLB_MISS",
|
||||
"BriefDescription": "L1I TLB miss"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "ICF sent 0 instructions to IDR this cycle",
|
||||
"EventCode": "0xD104",
|
||||
"EventName": "ICF_STALL",
|
||||
"BriefDescription": "ICF sent 0 instructions to IDR this cycle"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "PC FIFO Full",
|
||||
"EventCode": "0xD105",
|
||||
"EventName": "ICF_PC_FIFO_FULL",
|
||||
"BriefDescription": "PC FIFO Full"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Stall due to BOB ID",
|
||||
"EventCode": "0xD200",
|
||||
"EventName": "IDR_STALL_BOB_ID",
|
||||
"BriefDescription": "Stall due to BOB ID"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Dispatch stall due to LOB entries",
|
||||
"EventCode": "0xD201",
|
||||
"EventName": "IDR_STALL_LOB_ID",
|
||||
"BriefDescription": "Dispatch stall due to LOB entries"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Dispatch stall due to SOB entries",
|
||||
"EventCode": "0xD202",
|
||||
"EventName": "IDR_STALL_SOB_ID",
|
||||
"BriefDescription": "Dispatch stall due to SOB entries"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Dispatch stall due to IXU scheduler entries",
|
||||
"EventCode": "0xD203",
|
||||
"EventName": "IDR_STALL_IXU_SCHED",
|
||||
"BriefDescription": "Dispatch stall due to IXU scheduler entries"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Dispatch stall due to FSU scheduler entries",
|
||||
"EventCode": "0xD204",
|
||||
"EventName": "IDR_STALL_FSU_SCHED",
|
||||
"BriefDescription": "Dispatch stall due to FSU scheduler entries"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Dispatch stall due to ROB entries",
|
||||
"EventCode": "0xD205",
|
||||
"EventName": "IDR_STALL_ROB_ID",
|
||||
"BriefDescription": "Dispatch stall due to ROB entries"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Dispatch stall due to flush",
|
||||
"EventCode": "0xD206",
|
||||
"EventName": "IDR_STALL_FLUSH",
|
||||
"BriefDescription": "Dispatch stall due to flush"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Dispatch stall due to WFI",
|
||||
"EventCode": "0xD207",
|
||||
"EventName": "IDR_STALL_WFI",
|
||||
"BriefDescription": "Dispatch stall due to WFI"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of SWOB drains triggered by timeout",
|
||||
"EventCode": "0xD208",
|
||||
"EventName": "IDR_STALL_SWOB_TIMEOUT",
|
||||
"BriefDescription": "Number of SWOB drains triggered by timeout"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of SWOB drains triggered by system register or special-purpose register read-after-write or specific special-purpose register writes that cause SWOB drain",
|
||||
"EventCode": "0xD209",
|
||||
"EventName": "IDR_STALL_SWOB_RAW",
|
||||
"BriefDescription": "Number of SWOB drains triggered by system register or special-purpose register read-after-write or specific special-purpose register writes that cause SWOB drain"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of SWOB drains triggered by system register write when SWOB full",
|
||||
"EventCode": "0xD20A",
|
||||
"EventName": "IDR_STALL_SWOB_FULL",
|
||||
"BriefDescription": "Number of SWOB drains triggered by system register write when SWOB full"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Dispatch stall due to L1 instruction cache miss",
|
||||
"EventCode": "0xD20B",
|
||||
"EventName": "STALL_FRONTEND_CACHE",
|
||||
"BriefDescription": "Dispatch stall due to L1 instruction cache miss"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Dispatch stall due to L1 data cache miss",
|
||||
"EventCode": "0xD20D",
|
||||
"EventName": "STALL_BACKEND_CACHE",
|
||||
"BriefDescription": "Dispatch stall due to L1 data cache miss"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Dispatch stall due to lack of any core resource",
|
||||
"EventCode": "0xD20F",
|
||||
"EventName": "STALL_BACKEND_RESOURCE",
|
||||
"BriefDescription": "Dispatch stall due to lack of any core resource"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Instructions issued by the scheduler",
|
||||
"EventCode": "0xD300",
|
||||
"EventName": "IXU_NUM_UOPS_ISSUED",
|
||||
"BriefDescription": "Instructions issued by the scheduler"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Any uop issued was canceled for any reason",
|
||||
"EventCode": "0xD301",
|
||||
"EventName": "IXU_ISSUE_CANCEL",
|
||||
"BriefDescription": "Any uop issued was canceled for any reason"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "A load wakeup to the scheduler has been canceled",
|
||||
"EventCode": "0xD302",
|
||||
"EventName": "IXU_LOAD_CANCEL",
|
||||
"BriefDescription": "A load wakeup to the scheduler has been canceled"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "The scheduler had to cancel one slow Uop due to resource conflict",
|
||||
"EventCode": "0xD303",
|
||||
"EventName": "IXU_SLOW_CANCEL",
|
||||
"BriefDescription": "The scheduler had to cancel one slow Uop due to resource conflict"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Uops issued by the scheduler on IXA",
|
||||
"EventCode": "0xD304",
|
||||
"EventName": "IXU_IXA_ISSUED",
|
||||
"BriefDescription": "Uops issued by the scheduler on IXA"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Uops issued by the scheduler on IXA Par 0",
|
||||
"EventCode": "0xD305",
|
||||
"EventName": "IXU_IXA_PAR0_ISSUED",
|
||||
"BriefDescription": "Uops issued by the scheduler on IXA Par 0"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Uops issued by the scheduler on IXA Par 1",
|
||||
"EventCode": "0xD306",
|
||||
"EventName": "IXU_IXA_PAR1_ISSUED",
|
||||
"BriefDescription": "Uops issued by the scheduler on IXA Par 1"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Uops issued by the scheduler on IXB",
|
||||
"EventCode": "0xD307",
|
||||
"EventName": "IXU_IXB_ISSUED",
|
||||
"BriefDescription": "Uops issued by the scheduler on IXB"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Uops issued by the scheduler on IXB Par 0",
|
||||
"EventCode": "0xD308",
|
||||
"EventName": "IXU_IXB_PAR0_ISSUED",
|
||||
"BriefDescription": "Uops issued by the scheduler on IXB Par 0"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Uops issued by the scheduler on IXB Par 1",
|
||||
"EventCode": "0xD309",
|
||||
"EventName": "IXU_IXB_PAR1_ISSUED",
|
||||
"BriefDescription": "Uops issued by the scheduler on IXB Par 1"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Uops issued by the scheduler on IXC",
|
||||
"EventCode": "0xD30A",
|
||||
"EventName": "IXU_IXC_ISSUED",
|
||||
"BriefDescription": "Uops issued by the scheduler on IXC"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Uops issued by the scheduler on IXC Par 0",
|
||||
"EventCode": "0xD30B",
|
||||
"EventName": "IXU_IXC_PAR0_ISSUED",
|
||||
"BriefDescription": "Uops issued by the scheduler on IXC Par 0"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Uops issued by the scheduler on IXC Par 1",
|
||||
"EventCode": "0xD30C",
|
||||
"EventName": "IXU_IXC_PAR1_ISSUED",
|
||||
"BriefDescription": "Uops issued by the scheduler on IXC Par 1"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Uops issued by the scheduler on IXD",
|
||||
"EventCode": "0xD30D",
|
||||
"EventName": "IXU_IXD_ISSUED",
|
||||
"BriefDescription": "Uops issued by the scheduler on IXD"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Uops issued by the scheduler on IXD Par 0",
|
||||
"EventCode": "0xD30E",
|
||||
"EventName": "IXU_IXD_PAR0_ISSUED",
|
||||
"BriefDescription": "Uops issued by the scheduler on IXD Par 0"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Uops issued by the scheduler on IXD Par 1",
|
||||
"EventCode": "0xD30F",
|
||||
"EventName": "IXU_IXD_PAR1_ISSUED",
|
||||
"BriefDescription": "Uops issued by the scheduler on IXD Par 1"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Uops issued by the FSU scheduler",
|
||||
"EventCode": "0xD400",
|
||||
"EventName": "FSU_ISSUED",
|
||||
"BriefDescription": "Uops issued by the FSU scheduler"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Uops issued by the scheduler on FSX",
|
||||
"EventCode": "0xD401",
|
||||
"EventName": "FSU_FSX_ISSUED",
|
||||
"BriefDescription": "Uops issued by the scheduler on FSX"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Uops issued by the scheduler on FSY",
|
||||
"EventCode": "0xD402",
|
||||
"EventName": "FSU_FSY_ISSUED",
|
||||
"BriefDescription": "Uops issued by the scheduler on FSY"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Uops issued by the scheduler on FSZ",
|
||||
"EventCode": "0xD403",
|
||||
"EventName": "FSU_FSZ_ISSUED",
|
||||
"BriefDescription": "Uops issued by the scheduler on FSZ"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Uops canceled (load cancels)",
|
||||
"EventCode": "0xD404",
|
||||
"EventName": "FSU_CANCEL",
|
||||
"BriefDescription": "Uops canceled (load cancels)"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Count scheduler stalls due to divide/sqrt",
|
||||
"EventCode": "0xD405",
|
||||
"EventName": "FSU_DIV_SQRT_STALL",
|
||||
"BriefDescription": "Count scheduler stalls due to divide/sqrt"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of SWOB drains",
|
||||
"EventCode": "0xD500",
|
||||
"EventName": "GPC_SWOB_DRAIN",
|
||||
"BriefDescription": "Number of SWOB drains"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "GPC detected a Breakpoint instruction match",
|
||||
"EventCode": "0xD501",
|
||||
"EventName": "BREAKPOINT_MATCH",
|
||||
"BriefDescription": "GPC detected a Breakpoint instruction match"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Core progress monitor triggered",
|
||||
"EventCode": "0xd502",
|
||||
"EventName": "GPC_CPM_TRIGGER",
|
||||
"BriefDescription": "Core progress monitor triggered"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Fill buffer full",
|
||||
"EventCode": "0xD601",
|
||||
"EventName": "OFB_FULL",
|
||||
"BriefDescription": "Fill buffer full"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Load satisified from store forwarded data",
|
||||
"EventCode": "0xD605",
|
||||
"EventName": "LD_FROM_ST_FWD",
|
||||
"BriefDescription": "Load satisified from store forwarded data"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Store retirement pipe stall",
|
||||
"EventCode": "0xD60C",
|
||||
"EventName": "LSU_ST_RETIRE_STALL",
|
||||
"BriefDescription": "Store retirement pipe stall"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "LSU detected a Watchpoint data match",
|
||||
"EventCode": "0xD60D",
|
||||
"EventName": "WATCHPOINT_MATCH",
|
||||
"BriefDescription": "LSU detected a Watchpoint data match"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Counts cycles that MSC is telling GPC to stall commit due to ETM ISTALL feature",
|
||||
"EventCode": "0xda00",
|
||||
"EventName": "MSC_ETM_COMMIT_STALL",
|
||||
"BriefDescription": "Counts cycles that MSC is telling GPC to stall commit due to ETM ISTALL feature"
|
||||
}
|
||||
]
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
[
|
||||
{
|
||||
"ArchStdEvent": "EXC_UNDEF"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "EXC_SVC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "EXC_PABORT"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "EXC_DABORT"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "EXC_IRQ"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "EXC_FIQ"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "EXC_HVC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "EXC_TRAP_PABORT"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "EXC_TRAP_DABORT"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "EXC_TRAP_OTHER"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "EXC_TRAP_IRQ"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "EXC_TRAP_FIQ"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "EXC_TAKEN"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "EXC_RETURN"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "EXC_SMC"
|
||||
}
|
||||
]
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
[
|
||||
{
|
||||
"ArchStdEvent": "SW_INCR"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "ST_RETIRED"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "LD_SPEC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "ST_SPEC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "LDST_SPEC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "DP_SPEC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "ASE_SPEC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "VFP_SPEC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "PC_WRITE_SPEC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "BR_IMMED_RETIRED"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "BR_RETURN_RETIRED"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "CRYPTO_SPEC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "ISB_SPEC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "DSB_SPEC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "DMB_SPEC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "RC_LD_SPEC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "RC_ST_SPEC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "INST_RETIRED"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "CID_WRITE_RETIRED"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "PC_WRITE_RETIRED"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "INST_SPEC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "TTBR_WRITE_RETIRED"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "BR_RETIRED"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "BR_MIS_PRED_RETIRED"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "OP_RETIRED"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "OP_SPEC"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Operation speculatively executed - ASE Scalar",
|
||||
"EventCode": "0xd210",
|
||||
"EventName": "ASE_SCALAR_SPEC",
|
||||
"BriefDescription": "Operation speculatively executed - ASE Scalar"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Operation speculatively executed - ASE Vector",
|
||||
"EventCode": "0xd211",
|
||||
"EventName": "ASE_VECTOR_SPEC",
|
||||
"BriefDescription": "Operation speculatively executed - ASE Vector"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Barrier speculatively executed, CSDB",
|
||||
"EventCode": "0x7f",
|
||||
"EventName": "CSDB_SPEC",
|
||||
"BriefDescription": "Barrier speculatively executed, CSDB"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Prefetch sent to L2.",
|
||||
"EventCode": "0xd106",
|
||||
"EventName": "ICF_PREFETCH_DISPATCH",
|
||||
"BriefDescription": "Prefetch sent to L2."
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Prefetch response received but was dropped since we don't support inflight upgrades.",
|
||||
"EventCode": "0xd107",
|
||||
"EventName": "ICF_PREFETCH_DROPPED_NO_UPGRADE",
|
||||
"BriefDescription": "Prefetch response received but was dropped since we don't support inflight upgrades."
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Prefetch request missed TLB.",
|
||||
"EventCode": "0xd108",
|
||||
"EventName": "ICF_PREFETCH_DROPPED_TLB_MISS",
|
||||
"BriefDescription": "Prefetch request missed TLB."
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Prefetch request dropped since duplicate was found in TLB.",
|
||||
"EventCode": "0xd109",
|
||||
"EventName": "ICF_PREFETCH_DROPPED_DUPLICATE",
|
||||
"BriefDescription": "Prefetch request dropped since duplicate was found in TLB."
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Prefetch request dropped since it was found in cache.",
|
||||
"EventCode": "0xd10a",
|
||||
"EventName": "ICF_PREFETCH_DROPPED_CACHE_HIT",
|
||||
"BriefDescription": "Prefetch request dropped since it was found in cache."
|
||||
}
|
||||
]
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
[
|
||||
{
|
||||
"ArchStdEvent": "LDREX_SPEC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "STREX_PASS_SPEC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "STREX_FAIL_SPEC"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "STREX_SPEC"
|
||||
}
|
||||
]
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
[
|
||||
{
|
||||
"ArchStdEvent": "LD_RETIRED"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "MEM_ACCESS_RD"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "MEM_ACCESS_WR"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "LD_ALIGN_LAT"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "ST_ALIGN_LAT"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "MEM_ACCESS"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "MEMORY_ERROR"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "LDST_ALIGN_LAT"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "MEM_ACCESS_CHECKED"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "MEM_ACCESS_CHECKED_RD"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "MEM_ACCESS_CHECKED_WR"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Flushes due to memory hazards",
|
||||
"EventCode": "0x121",
|
||||
"EventName": "BPU_FLUSH_MEM_FAULT",
|
||||
"BriefDescription": "Flushes due to memory hazards"
|
||||
}
|
||||
]
|
||||
442
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json
Normal file
442
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json
Normal file
|
|
@ -0,0 +1,442 @@
|
|||
[
|
||||
{
|
||||
"MetricName": "branch_miss_pred_rate",
|
||||
"MetricExpr": "BR_MIS_PRED / BR_PRED",
|
||||
"BriefDescription": "Branch predictor misprediction rate. May not count branches that are never resolved because they are in the misprediction shadow of an earlier branch",
|
||||
"MetricGroup": "branch",
|
||||
"ScaleUnit": "100%"
|
||||
},
|
||||
{
|
||||
"MetricName": "bus_utilization",
|
||||
"MetricExpr": "BUS_ACCESS / (BUS_CYCLES * 1)",
|
||||
"BriefDescription": "Core-to-uncore bus utilization",
|
||||
"MetricGroup": "Bus",
|
||||
"ScaleUnit": "100percent of bus cycles"
|
||||
},
|
||||
{
|
||||
"MetricName": "l1d_cache_miss_ratio",
|
||||
"MetricExpr": "L1D_CACHE_REFILL / L1D_CACHE",
|
||||
"BriefDescription": "This metric measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gives an indication of the effectiveness of the level 1 data cache.",
|
||||
"MetricGroup": "Miss_Ratio;L1D_Cache_Effectiveness",
|
||||
"ScaleUnit": "1per cache access"
|
||||
},
|
||||
{
|
||||
"MetricName": "l1i_cache_miss_ratio",
|
||||
"MetricExpr": "L1I_CACHE_REFILL / L1I_CACHE",
|
||||
"BriefDescription": "This metric measures the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesses. This gives an indication of the effectiveness of the level 1 instruction cache.",
|
||||
"MetricGroup": "Miss_Ratio;L1I_Cache_Effectiveness",
|
||||
"ScaleUnit": "1per cache access"
|
||||
},
|
||||
{
|
||||
"MetricName": "Miss_Ratio;l1d_cache_read_miss",
|
||||
"MetricExpr": "L1D_CACHE_LMISS_RD / L1D_CACHE_RD",
|
||||
"BriefDescription": "L1D cache read miss rate",
|
||||
"MetricGroup": "Cache",
|
||||
"ScaleUnit": "1per cache read access"
|
||||
},
|
||||
{
|
||||
"MetricName": "l2_cache_miss_ratio",
|
||||
"MetricExpr": "L2D_CACHE_REFILL / L2D_CACHE",
|
||||
"BriefDescription": "This metric measures the ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives an indication of the effectiveness of the level 2 cache, which is a unified cache that stores both data and instruction. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.",
|
||||
"MetricGroup": "Miss_Ratio;L2_Cache_Effectiveness",
|
||||
"ScaleUnit": "1per cache access"
|
||||
},
|
||||
{
|
||||
"MetricName": "l1i_cache_read_miss_rate",
|
||||
"MetricExpr": "L1I_CACHE_LMISS / L1I_CACHE",
|
||||
"BriefDescription": "L1I cache read miss rate",
|
||||
"MetricGroup": "Cache",
|
||||
"ScaleUnit": "1per cache access"
|
||||
},
|
||||
{
|
||||
"MetricName": "l2d_cache_read_miss_rate",
|
||||
"MetricExpr": "L2D_CACHE_LMISS_RD / L2D_CACHE_RD",
|
||||
"BriefDescription": "L2 cache read miss rate",
|
||||
"MetricGroup": "Cache",
|
||||
"ScaleUnit": "1per cache read access"
|
||||
},
|
||||
{
|
||||
"MetricName": "l1d_cache_miss_mpki",
|
||||
"MetricExpr": "(L1D_CACHE_LMISS_RD * 1e3) / INST_RETIRED",
|
||||
"BriefDescription": "Misses per thousand instructions (data)",
|
||||
"MetricGroup": "Cache",
|
||||
"ScaleUnit": "1MPKI"
|
||||
},
|
||||
{
|
||||
"MetricName": "l1i_cache_miss_mpki",
|
||||
"MetricExpr": "(L1I_CACHE_LMISS * 1e3) / INST_RETIRED",
|
||||
"BriefDescription": "Misses per thousand instructions (instruction)",
|
||||
"MetricGroup": "Cache",
|
||||
"ScaleUnit": "1MPKI"
|
||||
},
|
||||
{
|
||||
"MetricName": "simd_percentage",
|
||||
"MetricExpr": "ASE_SPEC / INST_SPEC",
|
||||
"BriefDescription": "This metric measures advanced SIMD operations as a percentage of total operations speculatively executed.",
|
||||
"MetricGroup": "Operation_Mix",
|
||||
"ScaleUnit": "100percent of operations"
|
||||
},
|
||||
{
|
||||
"MetricName": "crypto_percentage",
|
||||
"MetricExpr": "CRYPTO_SPEC / INST_SPEC",
|
||||
"BriefDescription": "This metric measures crypto operations as a percentage of operations speculatively executed.",
|
||||
"MetricGroup": "Operation_Mix",
|
||||
"ScaleUnit": "100percent of operations"
|
||||
},
|
||||
{
|
||||
"MetricName": "gflops",
|
||||
"MetricExpr": "VFP_SPEC / (duration_time * 1e9)",
|
||||
"BriefDescription": "Giga-floating point operations per second",
|
||||
"MetricGroup": "InstructionMix"
|
||||
},
|
||||
{
|
||||
"MetricName": "integer_dp_percentage",
|
||||
"MetricExpr": "DP_SPEC / INST_SPEC",
|
||||
"BriefDescription": "This metric measures scalar integer operations as a percentage of operations speculatively executed.",
|
||||
"MetricGroup": "Operation_Mix",
|
||||
"ScaleUnit": "100percent of operations"
|
||||
},
|
||||
{
|
||||
"MetricName": "ipc",
|
||||
"MetricExpr": "INST_RETIRED / CPU_CYCLES",
|
||||
"BriefDescription": "This metric measures the number of instructions retired per cycle.",
|
||||
"MetricGroup": "General",
|
||||
"ScaleUnit": "1per cycle"
|
||||
},
|
||||
{
|
||||
"MetricName": "load_percentage",
|
||||
"MetricExpr": "LD_SPEC / INST_SPEC",
|
||||
"BriefDescription": "This metric measures load operations as a percentage of operations speculatively executed.",
|
||||
"MetricGroup": "Operation_Mix",
|
||||
"ScaleUnit": "100percent of operations"
|
||||
},
|
||||
{
|
||||
"MetricName": "load_store_spec_rate",
|
||||
"MetricExpr": "LDST_SPEC / INST_SPEC",
|
||||
"BriefDescription": "The rate of load or store instructions speculatively executed to overall instructions speclatively executed",
|
||||
"MetricGroup": "Operation_Mix",
|
||||
"ScaleUnit": "100percent of operations"
|
||||
},
|
||||
{
|
||||
"MetricName": "retired_mips",
|
||||
"MetricExpr": "INST_RETIRED / (duration_time * 1e6)",
|
||||
"BriefDescription": "Millions of instructions per second",
|
||||
"MetricGroup": "InstructionMix"
|
||||
},
|
||||
{
|
||||
"MetricName": "spec_utilization_mips",
|
||||
"MetricExpr": "INST_SPEC / (duration_time * 1e6)",
|
||||
"BriefDescription": "Millions of instructions per second",
|
||||
"MetricGroup": "PEutilization"
|
||||
},
|
||||
{
|
||||
"MetricName": "pc_write_spec_rate",
|
||||
"MetricExpr": "PC_WRITE_SPEC / INST_SPEC",
|
||||
"BriefDescription": "The rate of software change of the PC speculatively executed to overall instructions speclatively executed",
|
||||
"MetricGroup": "Operation_Mix",
|
||||
"ScaleUnit": "100percent of operations"
|
||||
},
|
||||
{
|
||||
"MetricName": "store_percentage",
|
||||
"MetricExpr": "ST_SPEC / INST_SPEC",
|
||||
"BriefDescription": "This metric measures store operations as a percentage of operations speculatively executed.",
|
||||
"MetricGroup": "Operation_Mix",
|
||||
"ScaleUnit": "100percent of operations"
|
||||
},
|
||||
{
|
||||
"MetricName": "scalar_fp_percentage",
|
||||
"MetricExpr": "VFP_SPEC / INST_SPEC",
|
||||
"BriefDescription": "This metric measures scalar floating point operations as a percentage of operations speculatively executed.",
|
||||
"MetricGroup": "Operation_Mix",
|
||||
"ScaleUnit": "100percent of operations"
|
||||
},
|
||||
{
|
||||
"MetricName": "retired_rate",
|
||||
"MetricExpr": "OP_RETIRED / OP_SPEC",
|
||||
"BriefDescription": "Of all the micro-operations issued, what percentage are retired(committed)",
|
||||
"MetricGroup": "General",
|
||||
"ScaleUnit": "100%"
|
||||
},
|
||||
{
|
||||
"MetricName": "wasted",
|
||||
"MetricExpr": "1 - (OP_RETIRED / (CPU_CYCLES * #slots))",
|
||||
"BriefDescription": "Of all the micro-operations issued, what proportion are lost",
|
||||
"MetricGroup": "General",
|
||||
"ScaleUnit": "100%"
|
||||
},
|
||||
{
|
||||
"MetricName": "wasted_rate",
|
||||
"MetricExpr": "1 - OP_RETIRED / OP_SPEC",
|
||||
"BriefDescription": "Of all the micro-operations issued, what percentage are not retired(committed)",
|
||||
"MetricGroup": "General",
|
||||
"ScaleUnit": "100%"
|
||||
},
|
||||
{
|
||||
"MetricName": "stall_backend_cache_rate",
|
||||
"MetricExpr": "STALL_BACKEND_CACHE / CPU_CYCLES",
|
||||
"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and cache miss",
|
||||
"MetricGroup": "Stall",
|
||||
"ScaleUnit": "100percent of cycles"
|
||||
},
|
||||
{
|
||||
"MetricName": "stall_backend_resource_rate",
|
||||
"MetricExpr": "STALL_BACKEND_RESOURCE / CPU_CYCLES",
|
||||
"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and resource full",
|
||||
"MetricGroup": "Stall",
|
||||
"ScaleUnit": "100percent of cycles"
|
||||
},
|
||||
{
|
||||
"MetricName": "stall_backend_tlb_rate",
|
||||
"MetricExpr": "STALL_BACKEND_TLB / CPU_CYCLES",
|
||||
"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and TLB miss",
|
||||
"MetricGroup": "Stall",
|
||||
"ScaleUnit": "100percent of cycles"
|
||||
},
|
||||
{
|
||||
"MetricName": "stall_frontend_cache_rate",
|
||||
"MetricExpr": "STALL_FRONTEND_CACHE / CPU_CYCLES",
|
||||
"BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and cache miss",
|
||||
"MetricGroup": "Stall",
|
||||
"ScaleUnit": "100percent of cycles"
|
||||
},
|
||||
{
|
||||
"MetricName": "stall_frontend_tlb_rate",
|
||||
"MetricExpr": "STALL_FRONTEND_TLB / CPU_CYCLES",
|
||||
"BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and TLB miss",
|
||||
"MetricGroup": "Stall",
|
||||
"ScaleUnit": "100percent of cycles"
|
||||
},
|
||||
{
|
||||
"MetricName": "dtlb_walk_ratio",
|
||||
"MetricExpr": "DTLB_WALK / L1D_TLB",
|
||||
"BriefDescription": "This metric measures the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication of the effectiveness of the data TLB accesses.",
|
||||
"MetricGroup": "Miss_Ratio;DTLB_Effectiveness",
|
||||
"ScaleUnit": "1per TLB access"
|
||||
},
|
||||
{
|
||||
"MetricName": "itlb_walk_ratio",
|
||||
"MetricExpr": "ITLB_WALK / L1I_TLB",
|
||||
"BriefDescription": "This metric measures the ratio of instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication of the effectiveness of the instruction TLB accesses.",
|
||||
"MetricGroup": "Miss_Ratio;ITLB_Effectiveness",
|
||||
"ScaleUnit": "1per TLB access"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "backend_bound"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "frontend_bound",
|
||||
"MetricExpr": "100 - (retired_fraction + slots_lost_misspeculation_fraction + backend_bound)"
|
||||
},
|
||||
{
|
||||
"MetricName": "slots_lost_misspeculation_fraction",
|
||||
"MetricExpr": "(OP_SPEC - OP_RETIRED) / (CPU_CYCLES * #slots)",
|
||||
"BriefDescription": "Fraction of slots lost due to misspeculation",
|
||||
"DefaultMetricgroupName": "TopdownL1",
|
||||
"MetricGroup": "Default;TopdownL1",
|
||||
"ScaleUnit": "100percent of slots"
|
||||
},
|
||||
{
|
||||
"MetricName": "retired_fraction",
|
||||
"MetricExpr": "OP_RETIRED / (CPU_CYCLES * #slots)",
|
||||
"BriefDescription": "Fraction of slots retiring, useful work",
|
||||
"DefaultMetricgroupName": "TopdownL1",
|
||||
"MetricGroup": "Default;TopdownL1",
|
||||
"ScaleUnit": "100percent of slots"
|
||||
},
|
||||
{
|
||||
"MetricName": "backend_core",
|
||||
"MetricExpr": "(backend_bound / 100) - backend_memory",
|
||||
"BriefDescription": "Fraction of slots the CPU was stalled due to backend non-memory subsystem issues",
|
||||
"MetricGroup": "TopdownL2",
|
||||
"ScaleUnit": "100%"
|
||||
},
|
||||
{
|
||||
"MetricName": "backend_memory",
|
||||
"MetricExpr": "(STALL_BACKEND_TLB + STALL_BACKEND_CACHE) / CPU_CYCLES",
|
||||
"BriefDescription": "Fraction of slots the CPU was stalled due to backend memory subsystem issues (cache/tlb miss)",
|
||||
"MetricGroup": "TopdownL2",
|
||||
"ScaleUnit": "100%"
|
||||
},
|
||||
{
|
||||
"MetricName": "branch_mispredict",
|
||||
"MetricExpr": "(BR_MIS_PRED_RETIRED / GPC_FLUSH) * slots_lost_misspeculation_fraction",
|
||||
"BriefDescription": "Fraction of slots lost due to branch misprediciton",
|
||||
"MetricGroup": "TopdownL2",
|
||||
"ScaleUnit": "1percent of slots"
|
||||
},
|
||||
{
|
||||
"MetricName": "frontend_bandwidth",
|
||||
"MetricExpr": "frontend_bound - frontend_latency",
|
||||
"BriefDescription": "Fraction of slots the CPU did not dispatch at full bandwidth - able to dispatch partial slots only (1, 2, or 3 uops)",
|
||||
"MetricGroup": "TopdownL2",
|
||||
"ScaleUnit": "1percent of slots"
|
||||
},
|
||||
{
|
||||
"MetricName": "frontend_latency",
|
||||
"MetricExpr": "(STALL_FRONTEND - ((STALL_SLOT_FRONTEND - ((frontend_bound / 100) * CPU_CYCLES * #slots)) / #slots)) / CPU_CYCLES",
|
||||
"BriefDescription": "Fraction of slots the CPU was stalled due to frontend latency issues (cache/tlb miss); nothing to dispatch",
|
||||
"MetricGroup": "TopdownL2",
|
||||
"ScaleUnit": "100percent of slots"
|
||||
},
|
||||
{
|
||||
"MetricName": "other_miss_pred",
|
||||
"MetricExpr": "slots_lost_misspeculation_fraction - branch_mispredict",
|
||||
"BriefDescription": "Fraction of slots lost due to other/non-branch misprediction misspeculation",
|
||||
"MetricGroup": "TopdownL2",
|
||||
"ScaleUnit": "1percent of slots"
|
||||
},
|
||||
{
|
||||
"MetricName": "pipe_utilization",
|
||||
"MetricExpr": "100 * ((IXU_NUM_UOPS_ISSUED + FSU_ISSUED) / (CPU_CYCLES * 6))",
|
||||
"BriefDescription": "Fraction of execute slots utilized",
|
||||
"MetricGroup": "TopdownL2",
|
||||
"ScaleUnit": "1percent of slots"
|
||||
},
|
||||
{
|
||||
"MetricName": "d_cache_l2_miss_rate",
|
||||
"MetricExpr": "STALL_BACKEND_MEM / CPU_CYCLES",
|
||||
"BriefDescription": "Fraction of cycles the CPU was stalled due to data L2 cache miss",
|
||||
"MetricGroup": "TopdownL3",
|
||||
"ScaleUnit": "100percent of cycles"
|
||||
},
|
||||
{
|
||||
"MetricName": "d_cache_miss_rate",
|
||||
"MetricExpr": "STALL_BACKEND_CACHE / CPU_CYCLES",
|
||||
"BriefDescription": "Fraction of cycles the CPU was stalled due to data cache miss",
|
||||
"MetricGroup": "TopdownL3",
|
||||
"ScaleUnit": "100percent of cycles"
|
||||
},
|
||||
{
|
||||
"MetricName": "d_tlb_miss_rate",
|
||||
"MetricExpr": "STALL_BACKEND_TLB / CPU_CYCLES",
|
||||
"BriefDescription": "Fraction of cycles the CPU was stalled due to data TLB miss",
|
||||
"MetricGroup": "TopdownL3",
|
||||
"ScaleUnit": "100percent of cycles"
|
||||
},
|
||||
{
|
||||
"MetricName": "fsu_pipe_utilization",
|
||||
"MetricExpr": "FSU_ISSUED / (CPU_CYCLES * 2)",
|
||||
"BriefDescription": "Fraction of FSU execute slots utilized",
|
||||
"MetricGroup": "TopdownL3",
|
||||
"ScaleUnit": "100percent of slots"
|
||||
},
|
||||
{
|
||||
"MetricName": "i_cache_miss_rate",
|
||||
"MetricExpr": "STALL_FRONTEND_CACHE / CPU_CYCLES",
|
||||
"BriefDescription": "Fraction of cycles the CPU was stalled due to instruction cache miss",
|
||||
"MetricGroup": "TopdownL3",
|
||||
"ScaleUnit": "100percent of slots"
|
||||
},
|
||||
{
|
||||
"MetricName": "i_tlb_miss_rate",
|
||||
"MetricExpr": "STALL_FRONTEND_TLB / CPU_CYCLES",
|
||||
"BriefDescription": "Fraction of cycles the CPU was stalled due to instruction TLB miss",
|
||||
"MetricGroup": "TopdownL3",
|
||||
"ScaleUnit": "100percent of slots"
|
||||
},
|
||||
{
|
||||
"MetricName": "ixu_pipe_utilization",
|
||||
"MetricExpr": "IXU_NUM_UOPS_ISSUED / (CPU_CYCLES * #slots)",
|
||||
"BriefDescription": "Fraction of IXU execute slots utilized",
|
||||
"MetricGroup": "TopdownL3",
|
||||
"ScaleUnit": "100percent of slots"
|
||||
},
|
||||
{
|
||||
"MetricName": "stall_recovery_rate",
|
||||
"MetricExpr": "IDR_STALL_FLUSH / CPU_CYCLES",
|
||||
"BriefDescription": "Fraction of cycles the CPU was stalled due to flush recovery",
|
||||
"MetricGroup": "TopdownL3",
|
||||
"ScaleUnit": "100percent of slots"
|
||||
},
|
||||
{
|
||||
"MetricName": "stall_fsu_sched_rate",
|
||||
"MetricExpr": "IDR_STALL_FSU_SCHED / CPU_CYCLES",
|
||||
"BriefDescription": "Fraction of cycles the CPU was stalled and FSU was full",
|
||||
"MetricGroup": "TopdownL4",
|
||||
"ScaleUnit": "100percent of cycles"
|
||||
},
|
||||
{
|
||||
"MetricName": "stall_ixu_sched_rate",
|
||||
"MetricExpr": "IDR_STALL_IXU_SCHED / CPU_CYCLES",
|
||||
"BriefDescription": "Fraction of cycles the CPU was stalled and IXU was full",
|
||||
"MetricGroup": "TopdownL4",
|
||||
"ScaleUnit": "100percent of cycles"
|
||||
},
|
||||
{
|
||||
"MetricName": "stall_lob_id_rate",
|
||||
"MetricExpr": "IDR_STALL_LOB_ID / CPU_CYCLES",
|
||||
"BriefDescription": "Fraction of cycles the CPU was stalled and LOB was full",
|
||||
"MetricGroup": "TopdownL4",
|
||||
"ScaleUnit": "100percent of cycles"
|
||||
},
|
||||
{
|
||||
"MetricName": "stall_rob_id_rate",
|
||||
"MetricExpr": "IDR_STALL_ROB_ID / CPU_CYCLES",
|
||||
"BriefDescription": "Fraction of cycles the CPU was stalled and ROB was full",
|
||||
"MetricGroup": "TopdownL4",
|
||||
"ScaleUnit": "100percent of cycles"
|
||||
},
|
||||
{
|
||||
"MetricName": "stall_sob_id_rate",
|
||||
"MetricExpr": "IDR_STALL_SOB_ID / CPU_CYCLES",
|
||||
"BriefDescription": "Fraction of cycles the CPU was stalled and SOB was full",
|
||||
"MetricGroup": "TopdownL4",
|
||||
"ScaleUnit": "100percent of cycles"
|
||||
},
|
||||
{
|
||||
"MetricName": "l1d_cache_access_demand",
|
||||
"MetricExpr": "L1D_CACHE_RW / L1D_CACHE",
|
||||
"BriefDescription": "L1D cache access - demand",
|
||||
"MetricGroup": "Cache",
|
||||
"ScaleUnit": "100percent of cache acceses"
|
||||
},
|
||||
{
|
||||
"MetricName": "l1d_cache_access_prefetces",
|
||||
"MetricExpr": "L1D_CACHE_PRFM / L1D_CACHE",
|
||||
"BriefDescription": "L1D cache access - prefetch",
|
||||
"MetricGroup": "Cache",
|
||||
"ScaleUnit": "100percent of cache acceses"
|
||||
},
|
||||
{
|
||||
"MetricName": "l1d_cache_demand_misses",
|
||||
"MetricExpr": "L1D_CACHE_REFILL_RW / L1D_CACHE",
|
||||
"BriefDescription": "L1D cache demand misses",
|
||||
"MetricGroup": "Cache",
|
||||
"ScaleUnit": "100percent of cache acceses"
|
||||
},
|
||||
{
|
||||
"MetricName": "l1d_cache_demand_misses_read",
|
||||
"MetricExpr": "L1D_CACHE_REFILL_RD / L1D_CACHE",
|
||||
"BriefDescription": "L1D cache demand misses - read",
|
||||
"MetricGroup": "Cache",
|
||||
"ScaleUnit": "100percent of cache acceses"
|
||||
},
|
||||
{
|
||||
"MetricName": "l1d_cache_demand_misses_write",
|
||||
"MetricExpr": "L1D_CACHE_REFILL_WR / L1D_CACHE",
|
||||
"BriefDescription": "L1D cache demand misses - write",
|
||||
"MetricGroup": "Cache",
|
||||
"ScaleUnit": "100percent of cache acceses"
|
||||
},
|
||||
{
|
||||
"MetricName": "l1d_cache_prefetch_misses",
|
||||
"MetricExpr": "L1D_CACHE_REFILL_PRFM / L1D_CACHE",
|
||||
"BriefDescription": "L1D cache prefetch misses",
|
||||
"MetricGroup": "Cache",
|
||||
"ScaleUnit": "100percent of cache acceses"
|
||||
},
|
||||
{
|
||||
"MetricName": "ase_scalar_mix",
|
||||
"MetricExpr": "ASE_SCALAR_SPEC / OP_SPEC",
|
||||
"BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) scalar operations",
|
||||
"MetricGroup": "Instructions",
|
||||
"ScaleUnit": "100percent of cache acceses"
|
||||
},
|
||||
{
|
||||
"MetricName": "ase_vector_mix",
|
||||
"MetricExpr": "ASE_VECTOR_SPEC / OP_SPEC",
|
||||
"BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) vector operations",
|
||||
"MetricGroup": "Instructions",
|
||||
"ScaleUnit": "100percent of cache acceses"
|
||||
}
|
||||
]
|
||||
170
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/mmu.json
Normal file
170
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/mmu.json
Normal file
|
|
@ -0,0 +1,170 @@
|
|||
[
|
||||
{
|
||||
"PublicDescription": "Level 2 data translation buffer allocation",
|
||||
"EventCode": "0xD800",
|
||||
"EventName": "MMU_D_OTB_ALLOC",
|
||||
"BriefDescription": "Level 2 data translation buffer allocation"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Data TLB translation cache hit on S1L2 walk cache entry",
|
||||
"EventCode": "0xd801",
|
||||
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L2_WALK",
|
||||
"BriefDescription": "Data TLB translation cache hit on S1L2 walk cache entry"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Data TLB translation cache hit on S1L1 walk cache entry",
|
||||
"EventCode": "0xd802",
|
||||
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L1_WALK",
|
||||
"BriefDescription": "Data TLB translation cache hit on S1L1 walk cache entry"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Data TLB translation cache hit on S1L0 walk cache entry",
|
||||
"EventCode": "0xd803",
|
||||
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L0_WALK",
|
||||
"BriefDescription": "Data TLB translation cache hit on S1L0 walk cache entry"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Data TLB translation cache hit on S2L2 walk cache entry",
|
||||
"EventCode": "0xd804",
|
||||
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L2_WALK",
|
||||
"BriefDescription": "Data TLB translation cache hit on S2L2 walk cache entry"
|
||||
},
|
||||
{
|
||||
"PublicDescrition": "Data TLB translation cache hit on S2L1 walk cache entry",
|
||||
"EventCode": "0xd805",
|
||||
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L1_WALK",
|
||||
"BriefDescription": "Data TLB translation cache hit on S2L1 walk cache entry"
|
||||
},
|
||||
{
|
||||
"PublicDescrition": "Data TLB translation cache hit on S2L0 walk cache entry",
|
||||
"EventCode": "0xd806",
|
||||
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L0_WALK",
|
||||
"BriefDescription": "Data TLB translation cache hit on S2L0 walk cache entry"
|
||||
},
|
||||
{
|
||||
"PublicDescrition": "Data-side S1 page walk cache lookup",
|
||||
"EventCode": "0xd807",
|
||||
"EventName": "MMU_D_S1_WALK_CACHE_LOOKUP",
|
||||
"BriefDescription": "Data-side S1 page walk cache lookup"
|
||||
},
|
||||
{
|
||||
"PublicDescrition": "Data-side S1 page walk cache refill",
|
||||
"EventCode": "0xd808",
|
||||
"EventName": "MMU_D_S1_WALK_CACHE_REFILL",
|
||||
"BriefDescription": "Data-side S1 page walk cache refill"
|
||||
},
|
||||
{
|
||||
"PublicDescrition": "Data-side S2 page walk cache lookup",
|
||||
"EventCode": "0xd809",
|
||||
"EventName": "MMU_D_S2_WALK_CACHE_LOOKUP",
|
||||
"BriefDescription": "Data-side S2 page walk cache lookup"
|
||||
},
|
||||
{
|
||||
"PublicDescrition": "Data-side S2 page walk cache refill",
|
||||
"EventCode": "0xd80a",
|
||||
"EventName": "MMU_D_S2_WALK_CACHE_REFILL",
|
||||
"BriefDescription": "Data-side S2 page walk cache refill"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Data-side S1 table walk fault",
|
||||
"EventCode": "0xD80B",
|
||||
"EventName": "MMU_D_S1_WALK_FAULT",
|
||||
"BriefDescription": "Data-side S1 table walk fault"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Data-side S2 table walk fault",
|
||||
"EventCode": "0xD80C",
|
||||
"EventName": "MMU_D_S2_WALK_FAULT",
|
||||
"BriefDescription": "Data-side S2 table walk fault"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Data-side table walk steps or descriptor fetches",
|
||||
"EventCode": "0xD80D",
|
||||
"EventName": "MMU_D_WALK_STEPS",
|
||||
"BriefDescription": "Data-side table walk steps or descriptor fetches"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Level 2 instruction translation buffer allocation",
|
||||
"EventCode": "0xD900",
|
||||
"EventName": "MMU_I_OTB_ALLOC",
|
||||
"BriefDescription": "Level 2 instruction translation buffer allocation"
|
||||
},
|
||||
{
|
||||
"PublicDescrition": "Instruction TLB translation cache hit on S1L2 walk cache entry",
|
||||
"EventCode": "0xd901",
|
||||
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L2_WALK",
|
||||
"BriefDescription": "Instruction TLB translation cache hit on S1L2 walk cache entry"
|
||||
},
|
||||
{
|
||||
"PublicDescrition": "Instruction TLB translation cache hit on S1L1 walk cache entry",
|
||||
"EventCode": "0xd902",
|
||||
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L1_WALK",
|
||||
"BriefDescription": "Instruction TLB translation cache hit on S1L1 walk cache entry"
|
||||
},
|
||||
{
|
||||
"PublicDescrition": "Instruction TLB translation cache hit on S1L0 walk cache entry",
|
||||
"EventCode": "0xd903",
|
||||
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L0_WALK",
|
||||
"BriefDescription": "Instruction TLB translation cache hit on S1L0 walk cache entry"
|
||||
},
|
||||
{
|
||||
"PublicDescrition": "Instruction TLB translation cache hit on S2L2 walk cache entry",
|
||||
"EventCode": "0xd904",
|
||||
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L2_WALK",
|
||||
"BriefDescription": "Instruction TLB translation cache hit on S2L2 walk cache entry"
|
||||
},
|
||||
{
|
||||
"PublicDescrition": "Instruction TLB translation cache hit on S2L1 walk cache entry",
|
||||
"EventCode": "0xd905",
|
||||
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L1_WALK",
|
||||
"BriefDescription": "Instruction TLB translation cache hit on S2L1 walk cache entry"
|
||||
},
|
||||
{
|
||||
"PublicDescrition": "Instruction TLB translation cache hit on S2L0 walk cache entry",
|
||||
"EventCode": "0xd906",
|
||||
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L0_WALK",
|
||||
"BriefDescription": "Instruction TLB translation cache hit on S2L0 walk cache entry"
|
||||
},
|
||||
{
|
||||
"PublicDescrition": "Instruction-side S1 page walk cache lookup",
|
||||
"EventCode": "0xd907",
|
||||
"EventName": "MMU_I_S1_WALK_CACHE_LOOKUP",
|
||||
"BriefDescription": "Instruction-side S1 page walk cache lookup"
|
||||
},
|
||||
{
|
||||
"PublicDescrition": "Instruction-side S1 page walk cache refill",
|
||||
"EventCode": "0xd908",
|
||||
"EventName": "MMU_I_S1_WALK_CACHE_REFILL",
|
||||
"BriefDescription": "Instruction-side S1 page walk cache refill"
|
||||
},
|
||||
{
|
||||
"PublicDescrition": "Instruction-side S2 page walk cache lookup",
|
||||
"EventCode": "0xd909",
|
||||
"EventName": "MMU_I_S2_WALK_CACHE_LOOKUP",
|
||||
"BriefDescription": "Instruction-side S2 page walk cache lookup"
|
||||
},
|
||||
{
|
||||
"PublicDescrition": "Instruction-side S2 page walk cache refill",
|
||||
"EventCode": "0xd90a",
|
||||
"EventName": "MMU_I_S2_WALK_CACHE_REFILL",
|
||||
"BriefDescription": "Instruction-side S2 page walk cache refill"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Instruction-side S1 table walk fault",
|
||||
"EventCode": "0xD90B",
|
||||
"EventName": "MMU_I_S1_WALK_FAULT",
|
||||
"BriefDescription": "Instruction-side S1 table walk fault"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Instruction-side S2 table walk fault",
|
||||
"EventCode": "0xD90C",
|
||||
"EventName": "MMU_I_S2_WALK_FAULT",
|
||||
"BriefDescription": "Instruction-side S2 table walk fault"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Instruction-side table walk steps or descriptor fetches",
|
||||
"EventCode": "0xD90D",
|
||||
"EventName": "MMU_I_WALK_STEPS",
|
||||
"BriefDescription": "Instruction-side table walk steps or descriptor fetches"
|
||||
}
|
||||
]
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
[
|
||||
{
|
||||
"ArchStdEvent": "STALL_FRONTEND",
|
||||
"Errata": "Errata AC03_CPU_29",
|
||||
"BriefDescription": "Impacted by errata, use metrics instead -"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "STALL_BACKEND"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "STALL",
|
||||
"Errata": "Errata AC03_CPU_29",
|
||||
"BriefDescription": "Impacted by errata, use metrics instead -"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "STALL_SLOT_BACKEND"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "STALL_SLOT_FRONTEND",
|
||||
"Errata": "Errata AC03_CPU_29",
|
||||
"BriefDescription": "Impacted by errata, use metrics instead -"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "STALL_SLOT"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "STALL_BACKEND_MEM"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Frontend stall cycles, TLB",
|
||||
"EventCode": "0x815c",
|
||||
"EventName": "STALL_FRONTEND_TLB",
|
||||
"BriefDescription": "Frontend stall cycles, TLB"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Backend stall cycles, TLB",
|
||||
"EventCode": "0x8167",
|
||||
"EventName": "STALL_BACKEND_TLB",
|
||||
"BriefDescription": "Backend stall cycles, TLB"
|
||||
}
|
||||
]
|
||||
14
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/spe.json
Normal file
14
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/spe.json
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
[
|
||||
{
|
||||
"ArchStdEvent": "SAMPLE_POP"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "SAMPLE_FEED"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "SAMPLE_FILTRATE"
|
||||
},
|
||||
{
|
||||
"ArchStdEvent": "SAMPLE_COLLISION"
|
||||
}
|
||||
]
|
||||
|
|
@ -42,3 +42,4 @@
|
|||
0x00000000480fd010,v1,hisilicon/hip08,core
|
||||
0x00000000500f0000,v1,ampere/emag,core
|
||||
0x00000000c00fac30,v1,ampere/ampereone,core
|
||||
0x00000000c00fac40,v1,ampere/ampereonex,core
|
||||
|
|
|
|||
|
Loading…
Reference in New Issue
Block a user