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ARM development updates for v6.12-rc1
- clean up TTBCR magic numbers and use u32 for this register - fix clang issue in VFP code leading to kernel oops, caused by compiler instruction scheduling. - switch 32-bit Arm to use GENERIC_CPU_DEVICES and use the arch_cpu_is_hotpluggable() hook. - pass struct device to arm_iommu_create_mapping() and move over to use iommu_paging_domain_alloc() rather than iommu_domain_alloc() - make amba_bustype constant -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEuNNh8scc2k/wOAE+9OeQG+StrGQFAmbZziAACgkQ9OeQG+St rGRC4g//WolL3+djg71a1uDj4X3XjuDStlCoj2WVrOqmoQ57BcNR+yR/H89tXtNa kWypAr6GZP9aFIS1Liprce2ypnsbNTKZjOnU4zqTiG9XTq5ddBvGw71RiA74R8Gt hDt27XpvzwAmkoLiTRK9KPrHUFRAL6jj++lq9HJBnHzIV2VD4wlUHt4P535Wn26p IO2vBWIHxsE/OBprO92nMeEskDHj3bwHGMBMdogz4mQvoet55m9q1JLtWlc5Fb5j yrHPoZ/4kYyu8ReIZMvudULMvg9XwF8LT4ferwk7qrKj/aua0xglK3h6FBzKj0EU Tsp9ic2TwVoDFg9xoV9US7+axVikxN6ZgVCqlGUZ+0jDArHlskV++cncsqfAxLw1 ga4Tb9JG3oPAj+SThLgsk8PzKK+RWXpW+n4DQsgJaI7iJhSyB6mLFwr5fud3j3mZ pMVMeXAh3GVjcdfwDtWmrUmwSLh9KMaOLIKCQm4ooL3ELVsa+UUbEHLb71ZKMa8T /H9bNkABhJHqTk7T2tBIVKV/hSnHddjg2lGLOppuo5z3DKYi6oIlbBcqBSqz69PK afkSrhWk8u7tvHI31uY9qncyjY8mQPkvXu1mYxz9t0D3w/+YM5ts45y4bLUg5wMr 8eSkmFPVBQWqeQurs490YwVcmGNL9v4gSsArI7RJzvxnj9UUVVY= =hhvp -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rmk/linux Pull ARM updates from Russell King: - clean up TTBCR magic numbers and use u32 for this register - fix clang issue in VFP code leading to kernel oops, caused by compiler instruction scheduling. - switch 32-bit Arm to use GENERIC_CPU_DEVICES and use the arch_cpu_is_hotpluggable() hook. - pass struct device to arm_iommu_create_mapping() and move over to use iommu_paging_domain_alloc() rather than iommu_domain_alloc() - make amba_bustype constant * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rmk/linux: ARM: 9418/1: dma-mapping: Use iommu_paging_domain_alloc() ARM: 9417/1: dma-mapping: Pass device to arm_iommu_create_mapping() ARM: 9416/1: amba: make amba_bustype constant ARM: 9412/1: Convert to arch_cpu_is_hotpluggable() ARM: 9411/1: Switch over to GENERIC_CPU_DEVICES using arch_register_cpu() ARM: 9410/1: vfp: Use asm volatile in fmrx/fmxr macros ARM: 9409/1: mmu: Do not use magic number for TTBCR settings
This commit is contained in:
commit
1636f57c78
@ -64,6 +64,7 @@ config ARM
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select GENERIC_CLOCKEVENTS_BROADCAST if SMP
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select GENERIC_IRQ_IPI if SMP
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select GENERIC_CPU_AUTOPROBE
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select GENERIC_CPU_DEVICES
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select GENERIC_EARLY_IOREMAP
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select GENERIC_IDLE_POLL_SETUP
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select GENERIC_IRQ_MULTI_HANDLER
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@ -11,7 +11,6 @@
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#include <linux/cpu.h>
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struct cpuinfo_arm {
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struct cpu cpu;
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u32 cpuid;
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#ifdef CONFIG_SMP
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unsigned int loops_per_jiffy;
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@ -24,7 +24,7 @@ struct dma_iommu_mapping {
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};
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struct dma_iommu_mapping *
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arm_iommu_create_mapping(const struct bus_type *bus, dma_addr_t base, u64 size);
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arm_iommu_create_mapping(struct device *dev, dma_addr_t base, u64 size);
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void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping);
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@ -106,6 +106,11 @@
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/*
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* TTBCR register bits.
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*
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* The ORGN0 and IRGN0 bits enables different forms of caching when
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* walking the translation table. Clearing these bits (which is claimed
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* to be the reset default) means "normal memory, [outer|inner]
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* non-cacheable"
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*/
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#define TTBCR_EAE (1 << 31)
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#define TTBCR_IMP (1 << 30)
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@ -1201,20 +1201,10 @@ void __init setup_arch(char **cmdline_p)
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mdesc->init_early();
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}
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static int __init topology_init(void)
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bool arch_cpu_is_hotpluggable(int num)
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{
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int cpu;
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for_each_possible_cpu(cpu) {
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struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu);
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cpuinfo->cpu.hotpluggable = platform_can_hotplug_cpu(cpu);
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register_cpu(&cpuinfo->cpu, cpu);
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}
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return 0;
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return platform_can_hotplug_cpu(num);
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}
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subsys_initcall(topology_init);
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#ifdef CONFIG_HAVE_PROC_CPU
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static int __init proc_cpu_init(void)
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@ -1532,7 +1532,7 @@ static const struct dma_map_ops iommu_ops = {
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/**
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* arm_iommu_create_mapping
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* @bus: pointer to the bus holding the client device (for IOMMU calls)
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* @dev: pointer to the client device (for IOMMU calls)
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* @base: start address of the valid IO address space
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* @size: maximum size of the valid IO address space
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*
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@ -1544,7 +1544,7 @@ static const struct dma_map_ops iommu_ops = {
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* arm_iommu_attach_device function.
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*/
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struct dma_iommu_mapping *
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arm_iommu_create_mapping(const struct bus_type *bus, dma_addr_t base, u64 size)
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arm_iommu_create_mapping(struct device *dev, dma_addr_t base, u64 size)
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{
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unsigned int bits = size >> PAGE_SHIFT;
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unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long);
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@ -1585,9 +1585,11 @@ arm_iommu_create_mapping(const struct bus_type *bus, dma_addr_t base, u64 size)
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spin_lock_init(&mapping->lock);
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mapping->domain = iommu_domain_alloc(bus);
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if (!mapping->domain)
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mapping->domain = iommu_paging_domain_alloc(dev);
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if (IS_ERR(mapping->domain)) {
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err = PTR_ERR(mapping->domain);
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goto err4;
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}
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kref_init(&mapping->kref);
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return mapping;
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@ -1718,7 +1720,7 @@ static void arm_setup_iommu_dma_ops(struct device *dev)
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dma_base = dma_range_map_min(dev->dma_range_map);
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size = dma_range_map_max(dev->dma_range_map) - dma_base;
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}
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mapping = arm_iommu_create_mapping(dev->bus, dma_base, size);
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mapping = arm_iommu_create_mapping(dev, dma_base, size);
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if (IS_ERR(mapping)) {
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pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n",
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size, dev_name(dev));
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@ -1638,7 +1638,7 @@ static void __init early_paging_init(const struct machine_desc *mdesc)
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{
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pgtables_remap *lpae_pgtables_remap;
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unsigned long pa_pgd;
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unsigned int cr, ttbcr;
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u32 cr, ttbcr, tmp;
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long long offset;
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if (!mdesc->pv_fixup)
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@ -1688,7 +1688,9 @@ static void __init early_paging_init(const struct machine_desc *mdesc)
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cr = get_cr();
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set_cr(cr & ~(CR_I | CR_C));
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ttbcr = cpu_get_ttbcr();
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cpu_set_ttbcr(ttbcr & ~(3 << 8 | 3 << 10));
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/* Disable all kind of caching of the translation table */
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tmp = ttbcr & ~(TTBCR_ORGN0_MASK | TTBCR_IRGN0_MASK);
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cpu_set_ttbcr(tmp);
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flush_cache_all();
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/*
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@ -64,33 +64,37 @@
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#ifdef CONFIG_AS_VFP_VMRS_FPINST
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#define fmrx(_vfp_) ({ \
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u32 __v; \
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asm(".fpu vfpv2\n" \
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"vmrs %0, " #_vfp_ \
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: "=r" (__v) : : "cc"); \
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__v; \
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})
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#define fmrx(_vfp_) ({ \
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u32 __v; \
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asm volatile (".fpu vfpv2\n" \
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"vmrs %0, " #_vfp_ \
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: "=r" (__v) : : "cc"); \
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__v; \
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})
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#define fmxr(_vfp_,_var_) \
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asm(".fpu vfpv2\n" \
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"vmsr " #_vfp_ ", %0" \
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: : "r" (_var_) : "cc")
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#define fmxr(_vfp_, _var_) ({ \
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asm volatile (".fpu vfpv2\n" \
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"vmsr " #_vfp_ ", %0" \
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: : "r" (_var_) : "cc"); \
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})
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#else
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#define vfpreg(_vfp_) #_vfp_
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#define fmrx(_vfp_) ({ \
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u32 __v; \
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asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \
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: "=r" (__v) : : "cc"); \
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__v; \
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})
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#define fmrx(_vfp_) ({ \
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u32 __v; \
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asm volatile ("mrc p10, 7, %0, " vfpreg(_vfp_) "," \
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"cr0, 0 @ fmrx %0, " #_vfp_ \
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: "=r" (__v) : : "cc"); \
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__v; \
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})
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#define fmxr(_vfp_,_var_) \
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asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
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: : "r" (_var_) : "cc")
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#define fmxr(_vfp_, _var_) ({ \
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asm volatile ("mcr p10, 7, %0, " vfpreg(_vfp_) "," \
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"cr0, 0 @ fmxr " #_vfp_ ", %0" \
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: : "r" (_var_) : "cc"); \
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})
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#endif
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@ -435,7 +435,7 @@ static const struct dev_pm_ops amba_pm = {
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* DMA configuration for platform and AMBA bus is same. So here we reuse
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* platform's DMA config routine.
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*/
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struct bus_type amba_bustype = {
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const struct bus_type amba_bustype = {
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.name = "amba",
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.dev_groups = amba_dev_groups,
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.match = amba_match,
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@ -110,7 +110,7 @@ int exynos_drm_register_dma(struct drm_device *drm, struct device *dev,
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void *mapping = NULL;
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if (IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU))
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mapping = arm_iommu_create_mapping(&platform_bus_type,
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mapping = arm_iommu_create_mapping(dev,
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EXYNOS_DEV_ADDR_START, EXYNOS_DEV_ADDR_SIZE);
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else if (IS_ENABLED(CONFIG_IOMMU_DMA))
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mapping = iommu_get_domain_for_dev(priv->dma_dev);
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@ -804,8 +804,7 @@ static int ipmmu_init_arm_mapping(struct device *dev)
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if (!mmu->mapping) {
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struct dma_iommu_mapping *mapping;
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mapping = arm_iommu_create_mapping(&platform_bus_type,
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SZ_1G, SZ_2G);
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mapping = arm_iommu_create_mapping(dev, SZ_1G, SZ_2G);
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if (IS_ERR(mapping)) {
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dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n");
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ret = PTR_ERR(mapping);
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@ -433,8 +433,7 @@ static int mtk_iommu_v1_create_mapping(struct device *dev,
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mtk_mapping = data->mapping;
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if (!mtk_mapping) {
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/* MTK iommu support 4GB iova address space. */
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mtk_mapping = arm_iommu_create_mapping(&platform_bus_type,
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0, 1ULL << 32);
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mtk_mapping = arm_iommu_create_mapping(dev, 0, 1ULL << 32);
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if (IS_ERR(mtk_mapping))
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return PTR_ERR(mtk_mapping);
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@ -1965,7 +1965,7 @@ static int isp_attach_iommu(struct isp_device *isp)
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* Create the ARM mapping, used by the ARM DMA mapping core to allocate
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* VAs. This will allocate a corresponding IOMMU domain.
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*/
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mapping = arm_iommu_create_mapping(&platform_bus_type, SZ_1G, SZ_2G);
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mapping = arm_iommu_create_mapping(isp->dev, SZ_1G, SZ_2G);
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if (IS_ERR(mapping)) {
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dev_err(isp->dev, "failed to create ARM IOMMU mapping\n");
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return PTR_ERR(mapping);
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@ -105,7 +105,7 @@ enum amba_vendor {
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AMBA_VENDOR_LSI = 0xb6,
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};
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extern struct bus_type amba_bustype;
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extern const struct bus_type amba_bustype;
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#define to_amba_device(d) container_of_const(d, struct amba_device, dev)
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