ARM: tegra: core SoC code changes for 3.18

the primary change here gets its address information from DT rather than
 iomap.h. This removes one more user of iomap.h, and will help allow the
 code to move to a location that can be shared between arch/arm and
 arch/arm64.
 
 An unused header file was also removed.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUGxmUAAoJEMzrak5tbycxh8gP/AraovjYUwxHfFDkRgRn/Ukb
 t8PRy/mieHwypO86Rseu4x5P+OWO3MFMYLfqFpJZAYugwq7hgB6dCCcFuezqDP0k
 HVBBQN1wu8XDpjJd260EQmzjx8mqW+omMmeWZcZSMChnqPsntVpCmbWf4dlGoAcY
 qgGfiNVZ7QWsS7ROjGD9JI0SmkYdfoXWtPX6r0z93sn3SM4lrJeIs/RGYKfEaQb0
 JXvJChj/K59Z8ejUjM5pI2CkC0Y23ftl5BH6sJk9yiFRA09UDahdUJiO1wcM0TgK
 oukVFOapGyGscFrN/bZq79RPde1P0GnbllcT0aOV5PWr4R6HGEArxrsVm7UoC+L3
 3J3OwpG5EokCOh7Agt81ExTP6uaohWZKC4WS8l247qbDXhdxIXscmTk9Y3Fey//x
 UM044kprNgUaRiQ/fFFx8W+6V3dHthCD6TslNCN8E0s1yjqgw8lLyuW0YqaO+CJe
 q3+d8Twf2d8GUwOPmh2hSYh1kGt47YNQvrQ+bkdb9FFOtkrrYZykPSDI71H/IpIR
 wrmHiueQV1zu6f4KRCgYgg5SQj/SI9rncoI1innarw+JszSK5Pn8fKp+z9mTRDML
 oaSCSKc9UNMVAMfex1p1GYgxuVbCQex6VHFTRXke99CJA7nedRzhB6v8wk7ICdXP
 pb3AeTLB4R1rr7Ull1mt
 =BeSe
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-3.18-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc

Pull "ARM: tegra: core SoC code changes for 3.18" from Stephen Warren:

the primary change here gets its address information from DT rather than
iomap.h. This removes one more user of iomap.h, and will help allow the
code to move to a location that can be shared between arch/arm and
arch/arm64.

An unused header file was also removed.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

* tag 'tegra-for-3.18-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
  ARM: tegra: remove unused tegra_emc.h
  ARM: tegra: Initialize flow controller from DT
  of: Add NVIDIA Tegra flow controller bindings

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt

@@ -0,0 +1,12 @@
+NVIDIA Tegra Flow Controller
+
+Required properties:
+- compatible: Should be "nvidia,tegra<chip>-flowctrl"
+- reg: Should contain one register range (address and length)
+
+Example:
+
+	flow-controller@60007000 {
+		compatible = "nvidia,tegra20-flowctrl";
+		reg = <0x60007000 0x1000>;
+	};

arch/arm/mach-tegra/flowctrl.c

@@ -22,11 +22,12 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <soc/tegra/fuse.h>
 
 #include "flowctrl.h"
-#include "iomap.h"
 
 static u8 flowctrl_offset_halt_cpu[] = {
 	FLOW_CTRL_HALT_CPU0_EVENTS,
@@ -42,23 +43,22 @@ static u8 flowctrl_offset_cpu_csr[] = {
 	FLOW_CTRL_CPU1_CSR + 16,
 };
 
+static void __iomem *tegra_flowctrl_base;
+
 static void flowctrl_update(u8 offset, u32 value)
 {
-	void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
-
-	writel(value, addr);
+	writel(value, tegra_flowctrl_base + offset);
 
 	/* ensure the update has reached the flow controller */
 	wmb();
-	readl_relaxed(addr);
+	readl_relaxed(tegra_flowctrl_base + offset);
 }
 
 u32 flowctrl_read_cpu_csr(unsigned int cpuid)
 {
 	u8 offset = flowctrl_offset_cpu_csr[cpuid];
-	void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
 
-	return readl(addr);
+	return readl(tegra_flowctrl_base + offset);
 }
 
 void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
@@ -139,3 +139,33 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
 	reg |= FLOW_CTRL_CSR_EVENT_FLAG;		/* clear event */
 	flowctrl_write_cpu_csr(cpuid, reg);
 }
+
+static const struct of_device_id matches[] __initconst = {
+	{ .compatible = "nvidia,tegra124-flowctrl" },
+	{ .compatible = "nvidia,tegra114-flowctrl" },
+	{ .compatible = "nvidia,tegra30-flowctrl" },
+	{ .compatible = "nvidia,tegra20-flowctrl" },
+	{ }
+};
+
+void __init tegra_flowctrl_init(void)
+{
+	/* hardcoded fallback if device tree node is missing */
+	unsigned long base = 0x60007000;
+	unsigned long size = SZ_4K;
+	struct device_node *np;
+
+	np = of_find_matching_node(NULL, matches);
+	if (np) {
+		struct resource res;
+
+		if (of_address_to_resource(np, 0, &res) == 0) {
+			size = resource_size(&res);
+			base = res.start;
+		}
+
+		of_node_put(np);
+	}
+
+	tegra_flowctrl_base = ioremap_nocache(base, size);
+}

arch/arm/mach-tegra/flowctrl.h

@@ -59,6 +59,8 @@ void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
 
 void flowctrl_cpu_suspend_enter(unsigned int cpuid);
 void flowctrl_cpu_suspend_exit(unsigned int cpuid);
+
+void tegra_flowctrl_init(void);
 #endif
 
 #endif

arch/arm/mach-tegra/tegra.c

@@ -48,6 +48,7 @@
 #include "board.h"
 #include "common.h"
 #include "cpuidle.h"
+#include "flowctrl.h"
 #include "iomap.h"
 #include "irq.h"
 #include "pm.h"
@@ -74,6 +75,7 @@ static void __init tegra_init_early(void)
 {
 	of_register_trusted_foundations();
 	tegra_cpu_reset_handler_init();
+	tegra_flowctrl_init();
 }
 
 static void __init tegra_dt_init_irq(void)

include/linux/platform_data/tegra_emc.h

@@ -1,34 +0,0 @@
-/*
- * Copyright (C) 2011 Google, Inc.
- *
- * Author:
- *	Colin Cross <ccross@android.com>
- *	Olof Johansson <olof@lixom.net>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __TEGRA_EMC_H_
-#define __TEGRA_EMC_H_
-
-#define TEGRA_EMC_NUM_REGS 46
-
-struct tegra_emc_table {
-	unsigned long rate;
-	u32 regs[TEGRA_EMC_NUM_REGS];
-};
-
-struct tegra_emc_pdata {
-	int num_tables;
-	struct tegra_emc_table *tables;
-};
-
-#endif