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bpf: Add x86-64 JIT support for bpf_addr_space_cast instruction.
LLVM generates bpf_addr_space_cast instruction while translating pointers between native (zero) address space and __attribute__((address_space(N))). The addr_space=1 is reserved as bpf_arena address space. rY = addr_space_cast(rX, 0, 1) is processed by the verifier and converted to normal 32-bit move: wX = wY rY = addr_space_cast(rX, 1, 0) has to be converted by JIT: aux_reg = upper_32_bits of arena->user_vm_start aux_reg <<= 32 wX = wY // clear upper 32 bits of dst register if (wX) // if not zero add upper bits of user_vm_start wX |= aux_reg JIT can do it more efficiently: mov dst_reg32, src_reg32 // 32-bit move shl dst_reg, 32 or dst_reg, user_vm_start rol dst_reg, 32 xor r11, r11 test dst_reg32, dst_reg32 // check if lower 32-bit are zero cmove r11, dst_reg // if so, set dst_reg to zero // Intel swapped src/dst register encoding in CMOVcc Signed-off-by: Alexei Starovoitov <ast@kernel.org> Signed-off-by: Andrii Nakryiko <andrii@kernel.org> Acked-by: Eduard Zingerman <eddyz87@gmail.com> Link: https://lore.kernel.org/bpf/20240308010812.89848-5-alexei.starovoitov@gmail.com
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@ -1276,13 +1276,14 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image
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bool tail_call_seen = false;
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bool seen_exit = false;
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u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
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u64 arena_vm_start;
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u64 arena_vm_start, user_vm_start;
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int i, excnt = 0;
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int ilen, proglen = 0;
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u8 *prog = temp;
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int err;
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arena_vm_start = bpf_arena_get_kern_vm_start(bpf_prog->aux->arena);
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user_vm_start = bpf_arena_get_user_vm_start(bpf_prog->aux->arena);
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detect_reg_usage(insn, insn_cnt, callee_regs_used,
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&tail_call_seen);
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@ -1350,6 +1351,40 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image
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break;
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case BPF_ALU64 | BPF_MOV | BPF_X:
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if (insn->off == BPF_ADDR_SPACE_CAST &&
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insn->imm == 1U << 16) {
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if (dst_reg != src_reg)
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/* 32-bit mov */
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emit_mov_reg(&prog, false, dst_reg, src_reg);
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/* shl dst_reg, 32 */
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maybe_emit_1mod(&prog, dst_reg, true);
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EMIT3(0xC1, add_1reg(0xE0, dst_reg), 32);
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/* or dst_reg, user_vm_start */
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maybe_emit_1mod(&prog, dst_reg, true);
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if (is_axreg(dst_reg))
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EMIT1_off32(0x0D, user_vm_start >> 32);
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else
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EMIT2_off32(0x81, add_1reg(0xC8, dst_reg), user_vm_start >> 32);
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/* rol dst_reg, 32 */
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maybe_emit_1mod(&prog, dst_reg, true);
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EMIT3(0xC1, add_1reg(0xC0, dst_reg), 32);
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/* xor r11, r11 */
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EMIT3(0x4D, 0x31, 0xDB);
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/* test dst_reg32, dst_reg32; check if lower 32-bit are zero */
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maybe_emit_mod(&prog, dst_reg, dst_reg, false);
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EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg));
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/* cmove r11, dst_reg; if so, set dst_reg to zero */
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/* WARNING: Intel swapped src/dst register encoding in CMOVcc !!! */
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maybe_emit_mod(&prog, AUX_REG, dst_reg, true);
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EMIT3(0x0F, 0x44, add_2reg(0xC0, AUX_REG, dst_reg));
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break;
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}
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fallthrough;
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case BPF_ALU | BPF_MOV | BPF_X:
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if (insn->off == 0)
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emit_mov_reg(&prog,
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@ -3432,6 +3467,11 @@ void bpf_arch_poke_desc_update(struct bpf_jit_poke_descriptor *poke,
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}
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}
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bool bpf_jit_supports_arena(void)
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{
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return true;
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}
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bool bpf_jit_supports_ptr_xchg(void)
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{
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return true;
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@ -962,6 +962,7 @@ bool bpf_jit_supports_kfunc_call(void);
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bool bpf_jit_supports_far_kfunc_call(void);
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bool bpf_jit_supports_exceptions(void);
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bool bpf_jit_supports_ptr_xchg(void);
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bool bpf_jit_supports_arena(void);
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void arch_bpf_stack_walk(bool (*consume_fn)(void *cookie, u64 ip, u64 sp, u64 bp), void *cookie);
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bool bpf_helper_changes_pkt_data(void *func);
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@ -2932,6 +2932,11 @@ bool __weak bpf_jit_supports_far_kfunc_call(void)
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return false;
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}
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bool __weak bpf_jit_supports_arena(void)
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{
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return false;
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}
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/* Return TRUE if the JIT backend satisfies the following two conditions:
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* 1) JIT backend supports atomic_xchg() on pointer-sized words.
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* 2) Under the specific arch, the implementation of xchg() is the same
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