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thermal: arm: dra752: Remove all TSHUT related definitions
No configuration needs to be done for TSHUT from software. Hence remove all the unnecessary definitions. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
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@ -54,7 +54,6 @@
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#define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8
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#define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154
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#define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac
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#define DRA752_BANDGAP_TSHUT_CORE_OFFSET 0x1b8
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#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET 0x1c4
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#define DRA752_DTEMP_CORE_0_OFFSET 0x208
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#define DRA752_DTEMP_CORE_1_OFFSET 0x20c
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@ -66,7 +65,6 @@
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#define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET 0x388
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#define DRA752_TEMP_SENSOR_IVA_OFFSET 0x398
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#define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET 0x3a4
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#define DRA752_BANDGAP_TSHUT_IVA_OFFSET 0x3ac
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#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET 0x3b4
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#define DRA752_DTEMP_IVA_0_OFFSET 0x3d0
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#define DRA752_DTEMP_IVA_1_OFFSET 0x3d4
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@ -78,7 +76,6 @@
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#define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET 0x4
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#define DRA752_TEMP_SENSOR_MPU_OFFSET 0x14c
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#define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET 0x1a4
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#define DRA752_BANDGAP_TSHUT_MPU_OFFSET 0x1b0
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#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET 0x1bc
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#define DRA752_DTEMP_MPU_0_OFFSET 0x1e0
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#define DRA752_DTEMP_MPU_1_OFFSET 0x1e4
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@ -90,7 +87,6 @@
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#define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET 0x384
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#define DRA752_TEMP_SENSOR_DSPEVE_OFFSET 0x394
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#define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET 0x3a0
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#define DRA752_BANDGAP_TSHUT_DSPEVE_OFFSET 0x3a8
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#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET 0x3b0
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#define DRA752_DTEMP_DSPEVE_0_OFFSET 0x3bc
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#define DRA752_DTEMP_DSPEVE_1_OFFSET 0x3c0
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@ -102,7 +98,6 @@
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#define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET 0x0
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#define DRA752_TEMP_SENSOR_GPU_OFFSET 0x150
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#define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET 0x1a8
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#define DRA752_BANDGAP_TSHUT_GPU_OFFSET 0x1b4
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#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET 0x1c0
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#define DRA752_DTEMP_GPU_0_OFFSET 0x1f4
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#define DRA752_DTEMP_GPU_1_OFFSET 0x1f8
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@ -173,10 +168,6 @@
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#define DRA752_BANDGAP_THRESHOLD_HOT_MASK (0x3ff << 16)
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#define DRA752_BANDGAP_THRESHOLD_COLD_MASK (0x3ff << 0)
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/* DRA752.TSHUT_THRESHOLD */
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#define DRA752_TSHUT_THRESHOLD_MUXCTRL_MASK BIT(31)
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#define DRA752_TSHUT_THRESHOLD_HOT_MASK (0x3ff << 16)
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#define DRA752_TSHUT_THRESHOLD_COLD_MASK (0x3ff << 0)
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/* DRA752.BANDGAP_CUMUL_DTEMP_CORE */
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#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_MASK (0xffffffff << 0)
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@ -216,8 +207,6 @@
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#define DRA752_GPU_MAX_TEMP 125000
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#define DRA752_GPU_HYST_VAL 5000
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/* interrupts thresholds */
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#define DRA752_GPU_TSHUT_HOT 915
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#define DRA752_GPU_TSHUT_COLD 900
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#define DRA752_GPU_T_HOT 800
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#define DRA752_GPU_T_COLD 795
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@ -230,8 +219,6 @@
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#define DRA752_MPU_MAX_TEMP 125000
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#define DRA752_MPU_HYST_VAL 5000
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/* interrupts thresholds */
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#define DRA752_MPU_TSHUT_HOT 915
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#define DRA752_MPU_TSHUT_COLD 900
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#define DRA752_MPU_T_HOT 800
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#define DRA752_MPU_T_COLD 795
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@ -244,8 +231,6 @@
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#define DRA752_CORE_MAX_TEMP 125000
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#define DRA752_CORE_HYST_VAL 5000
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/* interrupts thresholds */
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#define DRA752_CORE_TSHUT_HOT 915
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#define DRA752_CORE_TSHUT_COLD 900
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#define DRA752_CORE_T_HOT 800
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#define DRA752_CORE_T_COLD 795
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@ -258,8 +243,6 @@
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#define DRA752_DSPEVE_MAX_TEMP 125000
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#define DRA752_DSPEVE_HYST_VAL 5000
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/* interrupts thresholds */
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#define DRA752_DSPEVE_TSHUT_HOT 915
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#define DRA752_DSPEVE_TSHUT_COLD 900
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#define DRA752_DSPEVE_T_HOT 800
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#define DRA752_DSPEVE_T_COLD 795
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@ -272,8 +255,6 @@
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#define DRA752_IVA_MAX_TEMP 125000
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#define DRA752_IVA_HYST_VAL 5000
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/* interrupts thresholds */
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#define DRA752_IVA_TSHUT_HOT 915
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#define DRA752_IVA_TSHUT_COLD 900
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#define DRA752_IVA_T_HOT 800
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#define DRA752_IVA_T_COLD 795
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@ -49,9 +49,6 @@ dra752_core_temp_sensor_registers = {
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.bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET,
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.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
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.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
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.tshut_threshold = DRA752_BANDGAP_TSHUT_CORE_OFFSET,
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.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
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.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
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.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
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.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
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.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK,
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@ -85,9 +82,6 @@ dra752_iva_temp_sensor_registers = {
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.bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET,
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.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
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.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
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.tshut_threshold = DRA752_BANDGAP_TSHUT_IVA_OFFSET,
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.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
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.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
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.bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
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.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
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.status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK,
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@ -121,9 +115,6 @@ dra752_mpu_temp_sensor_registers = {
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.bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET,
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.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
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.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
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.tshut_threshold = DRA752_BANDGAP_TSHUT_MPU_OFFSET,
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.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
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.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
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.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
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.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
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.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK,
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@ -157,9 +148,6 @@ dra752_dspeve_temp_sensor_registers = {
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.bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET,
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.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
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.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
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.tshut_threshold = DRA752_BANDGAP_TSHUT_DSPEVE_OFFSET,
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.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
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.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
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.bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
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.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
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.status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK,
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@ -193,9 +181,6 @@ dra752_gpu_temp_sensor_registers = {
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.bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET,
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.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
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.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
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.tshut_threshold = DRA752_BANDGAP_TSHUT_GPU_OFFSET,
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.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
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.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
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.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
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.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
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.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK,
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@ -211,8 +196,6 @@ dra752_gpu_temp_sensor_registers = {
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/* Thresholds and limits for DRA752 MPU temperature sensor */
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static struct temp_sensor_data dra752_mpu_temp_sensor_data = {
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.tshut_hot = DRA752_MPU_TSHUT_HOT,
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.tshut_cold = DRA752_MPU_TSHUT_COLD,
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.t_hot = DRA752_MPU_T_HOT,
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.t_cold = DRA752_MPU_T_COLD,
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.min_freq = DRA752_MPU_MIN_FREQ,
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@ -226,8 +209,6 @@ static struct temp_sensor_data dra752_mpu_temp_sensor_data = {
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/* Thresholds and limits for DRA752 GPU temperature sensor */
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static struct temp_sensor_data dra752_gpu_temp_sensor_data = {
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.tshut_hot = DRA752_GPU_TSHUT_HOT,
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.tshut_cold = DRA752_GPU_TSHUT_COLD,
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.t_hot = DRA752_GPU_T_HOT,
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.t_cold = DRA752_GPU_T_COLD,
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.min_freq = DRA752_GPU_MIN_FREQ,
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@ -241,8 +222,6 @@ static struct temp_sensor_data dra752_gpu_temp_sensor_data = {
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/* Thresholds and limits for DRA752 CORE temperature sensor */
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static struct temp_sensor_data dra752_core_temp_sensor_data = {
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.tshut_hot = DRA752_CORE_TSHUT_HOT,
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.tshut_cold = DRA752_CORE_TSHUT_COLD,
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.t_hot = DRA752_CORE_T_HOT,
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.t_cold = DRA752_CORE_T_COLD,
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.min_freq = DRA752_CORE_MIN_FREQ,
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@ -256,8 +235,6 @@ static struct temp_sensor_data dra752_core_temp_sensor_data = {
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/* Thresholds and limits for DRA752 DSPEVE temperature sensor */
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static struct temp_sensor_data dra752_dspeve_temp_sensor_data = {
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.tshut_hot = DRA752_DSPEVE_TSHUT_HOT,
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.tshut_cold = DRA752_DSPEVE_TSHUT_COLD,
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.t_hot = DRA752_DSPEVE_T_HOT,
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.t_cold = DRA752_DSPEVE_T_COLD,
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.min_freq = DRA752_DSPEVE_MIN_FREQ,
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@ -271,8 +248,6 @@ static struct temp_sensor_data dra752_dspeve_temp_sensor_data = {
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/* Thresholds and limits for DRA752 IVA temperature sensor */
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static struct temp_sensor_data dra752_iva_temp_sensor_data = {
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.tshut_hot = DRA752_IVA_TSHUT_HOT,
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.tshut_cold = DRA752_IVA_TSHUT_COLD,
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.t_hot = DRA752_IVA_T_HOT,
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.t_cold = DRA752_IVA_T_COLD,
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.min_freq = DRA752_IVA_MIN_FREQ,
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