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iwlwifi: prepare for PAN queue/fifo assignment
PAN ucode will require a different queue assignment, in particular queue 9 instead of 4 should be used for commands. This is required because the ucode will stop/start queues 4 and 8 depending on the PAN state, since queue 8 will be used for PAN multicast (after DTIM). Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
This commit is contained in:
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246ed35522
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13bb9483e1
@ -226,6 +226,7 @@ struct iwl3945_eeprom {
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/* 4 DATA + 1 CMD. There are 2 HCCA queues that are not used. */
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#define IWL39_NUM_QUEUES 5
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#define IWL39_CMD_QUEUE_NUM 4
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#define IWL_DEFAULT_TX_RETRY 15
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@ -273,7 +273,7 @@ static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
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struct iwl_queue *q = &txq->q;
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struct iwl_tx_info *tx_info;
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BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
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BUG_ON(txq_id == IWL39_CMD_QUEUE_NUM);
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for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
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q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
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@ -285,7 +285,7 @@ static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
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}
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if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
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(txq_id != IWL_CMD_QUEUE_NUM) &&
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(txq_id != IWL39_CMD_QUEUE_NUM) &&
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priv->mac80211_registered)
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iwl_wake_queue(priv, txq_id);
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}
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@ -760,7 +760,7 @@ void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
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data_retry_limit = IWL_DEFAULT_TX_RETRY;
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tx_cmd->data_retry_limit = data_retry_limit;
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if (tx_id >= IWL_CMD_QUEUE_NUM)
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if (tx_id >= IWL39_CMD_QUEUE_NUM)
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rts_retry_limit = 3;
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else
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rts_retry_limit = 7;
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@ -909,7 +909,7 @@ static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
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/* Tx queue(s) */
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for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
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slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
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slots_num = (txq_id == IWL39_CMD_QUEUE_NUM) ?
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TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
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rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
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txq_id);
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@ -1072,7 +1072,7 @@ void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
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if (priv->txq)
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for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
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txq_id++)
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if (txq_id == IWL_CMD_QUEUE_NUM)
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if (txq_id == IWL39_CMD_QUEUE_NUM)
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iwl_cmd_queue_free(priv);
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else
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iwl_tx_queue_free(priv, txq_id);
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@ -576,7 +576,7 @@ static int iwl4965_alive_notify(struct iwl_priv *priv)
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/* Activate all Tx DMA/FIFO channels */
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priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 6));
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iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
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iwl4965_set_wr_ptrs(priv, IWL_DEFAULT_CMD_QUEUE_NUM, 0);
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/* make sure all queue are not stopped */
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memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
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@ -587,6 +587,7 @@ static int iwl4965_alive_notify(struct iwl_priv *priv)
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priv->txq_ctx_active_msk = 0;
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/* Map each Tx/cmd queue to its corresponding fifo */
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BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
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for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
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int ac = default_queue_to_tx_fifo[i];
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@ -1479,7 +1479,7 @@ int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
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/* waiting for all the tx frames complete might take a while */
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for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
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if (cnt == IWL_CMD_QUEUE_NUM)
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if (cnt == priv->cmd_queue)
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continue;
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txq = &priv->txq[cnt];
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q = &txq->q;
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@ -118,7 +118,7 @@ void iwlagn_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
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WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
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if (txq_id != IWL_CMD_QUEUE_NUM) {
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if (txq_id != priv->cmd_queue) {
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sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
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sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
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@ -155,7 +155,7 @@ void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
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WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
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if (txq_id != IWL_CMD_QUEUE_NUM)
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if (txq_id != priv->cmd_queue)
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sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
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bc_ent = cpu_to_le16(1 | (sta_id << 12));
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@ -825,7 +825,7 @@ void iwlagn_hw_txq_ctx_free(struct iwl_priv *priv)
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/* Tx queues */
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if (priv->txq) {
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for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
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if (txq_id == IWL_CMD_QUEUE_NUM)
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if (txq_id == priv->cmd_queue)
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iwl_cmd_queue_free(priv);
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else
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iwl_tx_queue_free(priv, txq_id);
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@ -882,9 +882,9 @@ int iwlagn_txq_ctx_alloc(struct iwl_priv *priv)
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spin_unlock_irqrestore(&priv->lock, flags);
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/* Alloc and init all Tx queues, including the command queue (#4) */
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/* Alloc and init all Tx queues, including the command queue (#4/#9) */
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for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
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slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
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slots_num = (txq_id == priv->cmd_queue) ?
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TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
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ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
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txq_id);
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@ -922,7 +922,7 @@ void iwlagn_txq_ctx_reset(struct iwl_priv *priv)
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/* Alloc and init all Tx queues, including the command queue (#4) */
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for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
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slots_num = txq_id == IWL_CMD_QUEUE_NUM ?
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slots_num = txq_id == priv->cmd_queue ?
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TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
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iwl_tx_queue_reset(priv, &priv->txq[txq_id], slots_num, txq_id);
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}
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@ -52,6 +52,19 @@ static const s8 iwlagn_default_queue_to_tx_fifo[] = {
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IWL_TX_FIFO_UNUSED,
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};
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static const s8 iwlagn_ipan_queue_to_tx_fifo[] = {
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IWL_TX_FIFO_VO,
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IWL_TX_FIFO_VI,
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IWL_TX_FIFO_BE,
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IWL_TX_FIFO_BK,
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IWL_TX_FIFO_UNUSED, /* FIXME */
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IWL_TX_FIFO_UNUSED, /* FIXME */
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IWL_TX_FIFO_UNUSED, /* FIXME */
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IWL_TX_FIFO_UNUSED, /* FIXME */
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IWL_TX_FIFO_UNUSED, /* FIXME */
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IWLAGN_CMD_FIFO_NUM,
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};
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static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
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{COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
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0, COEX_UNASSOC_IDLE_FLAGS},
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@ -376,6 +389,7 @@ static void iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
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int iwlagn_alive_notify(struct iwl_priv *priv)
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{
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const s8 *queues;
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u32 a;
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unsigned long flags;
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int i, chan;
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@ -410,7 +424,7 @@ int iwlagn_alive_notify(struct iwl_priv *priv)
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reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
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iwl_write_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL,
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IWLAGN_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
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IWLAGN_SCD_QUEUECHAIN_SEL_ALL(priv));
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iwl_write_prph(priv, IWLAGN_SCD_AGGR_SEL, 0);
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/* initiate the queues */
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@ -436,7 +450,13 @@ int iwlagn_alive_notify(struct iwl_priv *priv)
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/* Activate all Tx DMA/FIFO channels */
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priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
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iwlagn_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
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/* map queues to FIFOs */
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if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
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queues = iwlagn_ipan_queue_to_tx_fifo;
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else
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queues = iwlagn_default_queue_to_tx_fifo;
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iwlagn_set_wr_ptrs(priv, priv->cmd_queue, 0);
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/* make sure all queue are not stopped */
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memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
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@ -445,11 +465,12 @@ int iwlagn_alive_notify(struct iwl_priv *priv)
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/* reset to 0 to enable all the queue first */
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priv->txq_ctx_active_msk = 0;
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/* map qos queues to fifos one-to-one */
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BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) != 10);
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for (i = 0; i < ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo); i++) {
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int ac = iwlagn_default_queue_to_tx_fifo[i];
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BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) != 10);
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BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) != 10);
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for (i = 0; i < 10; i++) {
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int ac = queues[i];
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iwl_txq_ctx_activate(priv, i);
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@ -3011,6 +3011,9 @@ static int __iwl_up(struct iwl_priv *priv)
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iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
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/* must be initialised before iwl_hw_nic_init */
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priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
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ret = iwlagn_hw_nic_init(priv);
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if (ret) {
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IWL_ERR(priv, "Unable to init nic\n");
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@ -2757,14 +2757,14 @@ void iwl_bg_monitor_recover(unsigned long data)
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return;
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/* monitor and check for stuck cmd queue */
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if (iwl_check_stuck_queue(priv, IWL_CMD_QUEUE_NUM))
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if (iwl_check_stuck_queue(priv, priv->cmd_queue))
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return;
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/* monitor and check for other stuck queues */
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if (iwl_is_any_associated(priv)) {
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for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
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/* skip as we already checked the command queue */
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if (cnt == IWL_CMD_QUEUE_NUM)
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if (cnt == priv->cmd_queue)
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continue;
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if (iwl_check_stuck_queue(priv, cnt))
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return;
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@ -265,11 +265,10 @@ struct iwl_channel_info {
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#define IWL_MIN_NUM_QUEUES 10
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/*
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* Queue #4 is the command queue for 3945/4965/5x00/1000/6x00,
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* the driver maps it into the appropriate device FIFO for the
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* uCode.
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* Command queue depends on iPAN support.
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*/
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#define IWL_CMD_QUEUE_NUM 4
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#define IWL_DEFAULT_CMD_QUEUE_NUM 4
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#define IWL_IPAN_CMD_QUEUE_NUM 9
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/* Power management (not Tx power) structures */
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@ -1197,6 +1196,9 @@ struct iwl_priv {
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/* microcode/device supports multiple contexts */
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u8 valid_contexts;
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/* command queue number */
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u8 cmd_queue;
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/* EEPROM MAC addresses */
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struct mac_address addresses[2];
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@ -232,7 +232,7 @@ cancel:
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* in later, it will possibly set an invalid
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* address (cmd->meta.source).
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*/
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priv->txq[IWL_CMD_QUEUE_NUM].meta[cmd_idx].flags &=
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priv->txq[priv->cmd_queue].meta[cmd_idx].flags &=
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~CMD_WANT_SKB;
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}
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fail:
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@ -306,7 +306,7 @@
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* at a time, until receiving ACK from receiving station, or reaching
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* retry limit and giving up.
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*
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* The command queue (#4) must use this mode!
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* The command queue (#4/#9) must use this mode!
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* This mode does not require use of the Byte Count table in host DRAM.
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*
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* Driver controls scheduler operation via 3 means:
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@ -322,7 +322,7 @@
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* (1024 bytes for each queue).
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*
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* After receiving "Alive" response from uCode, driver must initialize
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* the scheduler (especially for queue #4, the command queue, otherwise
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* the scheduler (especially for queue #4/#9, the command queue, otherwise
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* the driver can't issue commands!):
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*/
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@ -555,8 +555,9 @@
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#define IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
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((IWLAGN_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffc)
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#define IWLAGN_SCD_QUEUECHAIN_SEL_ALL(x) (((1<<(x)) - 1) &\
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(~(1<<IWL_CMD_QUEUE_NUM)))
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#define IWLAGN_SCD_QUEUECHAIN_SEL_ALL(priv) \
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(((1<<(priv)->hw_params.max_txq_num) - 1) &\
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(~(1<<(priv)->cmd_queue)))
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#define IWLAGN_SCD_BASE (PRPH_BASE + 0xa02c00)
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@ -134,7 +134,7 @@ EXPORT_SYMBOL(iwl_tx_queue_free);
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*/
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void iwl_cmd_queue_free(struct iwl_priv *priv)
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{
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struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
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struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
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struct iwl_queue *q = &txq->q;
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struct device *dev = &priv->pci_dev->dev;
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int i;
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@ -271,7 +271,7 @@ static int iwl_tx_queue_alloc(struct iwl_priv *priv,
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/* Driver private data, only for Tx (not command) queues,
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* not shared with device. */
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if (id != IWL_CMD_QUEUE_NUM) {
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if (id != priv->cmd_queue) {
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txq->txb = kzalloc(sizeof(txq->txb[0]) *
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TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
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if (!txq->txb) {
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@ -314,13 +314,13 @@ int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
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/*
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* Alloc buffer array for commands (Tx or other types of commands).
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* For the command queue (#4), allocate command space + one big
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* For the command queue (#4/#9), allocate command space + one big
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* command for scan, since scan command is very huge; the system will
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* not have two scans at the same time, so only one is needed.
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* For normal Tx queues (all other queues), no super-size command
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* space is needed.
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*/
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if (txq_id == IWL_CMD_QUEUE_NUM)
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if (txq_id == priv->cmd_queue)
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actual_slots++;
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txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
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@ -355,7 +355,7 @@ int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
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* need an swq_id so don't set one to catch errors, all others can
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* be set up to the identity mapping.
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*/
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if (txq_id != IWL_CMD_QUEUE_NUM)
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if (txq_id != priv->cmd_queue)
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txq->swq_id = txq_id;
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/* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
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@ -385,7 +385,7 @@ void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq,
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{
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int actual_slots = slots_num;
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if (txq_id == IWL_CMD_QUEUE_NUM)
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if (txq_id == priv->cmd_queue)
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actual_slots++;
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memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots);
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@ -413,7 +413,7 @@ EXPORT_SYMBOL(iwl_tx_queue_reset);
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*/
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int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
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{
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struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
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struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
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struct iwl_queue *q = &txq->q;
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struct iwl_device_cmd *out_cmd;
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struct iwl_cmd_meta *out_meta;
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@ -483,7 +483,7 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
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* information */
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out_cmd->hdr.flags = 0;
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out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
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out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) |
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INDEX_TO_SEQ(q->write_ptr));
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if (cmd->flags & CMD_SIZE_HUGE)
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out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
|
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@ -500,15 +500,15 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
||||
get_cmd_string(out_cmd->hdr.cmd),
|
||||
out_cmd->hdr.cmd,
|
||||
le16_to_cpu(out_cmd->hdr.sequence), fix_size,
|
||||
q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
|
||||
break;
|
||||
q->write_ptr, idx, priv->cmd_queue);
|
||||
break;
|
||||
default:
|
||||
IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
|
||||
"%d bytes at %d[%d]:%d\n",
|
||||
get_cmd_string(out_cmd->hdr.cmd),
|
||||
out_cmd->hdr.cmd,
|
||||
le16_to_cpu(out_cmd->hdr.sequence), fix_size,
|
||||
q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
|
||||
q->write_ptr, idx, priv->cmd_queue);
|
||||
}
|
||||
#endif
|
||||
txq->need_update = 1;
|
||||
@ -587,16 +587,16 @@ void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
|
||||
bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
|
||||
struct iwl_device_cmd *cmd;
|
||||
struct iwl_cmd_meta *meta;
|
||||
struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
|
||||
struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
|
||||
|
||||
/* If a Tx command is being handled and it isn't in the actual
|
||||
* command queue then there a command routing bug has been introduced
|
||||
* in the queue management code. */
|
||||
if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
|
||||
"wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
|
||||
txq_id, sequence,
|
||||
priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
|
||||
priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
|
||||
if (WARN(txq_id != priv->cmd_queue,
|
||||
"wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
|
||||
txq_id, priv->cmd_queue, sequence,
|
||||
priv->txq[priv->cmd_queue].q.read_ptr,
|
||||
priv->txq[priv->cmd_queue].q.write_ptr)) {
|
||||
iwl_print_hex_error(priv, pkt, 32);
|
||||
return;
|
||||
}
|
||||
|
@ -4001,6 +4001,8 @@ static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
|
||||
priv = hw->priv;
|
||||
SET_IEEE80211_DEV(hw, &pdev->dev);
|
||||
|
||||
priv->cmd_queue = IWL39_CMD_QUEUE_NUM;
|
||||
|
||||
/* 3945 has only one valid context */
|
||||
priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user