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arm64: tegra: Device tree changes for v5.1-rc1

Browse Source 
This contains a couple of fixes to existing device trees, enables CPU
 frequency scaling on various Tegra210 boards, enables the TCU as debug
 serial port on Jetson Xavier, adds various improvements for SDMMC on
 Tegra210, Tegra186 and Tegra194 boards and finally adds initial support
 for the NVIDIA Shield TV.
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Merge tag 'tegra-for-5.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

arm64: tegra: Device tree changes for v5.1-rc1

This contains a couple of fixes to existing device trees, enables CPU
frequency scaling on various Tegra210 boards, enables the TCU as debug
serial port on Jetson Xavier, adds various improvements for SDMMC on
Tegra210, Tegra186 and Tegra194 boards and finally adds initial support
for the NVIDIA Shield TV.

* tag 'tegra-for-5.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (25 commits)
  arm64: tegra: Update compatible for Tegra186 I2C
  arm64: tegra: Update compatible for Tegra210 I2C
  arm64: tegra: Support 200 MHz for SDMMC on Tegra194
  arm64: tegra: Add CQE Support for SDMMC4
  arm64: tegra: Add SDMMC auto-calibration settings
  arm64: tegra: Mark TCU as primary serial port on Tegra194 P2888
  arm64: tegra: Add nodes for TCU on Tegra194
  arm64: tegra: Enable DFLL clock on Smaug
  arm64: tegra: Add CPU power rail regulator on Smaug
  arm64: tegra: Enable DFLL clock on Jetson TX1
  arm64: tegra: Add pinmux for PWM-based DFLL support on P2597
  arm64: tegra: Add CPU clocks on Tegra210
  arm64: tegra: Add DFLL clock on Tegra210
  arm64: tegra: p2771-0000: Use TEGRA186_ prefix for GPIO names
  arm64: tegra: p3310: Use TEGRA186_ prefix for GPIO names
  arm64: tegra: p2597: Sort nodes by unit-address
  arm64: tegra: p2972: Sort nodes properly
  arm64: tegra: Add regulators for Tegra210 Darcy
  arm64: tegra: Add pinmux for Darcy board
  arm64: tegra: Add gpio-keys nodes for Darcy
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2019-02-15 15:51:42 +01:00
commit 1228c051ba
13 changed files with 2140 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm64/boot/dts/nvidia/Makefile
View File

@ -4,5 +4,6 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb
dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb

18
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
View File

@ -26,7 +26,8 @@
reg = <0x74>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_MAIN_GPIO(Y, 0) GPIO_ACTIVE_LOW>;
interrupts = <TEGRA186_MAIN_GPIO(Y, 0)
GPIO_ACTIVE_LOW>;
#gpio-cells = <2>;
gpio-controller;
@ -37,7 +38,8 @@
reg = <0x77>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_MAIN_GPIO(Y, 6) GPIO_ACTIVE_LOW>;
interrupts = <TEGRA186_MAIN_GPIO(Y, 6)
GPIO_ACTIVE_LOW>;
#gpio-cells = <2>;
gpio-controller;
@ -108,7 +110,8 @@
hdmi-supply = <&vdd_hdmi>;
nvidia,ddc-i2c-bus = <&ddc>;
nvidia,hpd-gpio = <&gpio TEGRA_MAIN_GPIO(P, 1) GPIO_ACTIVE_LOW>;
nvidia,hpd-gpio = <&gpio TEGRA186_MAIN_GPIO(P, 1)
GPIO_ACTIVE_LOW>;
};
dpaux@155c0000 {
@ -121,7 +124,7 @@
power {
label = "Power";
gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 0)
gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0)
GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_POWER>;
@ -132,7 +135,7 @@
volume-up {
label = "Volume Up";
gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 1)
gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1)
GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_VOLUMEUP>;
@ -141,7 +144,7 @@
volume-down {
label = "Volume Down";
gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 2)
gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2)
GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_VOLUMEDOWN>;
@ -158,7 +161,8 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6)
GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_3v3_sys>;

10
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
View File

@ -34,7 +34,8 @@
ethernet@2490000 {
status = "okay";
phy-reset-gpios = <&gpio TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>;
phy-reset-gpios = <&gpio TEGRA186_MAIN_GPIO(M, 4)
GPIO_ACTIVE_LOW>;
phy-handle = <&phy>;
phy-mode = "rgmii";
@ -46,7 +47,8 @@
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_MAIN_GPIO(M, 5) IRQ_TYPE_LEVEL_LOW>;
interrupts = <TEGRA186_MAIN_GPIO(M, 5)
IRQ_TYPE_LEVEL_LOW>;
};
};
};
@ -91,8 +93,8 @@
/* SDMMC1 (SD/MMC) */
sdhci@3400000 {
cd-gpios = <&gpio TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
vqmmc-supply = <&vddio_sdmmc1>;
};

21
arch/arm64/boot/dts/nvidia/tegra186.dtsi
View File

@ -136,7 +136,7 @@
};
gen1_i2c: i2c@3160000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
reg = <0x0 0x03160000 0x0 0x10000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -149,7 +149,7 @@
};
cam_i2c: i2c@3180000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
reg = <0x0 0x03180000 0x0 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -163,7 +163,7 @@
/* shares pads with dpaux1 */
dp_aux_ch1_i2c: i2c@3190000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
reg = <0x0 0x03190000 0x0 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -177,7 +177,7 @@
/* controlled by BPMP, should not be enabled */
pwr_i2c: i2c@31a0000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
reg = <0x0 0x031a0000 0x0 0x10000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -191,7 +191,7 @@
/* shares pads with dpaux0 */
dp_aux_ch0_i2c: i2c@31b0000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
reg = <0x0 0x031b0000 0x0 0x10000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -204,7 +204,7 @@
};
gen7_i2c: i2c@31c0000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
reg = <0x0 0x031c0000 0x0 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -217,7 +217,7 @@
};
gen9_i2c: i2c@31e0000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
reg = <0x0 0x031e0000 0x0 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -315,10 +315,13 @@
nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
nvidia,default-tap = <0x5>;
nvidia,default-trim = <0x9>;
nvidia,dqs-trim = <63>;
mmc-hs400-1_8v;
supports-cqe;
status = "disabled";
};
@ -375,7 +378,7 @@
};
gen2_i2c: i2c@c240000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
reg = <0x0 0x0c240000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -388,7 +391,7 @@
};
gen8_i2c: i2c@c250000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
reg = <0x0 0x0c250000 0x0 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;

2
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
View File

@ -10,7 +10,7 @@
aliases {
sdhci0 = "/cbb/sdhci@3460000";
sdhci1 = "/cbb/sdhci@3400000";
serial0 = &uartb;
serial0 = &tcu;
i2c0 = "/bpmp/i2c";
i2c1 = "/cbb/i2c@3160000";
i2c2 = "/cbb/i2c@c240000";

10
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
View File

@ -11,12 +11,16 @@
compatible = "nvidia,p2972-0000", "nvidia,tegra194";
cbb {
ddc: i2c@31c0000 {
status = "okay";
};
/* SDMMC1 (SD/MMC) */
sdhci@3400000 {
status = "okay";
};
ddc: i2c@31c0000 {
hda@3510000 {
status = "okay";
};
@ -24,10 +28,6 @@
status = "okay";
};
hda@3510000 {
status = "okay";
};
host1x@13e00000 {
display-hub@15200000 {
status = "okay";

77
arch/arm64/boot/dts/nvidia/tegra194.dtsi
View File

@ -303,6 +303,17 @@
clock-names = "sdhci";
resets = <&bpmp TEGRA194_RESET_SDMMC1>;
reset-names = "sdhci";
nvidia,pad-autocal-pull-up-offset-3v3-timeout =
<0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout =
<0x07>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
nvidia,pad-autocal-pull-down-offset-1v8-timeout =
<0x07>;
nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
nvidia,default-tap = <0x9>;
nvidia,default-trim = <0x5>;
status = "disabled";
};
@ -314,6 +325,18 @@
clock-names = "sdhci";
resets = <&bpmp TEGRA194_RESET_SDMMC3>;
reset-names = "sdhci";
nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout =
<0x07>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
nvidia,pad-autocal-pull-down-offset-1v8-timeout =
<0x07>;
nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
nvidia,default-tap = <0x9>;
nvidia,default-trim = <0x5>;
status = "disabled";
};
@ -323,8 +346,24 @@
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
clock-names = "sdhci";
assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
<&bpmp TEGRA194_CLK_PLLC4>;
assigned-clock-parents =
<&bpmp TEGRA194_CLK_PLLC4>;
resets = <&bpmp TEGRA194_RESET_SDMMC4>;
reset-names = "sdhci";
nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
nvidia,pad-autocal-pull-down-offset-1v8-timeout =
<0x0a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout =
<0x0a>;
nvidia,default-tap = <0x8>;
nvidia,default-trim = <0x14>;
nvidia,dqs-trim = <40>;
supports-cqe;
status = "disabled";
};
@ -367,10 +406,35 @@
};
hsp_top0: hsp@3c00000 {
compatible = "nvidia,tegra186-hsp";
compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
reg = <0x03c00000 0xa0000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "doorbell";
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "doorbell", "shared0", "shared1", "shared2",
"shared3", "shared4", "shared5", "shared6",
"shared7";
#mbox-cells = <2>;
};
hsp_aon: hsp@c150000 {
compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
reg = <0x0c150000 0xa0000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
/*
* Shared interrupt 0 is routed only to AON/SPE, so
* we only have 4 shared interrupts for the CCPLEX.
*/
interrupt-names = "shared1", "shared2", "shared3", "shared4";
#mbox-cells = <2>;
};
@ -933,6 +997,13 @@
method = "smc";
};
tcu: tcu {
compatible = "nvidia,tegra194-tcu";
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
<&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
mbox-names = "rx", "tx";
};
thermal-zones {
cpu {
thermal-sensors = <&{/bpmp/thermal}

21
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
View File

@ -78,4 +78,25 @@
};
};
};
clock@70110000 {
status = "okay";
nvidia,cf = <6>;
nvidia,ci = <0>;
nvidia,cg = <2>;
nvidia,droop-ctrl = <0x00000f00>;
nvidia,force-mode = <1>;
nvidia,sample-rate = <25000>;
nvidia,pwm-min-microvolts = <708000>;
nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
nvidia,pwm-to-pmic;
nvidia,pwm-tristate-microvolts = <1000000>;
nvidia,pwm-voltage-step-microvolts = <19200>;
pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
pinctrl-0 = <&dvfs_pwm_active_state>;
pinctrl-1 = <&dvfs_pwm_inactive_state>;
};
};

32
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
View File

@ -1278,6 +1278,20 @@
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
};
dvfs_pwm_active_state: dvfs_pwm_active {
dvfs_pwm_pbb1 {
nvidia,pins = "dvfs_pwm_pbb1";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
};
dvfs_pwm_inactive_state: dvfs_pwm_inactive {
dvfs_pwm_pbb1 {
nvidia,pins = "dvfs_pwm_pbb1";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
};
};
pwm@7000a000 {
@ -1303,6 +1317,15 @@
clock-frequency = <100000>;
};
sata@70020000 {
status = "okay";
phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
};
hda@70030000 {
status = "okay";
};
usb@70090000 {
phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
<&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
@ -1325,15 +1348,6 @@
status = "okay";
};
sata@70020000 {
status = "okay";
phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
};
hda@70030000 {
status = "okay";
};
padctl@7009f000 {
status = "okay";

9
arch/arm64/boot/dts/nvidia/tegra210-p2894-0050-a08.dts Normal file
View File

@ -0,0 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra210-p2894.dtsi"
/ {
model = "NVIDIA Shield TV";
compatible = "nvidia,p2894-0050-a08", "nvidia,darcy", "nvidia,tegra210";
};

1858
arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

34
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
View File

@ -1340,10 +1340,29 @@
status = "okay";
clock-frequency = <1000000>;
max77621_cpu: max77621@1b {
compatible = "maxim,max77621";
reg = <0x1b>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(Y, 1) IRQ_TYPE_LEVEL_LOW>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1231250>;
regulator-name = "PPVAR_CPU";
regulator-ramp-delay = <12500>;
maxim,dvs-default-state = <1>;
maxim,enable-active-discharge;
maxim,enable-bias-control;
maxim,enable-etr;
maxim,enable-gpio = <&max77620 5 0>;
maxim,externally-enable;
};
max77620: max77620@3c {
compatible = "maxim,max77620";
reg = <0x3c>;
interrupts = <0 86 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
@ -1679,6 +1698,18 @@
status = "okay";
};
clock@70110000 {
status = "okay";
nvidia,cf = <6>;
nvidia,ci = <0>;
nvidia,cg = <2>;
nvidia,droop-ctrl = <0x00000f00>;
nvidia,force-mode = <1>;
nvidia,i2c-fs-rate = <400000>;
nvidia,sample-rate = <12500>;
vdd-cpu-supply = <&max77621_cpu>;
};
aconnect@702c0000 {
status = "okay";
@ -1724,7 +1755,6 @@
gpio-keys {
compatible = "gpio-keys";
gpio-keys,name = "gpio-keys";
power {
label = "Power";

96
arch/arm64/boot/dts/nvidia/tegra210.dtsi
View File

@ -4,6 +4,7 @@
#include <dt-bindings/memory/tegra210-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
#include <dt-bindings/reset/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
@ -469,13 +470,55 @@
apbmisc@70000800 {
compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
<0x0 0x7000e864 0x0 0x04>; /* Strapping options */
<0x0 0x70000008 0x0 0x04>; /* Strapping options */
};
pinmux: pinmux@700008d4 {
compatible = "nvidia,tegra210-pinmux";
reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
<0x0 0x70003000 0x0 0x294>; /* Mux registers */
sdmmc1_3v3_drv: sdmmc1-3v3-drv {
sdmmc1 {
nvidia,pins = "drive_sdmmc1";
nvidia,pull-down-strength = <0x8>;
nvidia,pull-up-strength = <0x8>;
};
};
sdmmc1_1v8_drv: sdmmc1-1v8-drv {
sdmmc1 {
nvidia,pins = "drive_sdmmc1";
nvidia,pull-down-strength = <0x4>;
nvidia,pull-up-strength = <0x3>;
};
};
sdmmc2_1v8_drv: sdmmc2-1v8-drv {
sdmmc2 {
nvidia,pins = "drive_sdmmc2";
nvidia,pull-down-strength = <0x10>;
nvidia,pull-up-strength = <0x10>;
};
};
sdmmc3_3v3_drv: sdmmc3-3v3-drv {
sdmmc3 {
nvidia,pins = "drive_sdmmc3";
nvidia,pull-down-strength = <0x8>;
nvidia,pull-up-strength = <0x8>;
};
};
sdmmc3_1v8_drv: sdmmc3-1v8-drv {
sdmmc3 {
nvidia,pins = "drive_sdmmc3";
nvidia,pull-down-strength = <0x4>;
nvidia,pull-up-strength = <0x3>;
};
};
sdmmc4_1v8_drv: sdmmc4-1v8-drv {
sdmmc4 {
nvidia,pins = "drive_sdmmc4";
nvidia,pull-down-strength = <0x10>;
nvidia,pull-up-strength = <0x10>;
};
};
};
/*
@ -554,7 +597,7 @@
};
i2c@7000c000 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
reg = <0x0 0x7000c000 0x0 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -569,7 +612,7 @@
};
i2c@7000c400 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
reg = <0x0 0x7000c400 0x0 0x100>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -584,7 +627,7 @@
};
i2c@7000c500 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
reg = <0x0 0x7000c500 0x0 0x100>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -599,7 +642,7 @@
};
i2c@7000c700 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
reg = <0x0 0x7000c700 0x0 0x100>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -617,7 +660,7 @@
};
i2c@7000d000 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
reg = <0x0 0x7000d000 0x0 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -632,7 +675,7 @@
};
i2c@7000d100 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
reg = <0x0 0x7000d100 0x0 0x100>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -1050,9 +1093,12 @@
clock-names = "sdhci";
resets = <&tegra_car 14>;
reset-names = "sdhci";
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
"sdmmc-3v3-drv", "sdmmc-1v8-drv";
pinctrl-0 = <&sdmmc1_3v3>;
pinctrl-1 = <&sdmmc1_1v8>;
pinctrl-2 = <&sdmmc1_3v3_drv>;
pinctrl-3 = <&sdmmc1_1v8_drv>;
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
@ -1075,6 +1121,8 @@
clock-names = "sdhci";
resets = <&tegra_car 9>;
reset-names = "sdhci";
pinctrl-names = "sdmmc-1v8-drv";
pinctrl-0 = <&sdmmc2_1v8_drv>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
nvidia,default-tap = <0x8>;
@ -1090,9 +1138,12 @@
clock-names = "sdhci";
resets = <&tegra_car 69>;
reset-names = "sdhci";
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
"sdmmc-3v3-drv", "sdmmc-1v8-drv";
pinctrl-0 = <&sdmmc3_3v3>;
pinctrl-1 = <&sdmmc3_1v8>;
pinctrl-2 = <&sdmmc3_3v3_drv>;
pinctrl-3 = <&sdmmc3_1v8_drv>;
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
@ -1110,6 +1161,9 @@
clock-names = "sdhci";
resets = <&tegra_car 15>;
reset-names = "sdhci";
pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
pinctrl-0 = <&sdmmc4_1v8_drv>;
pinctrl-1 = <&sdmmc4_1v8_drv>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
nvidia,default-tap = <0x8>;
@ -1131,6 +1185,24 @@
#nvidia,mipi-calibrate-cells = <1>;
};
dfll: clock@70110000 {
compatible = "nvidia,tegra210-dfll";
reg = <0 0x70110000 0 0x100>, /* DFLL control */
<0 0x70110000 0 0x100>, /* I2C output control */
<0 0x70110100 0 0x100>, /* Integrated I2C controller */
<0 0x70110200 0 0x100>; /* Look-up table RAM */
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
<&tegra_car TEGRA210_CLK_DFLL_REF>,
<&tegra_car TEGRA210_CLK_I2C5>;
clock-names = "soc", "ref", "i2c";
resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
reset-names = "dvco";
#clock-cells = <0>;
clock-output-names = "dfllCPU_out";
status = "disabled";
};
aconnect@702c0000 {
compatible = "nvidia,tegra210-aconnect";
clocks = <&tegra_car TEGRA210_CLK_APE>,
@ -1285,6 +1357,12 @@
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0>;
clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
<&tegra_car TEGRA210_CLK_PLL_X>,
<&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
<&dfll>;
clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
clock-latency = <300000>;
};
cpu@1 {