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iommu/vt-d: Generalise DMAR MSI setup to allow for page request events
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
parent
907fea3491
commit
1208225cf4
@ -1086,6 +1086,11 @@ static void free_iommu(struct intel_iommu *iommu)
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iommu_device_destroy(iommu->iommu_dev);
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if (iommu->irq) {
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if (iommu->pr_irq) {
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free_irq(iommu->pr_irq, iommu);
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dmar_free_hwirq(iommu->pr_irq);
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iommu->pr_irq = 0;
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}
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free_irq(iommu->irq, iommu);
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dmar_free_hwirq(iommu->irq);
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iommu->irq = 0;
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@ -1493,53 +1498,68 @@ static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type)
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}
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}
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static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq)
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{
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if (iommu->irq == irq)
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return DMAR_FECTL_REG;
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else if (iommu->pr_irq == irq)
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return DMAR_PECTL_REG;
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else
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BUG();
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}
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void dmar_msi_unmask(struct irq_data *data)
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{
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struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
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int reg = dmar_msi_reg(iommu, data->irq);
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unsigned long flag;
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/* unmask it */
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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writel(0, iommu->reg + DMAR_FECTL_REG);
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writel(0, iommu->reg + reg);
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/* Read a reg to force flush the post write */
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readl(iommu->reg + DMAR_FECTL_REG);
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readl(iommu->reg + reg);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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void dmar_msi_mask(struct irq_data *data)
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{
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unsigned long flag;
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struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
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int reg = dmar_msi_reg(iommu, data->irq);
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unsigned long flag;
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/* mask it */
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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writel(DMA_FECTL_IM, iommu->reg + DMAR_FECTL_REG);
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writel(DMA_FECTL_IM, iommu->reg + reg);
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/* Read a reg to force flush the post write */
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readl(iommu->reg + DMAR_FECTL_REG);
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readl(iommu->reg + reg);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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void dmar_msi_write(int irq, struct msi_msg *msg)
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{
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struct intel_iommu *iommu = irq_get_handler_data(irq);
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int reg = dmar_msi_reg(iommu, irq);
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unsigned long flag;
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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writel(msg->data, iommu->reg + DMAR_FEDATA_REG);
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writel(msg->address_lo, iommu->reg + DMAR_FEADDR_REG);
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writel(msg->address_hi, iommu->reg + DMAR_FEUADDR_REG);
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writel(msg->data, iommu->reg + reg + 4);
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writel(msg->address_lo, iommu->reg + reg + 8);
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writel(msg->address_hi, iommu->reg + reg + 12);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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void dmar_msi_read(int irq, struct msi_msg *msg)
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{
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struct intel_iommu *iommu = irq_get_handler_data(irq);
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int reg = dmar_msi_reg(iommu, irq);
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unsigned long flag;
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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msg->data = readl(iommu->reg + DMAR_FEDATA_REG);
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msg->address_lo = readl(iommu->reg + DMAR_FEADDR_REG);
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msg->address_hi = readl(iommu->reg + DMAR_FEUADDR_REG);
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msg->data = readl(iommu->reg + reg + 4);
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msg->address_lo = readl(iommu->reg + reg + 8);
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msg->address_hi = readl(iommu->reg + reg + 12);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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@ -60,6 +60,14 @@
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#define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
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#define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
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#define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
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#define DMAR_PQH_REG 0xc0 /* Page request queue head register */
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#define DMAR_PQT_REG 0xc8 /* Page request queue tail register */
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#define DMAR_PQA_REG 0xd0 /* Page request queue address register */
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#define DMAR_PRS_REG 0xdc /* Page request status register */
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#define DMAR_PECTL_REG 0xe0 /* Page request event control register */
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#define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */
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#define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */
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#define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */
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#define OFFSET_STRIDE (9)
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@ -373,7 +381,7 @@ struct intel_iommu {
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int seq_id; /* sequence id of the iommu */
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int agaw; /* agaw of this iommu */
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int msagaw; /* max sagaw of this iommu */
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unsigned int irq;
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unsigned int irq, pr_irq;
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u16 segment; /* PCI segment# */
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unsigned char name[13]; /* Device Name */
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