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drm/xe/migrate: Handle clear ccs logic for xe2 dgfx
For Xe2 dGPU, we clear the bo by modifying the VRAM using an uncompressed pat index which then indirectly updates the compression status as uncompressed i.e zeroed CCS. So xe_migrate_clear() should be updated for BMG to not emit CCS surf copy commands. v2: Moved xe_device_needs_ccs_emit() to xe_migrate.c and changed name to xe_migrate_needs_ccs_emit() since its very specific to migration.(Matt) Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/8dd869dd8dda5e17ace28c04f1a48675f5540874.1721250309.git.akshata.jahagirdar@intel.com
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@ -347,6 +347,11 @@ static u32 xe_migrate_usm_logical_mask(struct xe_gt *gt)
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return logical_mask;
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}
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static bool xe_migrate_needs_ccs_emit(struct xe_device *xe)
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{
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return xe_device_has_flat_ccs(xe) && !(GRAPHICS_VER(xe) >= 20 && IS_DGFX(xe));
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}
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/**
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* xe_migrate_init() - Initialize a migrate context
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* @tile: Back-pointer to the tile we're initializing for.
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@ -420,7 +425,7 @@ struct xe_migrate *xe_migrate_init(struct xe_tile *tile)
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return ERR_PTR(err);
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if (IS_DGFX(xe)) {
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if (xe_device_has_flat_ccs(xe))
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if (xe_migrate_needs_ccs_emit(xe))
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/* min chunk size corresponds to 4K of CCS Metadata */
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m->min_chunk_size = SZ_4K * SZ_64K /
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xe_device_ccs_bytes(xe, SZ_64K);
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@ -1034,7 +1039,7 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m,
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clear_system_ccs ? 0 : emit_clear_cmd_len(gt), 0,
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avail_pts);
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if (xe_device_has_flat_ccs(xe))
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if (xe_migrate_needs_ccs_emit(xe))
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batch_size += EMIT_COPY_CCS_DW;
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/* Clear commands */
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@ -1062,7 +1067,7 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m,
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if (!clear_system_ccs)
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emit_clear(gt, bb, clear_L0_ofs, clear_L0, XE_PAGE_SIZE, clear_vram);
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if (xe_device_has_flat_ccs(xe)) {
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if (xe_migrate_needs_ccs_emit(xe)) {
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emit_copy_ccs(gt, bb, clear_L0_ofs, true,
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m->cleared_mem_ofs, false, clear_L0);
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flush_flags = MI_FLUSH_DW_CCS;
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