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counter: ti-eqep: implement over/underflow events
This adds support to the TI eQEP counter driver for subscribing to overflow and underflow events using the counter chrdev interface. Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://lore.kernel.org/r/20240609-counter-ti-eqep-over-under-events-v1-1-74fe1632f5ab@baylibre.com Signed-off-by: William Breathitt Gray <wbg@kernel.org>
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@ -8,6 +8,7 @@
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/counter.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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@ -68,6 +69,44 @@
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#define QEPCTL_UTE BIT(1)
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#define QEPCTL_WDE BIT(0)
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#define QEINT_UTO BIT(11)
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#define QEINT_IEL BIT(10)
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#define QEINT_SEL BIT(9)
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#define QEINT_PCM BIT(8)
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#define QEINT_PCR BIT(7)
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#define QEINT_PCO BIT(6)
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#define QEINT_PCU BIT(5)
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#define QEINT_WTO BIT(4)
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#define QEINT_QDC BIT(3)
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#define QEINT_PHE BIT(2)
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#define QEINT_PCE BIT(1)
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#define QFLG_UTO BIT(11)
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#define QFLG_IEL BIT(10)
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#define QFLG_SEL BIT(9)
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#define QFLG_PCM BIT(8)
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#define QFLG_PCR BIT(7)
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#define QFLG_PCO BIT(6)
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#define QFLG_PCU BIT(5)
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#define QFLG_WTO BIT(4)
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#define QFLG_QDC BIT(3)
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#define QFLG_PHE BIT(2)
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#define QFLG_PCE BIT(1)
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#define QFLG_INT BIT(0)
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#define QCLR_UTO BIT(11)
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#define QCLR_IEL BIT(10)
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#define QCLR_SEL BIT(9)
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#define QCLR_PCM BIT(8)
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#define QCLR_PCR BIT(7)
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#define QCLR_PCO BIT(6)
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#define QCLR_PCU BIT(5)
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#define QCLR_WTO BIT(4)
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#define QCLR_QDC BIT(3)
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#define QCLR_PHE BIT(2)
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#define QCLR_PCE BIT(1)
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#define QCLR_INT BIT(0)
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/* EQEP Inputs */
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enum {
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TI_EQEP_SIGNAL_QEPA, /* QEPA/XCLK */
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@ -239,12 +278,49 @@ static int ti_eqep_action_read(struct counter_device *counter,
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}
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}
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static int ti_eqep_events_configure(struct counter_device *counter)
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{
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struct ti_eqep_cnt *priv = counter_priv(counter);
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struct counter_event_node *event_node;
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u32 qeint = 0;
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list_for_each_entry(event_node, &counter->events_list, l) {
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switch (event_node->event) {
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case COUNTER_EVENT_OVERFLOW:
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qeint |= QEINT_PCO;
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break;
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case COUNTER_EVENT_UNDERFLOW:
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qeint |= QEINT_PCU;
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break;
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}
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}
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return regmap_write(priv->regmap16, QEINT, qeint);
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}
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static int ti_eqep_watch_validate(struct counter_device *counter,
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const struct counter_watch *watch)
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{
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switch (watch->event) {
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case COUNTER_EVENT_OVERFLOW:
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case COUNTER_EVENT_UNDERFLOW:
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if (watch->channel != 0)
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return -EINVAL;
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return 0;
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default:
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return -EINVAL;
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}
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}
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static const struct counter_ops ti_eqep_counter_ops = {
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.count_read = ti_eqep_count_read,
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.count_write = ti_eqep_count_write,
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.function_read = ti_eqep_function_read,
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.function_write = ti_eqep_function_write,
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.action_read = ti_eqep_action_read,
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.events_configure = ti_eqep_events_configure,
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.watch_validate = ti_eqep_watch_validate,
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};
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static int ti_eqep_position_ceiling_read(struct counter_device *counter,
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@ -355,6 +431,25 @@ static struct counter_count ti_eqep_counts[] = {
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},
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};
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static irqreturn_t ti_eqep_irq_handler(int irq, void *dev_id)
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{
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struct counter_device *counter = dev_id;
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struct ti_eqep_cnt *priv = counter_priv(counter);
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u32 qflg;
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regmap_read(priv->regmap16, QFLG, &qflg);
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if (qflg & QFLG_PCO)
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counter_push_event(counter, COUNTER_EVENT_OVERFLOW, 0);
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if (qflg & QFLG_PCU)
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counter_push_event(counter, COUNTER_EVENT_UNDERFLOW, 0);
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regmap_write(priv->regmap16, QCLR, qflg);
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return IRQ_HANDLED;
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}
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static const struct regmap_config ti_eqep_regmap32_config = {
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.name = "32-bit",
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.reg_bits = 32,
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@ -378,7 +473,7 @@ static int ti_eqep_probe(struct platform_device *pdev)
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struct ti_eqep_cnt *priv;
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void __iomem *base;
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struct clk *clk;
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int err;
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int err, irq;
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counter = devm_counter_alloc(dev, sizeof(*priv));
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if (!counter)
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@ -399,6 +494,15 @@ static int ti_eqep_probe(struct platform_device *pdev)
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if (IS_ERR(priv->regmap16))
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return PTR_ERR(priv->regmap16);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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err = devm_request_threaded_irq(dev, irq, NULL, ti_eqep_irq_handler,
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IRQF_ONESHOT, dev_name(dev), counter);
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if (err < 0)
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return dev_err_probe(dev, err, "failed to request IRQ\n");
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counter->name = dev_name(dev);
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counter->parent = dev;
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counter->ops = &ti_eqep_counter_ops;
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