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Merge branch 'pxa-plat' into devel

Browse Source 
* pxa-plat: (53 commits)
  [ARM] 4762/1: Basic support for Toradex Colibri module
  [ARM] pxa: fix mci_init functions returning -1
  [ARM] 4737/1: Refactor corgi_lcd to improve readability + bugfix
  [ARM] 4747/1: pcm027: support for pcm990 baseboard for phyCORE-PXA270
  [ARM] 4746/1: pcm027: network support for phyCORE-PXA270
  [ARM] 4745/1: pcm027: default configuration
  [ARM] 4744/1: pcm027: add support for phyCORE-PXA270 CPU module
  [NET] smc91x: Make smc91x use IRQ resource trigger flags
  [ARM] pxa: add default config for littleton
  [ARM] pxa: add basic support for Littleton (PXA3xx Form Factor Platform)
  [ARM] 4664/1: Add basic support for HTC Magician PDA phones
  [ARM] 4649/1: Base support for pxa-based Toshiba e-series PDAs.
  [ARM] pxa: skip registers saving/restoring if entering standby mode
  [ARM] pxa: fix PXA27x resume
  [ARM] pxa: Avoid fiddling with CKEN register on suspend
  [ARM] pxa: Add PXA3 standby code hooked into the IRQ wake scheme
  [ARM] pxa: Add zylonite MFP wakeup configurations
  [ARM] pxa: program MFPs for low power mode when suspending
  [ARM] pxa: make MFP configuration processor independent
  [ARM] pxa: remove un-used pxa3xx_mfp_set_xxx() functions
  ...

Conflicts:

	arch/arm/mach-pxa/ssp.c

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2008-01-28 13:21:38 +00:00 committed by Russell King
commit 0ff66f0c7a
88 changed files with 10029 additions and 1844 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/cpu-freq/user-guide.txt
View File

@ -45,6 +45,7 @@ The following ARM processors are supported by cpufreq:
ARM Integrator
ARM-SA1100
ARM-SA1110
Intel PXA
1.2 x86

9
arch/arm/Kconfig
View File

@ -356,6 +356,7 @@ config ARCH_PXA
select GENERIC_GPIO
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select TICK_ONESHOT
help
Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
@ -895,7 +896,7 @@ config KEXEC
endmenu
if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX )
if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
menu "CPU Frequency scaling"
@ -931,6 +932,12 @@ config CPU_FREQ_IMX
If in doubt, say N.
config CPU_FREQ_PXA
bool
depends on CPU_FREQ && ARCH_PXA && PXA25x
default y
select CPU_FREQ_DEFAULT_GOV_USERSPACE
endmenu
endif

1481
arch/arm/configs/colibri_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

1499
arch/arm/configs/eseries_pxa_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

783
arch/arm/configs/littleton_defconfig Normal file
View File

@ -0,0 +1,783 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.24-rc5
# Fri Dec 21 11:06:19 2007
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_MMU=y
# CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ZONE_DMA=y
CONFIG_ARCH_MTD_XIP=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_FAIR_USER_SCHED=y
# CONFIG_FAIR_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
# CONFIG_EMBEDDED is not set
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_KMOD is not set
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
#
# System Type
#
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_PNX4008 is not set
CONFIG_ARCH_PXA=y
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
#
# Intel PXA2xx/PXA3xx Implementations
#
#
# Supported PXA3xx Processor Variants
#
CONFIG_CPU_PXA300=y
CONFIG_CPU_PXA310=y
# CONFIG_CPU_PXA320 is not set
# CONFIG_ARCH_LUBBOCK is not set
# CONFIG_MACH_LOGICPD_PXA270 is not set
# CONFIG_MACH_MAINSTONE is not set
# CONFIG_ARCH_PXA_IDP is not set
# CONFIG_PXA_SHARPSL is not set
# CONFIG_MACH_TRIZEPS4 is not set
# CONFIG_MACH_EM_X270 is not set
# CONFIG_MACH_ZYLONITE is not set
CONFIG_MACH_LITTLETON=y
# CONFIG_MACH_ARMCORE is not set
CONFIG_PXA3xx=y
CONFIG_PXA_SSP=y
#
# Boot options
#
#
# Power management
#
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_XSC3=y
CONFIG_CPU_32v5=y
CONFIG_CPU_ABRT_EV5T=y
CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_TLB_V4WBI=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_IO_36=y
#
# Processor Features
#
# CONFIG_ARM_THUMB is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
# CONFIG_OUTER_CACHE is not set
CONFIG_IWMMXT=y
#
# Bus support
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Kernel Features
#
CONFIG_TICK_ONESHOT=y
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_PREEMPT=y
CONFIG_HZ=100
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
CONFIG_ALIGNMENT_TRAP=y
#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS2,38400 mem=64M"
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set
#
# Floating point emulation
#
#
# At least one emulation must be selected
#
CONFIG_FPE_NWFPE=y
# CONFIG_FPE_NWFPE_XP is not set
# CONFIG_FPE_FASTFPE is not set
#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
#
# Power management options
#
# CONFIG_PM is not set
CONFIG_SUSPEND_UP_POSSIBLE=y
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
# CONFIG_IP_PNP_DHCP is not set
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_FW_LOADER=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
# CONFIG_MTD is not set
# CONFIG_PARPORT is not set
# CONFIG_BLK_DEV is not set
# CONFIG_MISC_DEVICES is not set
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_AX88796 is not set
CONFIG_SMC91X=y
# CONFIG_DM9000 is not set
# CONFIG_SMC911X is not set
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
# CONFIG_B44 is not set
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_ISDN is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_PXA=y
CONFIG_SERIAL_PXA_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_WATCHDOG is not set
#
# Sonics Silicon Backplane
#
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_SM501 is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set
# CONFIG_FB_SYS_FOPS is not set
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set
#
# Frame buffer hardware drivers
#
# CONFIG_FB_S1D13XXX is not set
CONFIG_FB_PXA=y
# CONFIG_FB_PXA_PARAMETERS is not set
# CONFIG_FB_MBX is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_FONTS=y
# CONFIG_FONT_8x8 is not set
CONFIG_FONT_8x16=y
# CONFIG_FONT_6x11 is not set
# CONFIG_FONT_7x14 is not set
# CONFIG_FONT_PEARL_8x8 is not set
# CONFIG_FONT_ACORN_8x8 is not set
# CONFIG_FONT_MINI_4x6 is not set
# CONFIG_FONT_SUN8x16 is not set
# CONFIG_FONT_SUN12x22 is not set
# CONFIG_FONT_10x18 is not set
CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
#
# Sound
#
# CONFIG_SOUND is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_MMC is not set
# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
#
# File systems
#
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_INOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_DNOTIFY is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
# CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFS_DIRECTIO=y
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
# CONFIG_SUNRPC_BIND34 is not set
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_NLS is not set
# CONFIG_DLM is not set
# CONFIG_INSTRUMENTATION is not set
#
# Kernel hacking
#
CONFIG_PRINTK_TIME=y
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SG is not set
CONFIG_FRAME_POINTER=y
CONFIG_FORCED_INLINING=y
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SAMPLES is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_LL=y
# CONFIG_DEBUG_ICEDCC is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_MANAGER=y
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_GF128MUL is not set
# CONFIG_CRYPTO_ECB is not set
CONFIG_CRYPTO_CBC=y
# CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_XTS is not set
# CONFIG_CRYPTO_CRYPTD is not set
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_AES is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_TEST is not set
# CONFIG_CRYPTO_AUTHENC is not set
CONFIG_CRYPTO_HW=y
#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_CRC_CCITT=y
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

1096
arch/arm/configs/pcm027_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

2
arch/arm/mach-omap1/board-fsample.c
View File

@ -76,7 +76,7 @@ static struct resource smc91x_resources[] = {
[1] = {
.start = INT_730_MPU_EXT_NIRQ,
.end = 0,
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
};

2
arch/arm/mach-omap1/board-h2.c
View File

@ -209,7 +209,7 @@ static struct resource h2_smc91x_resources[] = {
[1] = {
.start = OMAP_GPIO_IRQ(0),
.end = OMAP_GPIO_IRQ(0),
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};

2
arch/arm/mach-omap1/board-h3.c
View File

@ -208,7 +208,7 @@ static struct resource smc91x_resources[] = {
[1] = {
.start = OMAP_GPIO_IRQ(40),
.end = OMAP_GPIO_IRQ(40),
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};

4
arch/arm/mach-omap1/board-innovator.c
View File

@ -202,7 +202,7 @@ static struct resource innovator1510_smc91x_resources[] = {
[1] = {
.start = OMAP1510_INT_ETHER,
.end = OMAP1510_INT_ETHER,
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
};
@ -269,7 +269,7 @@ static struct resource innovator1610_smc91x_resources[] = {
[1] = {
.start = OMAP_GPIO_IRQ(0),
.end = OMAP_GPIO_IRQ(0),
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};

2
arch/arm/mach-omap1/board-osk.c
View File

@ -111,7 +111,7 @@ static struct resource osk5912_smc91x_resources[] = {
[1] = {
.start = OMAP_GPIO_IRQ(0),
.end = OMAP_GPIO_IRQ(0),
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
};

2
arch/arm/mach-omap1/board-perseus2.c
View File

@ -75,7 +75,7 @@ static struct resource smc91x_resources[] = {
[1] = {
.start = INT_730_MPU_EXT_NIRQ,
.end = 0,
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
};

2
arch/arm/mach-omap1/board-voiceblue.c
View File

@ -117,7 +117,7 @@ static struct resource voiceblue_smc91x_resources[] = {
[1] = {
.start = OMAP_GPIO_IRQ(8),
.end = OMAP_GPIO_IRQ(8),
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
};

2
arch/arm/mach-omap2/board-2430sdp.c
View File

@ -104,7 +104,7 @@ static struct resource sdp2430_smc91x_resources[] = {
[1] = {
.start = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ),
.end = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ),
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
};

2
arch/arm/mach-omap2/board-apollon.c
View File

@ -126,7 +126,7 @@ static struct resource apollon_smc91x_resources[] = {
[1] = {
.start = OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ),
.end = OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ),
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
};

73
arch/arm/mach-pxa/Kconfig
View File

@ -51,6 +51,50 @@ config PXA_SHARPSL
SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa)
handheld computer.
config ARCH_PXA_ESERIES
bool "PXA based Toshiba e-series PDAs"
select PXA25x
config MACH_E330
bool "Toshiba e330"
default y
depends on ARCH_PXA_ESERIES
help
Say Y here if you intend to run this kernel on a Toshiba
e330 family PDA.
config MACH_E740
bool "Toshiba e740"
default y
depends on ARCH_PXA_ESERIES
help
Say Y here if you intend to run this kernel on a Toshiba
e740 family PDA.
config MACH_E750
bool "Toshiba e750"
default y
depends on ARCH_PXA_ESERIES
help
Say Y here if you intend to run this kernel on a Toshiba
e750 family PDA.
config MACH_E400
bool "Toshiba e400"
default y
depends on ARCH_PXA_ESERIES
help
Say Y here if you intend to run this kernel on a Toshiba
e400 family PDA.
config MACH_E800
bool "Toshiba e800"
default y
depends on ARCH_PXA_ESERIES
help
Say Y here if you intend to run this kernel on a Toshiba
e800 family PDA.
config MACH_TRIZEPS4
bool "Keith und Koep Trizeps4 DIMM-Module"
select PXA27x
@ -59,15 +103,44 @@ config MACH_EM_X270
bool "CompuLab EM-x270 platform"
select PXA27x
config MACH_COLIBRI
bool "Toradex Colibri PX27x"
select PXA27x
config MACH_ZYLONITE
bool "PXA3xx Development Platform"
select PXA3xx
config MACH_LITTLETON
bool "PXA3xx Form Factor Platform (aka Littleton)"
select PXA3xx
select PXA_SSP
config MACH_ARMCORE
bool "CompuLab CM-X270 modules"
select PXA27x
select IWMMXT
config MACH_MAGICIAN
bool "Enable HTC Magician Support"
depends on ARCH_PXA
select PXA27x
select IWMMXT
config MACH_PCM027
bool "Phytec phyCORE-PXA270 CPU module (PCM-027)"
select PXA27x
select IWMMXT
endchoice
choice
prompt "Used baseboard"
depends on MACH_PCM027
config MACH_PCM990_BASEBOARD
bool "PHYTEC PCM-990 development board"
endchoice
if PXA_SHARPSL

15
arch/arm/mach-pxa/Makefile
View File

@ -3,7 +3,7 @@
#
# Common support (must be linked before board specific support)
obj-y += clock.o generic.o irq.o dma.o time.o
obj-y += clock.o devices.o generic.o irq.o dma.o time.o
obj-$(CONFIG_PXA25x) += pxa25x.o
obj-$(CONFIG_PXA27x) += pxa27x.o
obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o
@ -16,18 +16,24 @@ obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o
obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o
obj-$(CONFIG_MACH_COLIBRI) += colibri.o
obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o
obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o
obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o
obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o
obj-$(CONFIG_MACH_PCM027) += pcm027.o
obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o
obj-$(CONFIG_MACH_TOSA) += tosa.o
obj-$(CONFIG_MACH_EM_X270) += em-x270.o
obj-$(CONFIG_MACH_MAGICIAN) += magician.o
obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o
ifeq ($(CONFIG_MACH_ZYLONITE),y)
obj-y += zylonite.o
obj-$(CONFIG_CPU_PXA300) += zylonite_pxa300.o
obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o
endif
obj-$(CONFIG_MACH_LITTLETON) += littleton.o
obj-$(CONFIG_MACH_ARMCORE) += cm-x270.o
@ -41,13 +47,10 @@ led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o
obj-$(CONFIG_LEDS) += $(led-y)
# Misc features
obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_PM) += pm.o sleep.o standby.o
obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
obj-$(CONFIG_PXA_SSP) += ssp.o
ifeq ($(CONFIG_PXA27x),y)
obj-$(CONFIG_PM) += standby.o
endif
ifeq ($(CONFIG_PCI),y)
obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o
endif

7
arch/arm/mach-pxa/cm-x270.c
View File

@ -487,18 +487,15 @@ static int cmx270_mci_init(struct device *dev,
/* card detect IRQ on GPIO 83 */
pxa_gpio_mode(IRQ_TO_GPIO(CMX270_MMC_IRQ));
set_irq_type(CMX270_MMC_IRQ, IRQT_FALLING);
err = request_irq(CMX270_MMC_IRQ, cmx270_detect_int,
IRQF_DISABLED | IRQF_TRIGGER_FALLING,
"MMC card detect", data);
if (err) {
if (err)
printk(KERN_ERR "cmx270_mci_init: MMC/SD: can't"
" request MMC card detect IRQ\n");
return -1;
}
return 0;
return err;
}
static void cmx270_mci_setpower(struct device *dev, unsigned int vdd)

134
arch/arm/mach-pxa/colibri.c Normal file
View File

@ -0,0 +1,134 @@
/*
* linux/arch/arm/mach-pxa/colibri.c
*
* Support for Toradex PXA27x based Colibri module
* Daniel Mack <daniel@caiaq.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <asm/mach-types.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/sizes.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach/flash.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/colibri.h>
#include "generic.h"
#include "devices.h"
/*
* Flash
*/
static struct mtd_partition colibri_partitions[] = {
{
.name = "Bootloader",
.offset = 0x00000000,
.size = 0x00040000,
.mask_flags = MTD_WRITEABLE /* force read-only */
}, {
.name = "Kernel",
.offset = 0x00040000,
.size = 0x00400000,
.mask_flags = 0
}, {
.name = "Rootfs",
.offset = 0x00440000,
.size = MTDPART_SIZ_FULL,
.mask_flags = 0
}
};
static struct physmap_flash_data colibri_flash_data[] = {
{
.width = 4, /* bankwidth in bytes */
.parts = colibri_partitions,
.nr_parts = ARRAY_SIZE(colibri_partitions)
}
};
static struct resource flash_resource = {
.start = PXA_CS0_PHYS,
.end = PXA_CS0_PHYS + SZ_32M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = colibri_flash_data,
},
.resource = &flash_resource,
.num_resources = 1,
};
/*
* DM9000 Ethernet
*/
static struct resource dm9000_resources[] = {
[0] = {
.start = COLIBRI_ETH_PHYS,
.end = COLIBRI_ETH_PHYS + 3,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = COLIBRI_ETH_PHYS + 4,
.end = COLIBRI_ETH_PHYS + 4 + 500,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = COLIBRI_ETH_IRQ,
.end = COLIBRI_ETH_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dm9000_device = {
.name = "dm9000",
.id = -1,
.num_resources = ARRAY_SIZE(dm9000_resources),
.resource = dm9000_resources,
};
static struct platform_device *colibri_devices[] __initdata = {
&flash_device,
&dm9000_device,
};
static void __init colibri_init(void)
{
/* DM9000 LAN */
pxa_gpio_mode(GPIO78_nCS_2_MD);
pxa_gpio_mode(GPIO_DM9000 | GPIO_IN);
set_irq_type(COLIBRI_ETH_IRQ, IRQT_FALLING);
platform_add_devices(colibri_devices, ARRAY_SIZE(colibri_devices));
}
MACHINE_START(COLIBRI, "Toradex Colibri PXA27x")
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = COLIBRI_SDRAM_BASE + 0x100,
.init_machine = colibri_init,
.map_io = pxa_map_io,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
MACHINE_END

185
arch/arm/mach-pxa/corgi.c
View File

@ -21,6 +21,7 @@
#include <linux/mmc/host.h>
#include <linux/pm.h>
#include <linux/backlight.h>
#include <video/w100fb.h>
#include <asm/setup.h>
#include <asm/memory.h>
@ -140,6 +141,136 @@ struct corgissp_machinfo corgi_ssp_machinfo = {
};
/*
* LCD/Framebuffer
*/
static void w100_lcdtg_suspend(struct w100fb_par *par)
{
corgi_lcdtg_suspend();
}
static void w100_lcdtg_init(struct w100fb_par *par)
{
corgi_lcdtg_hw_init(par->xres);
}
static struct w100_tg_info corgi_lcdtg_info = {
.change = w100_lcdtg_init,
.suspend = w100_lcdtg_suspend,
.resume = w100_lcdtg_init,
};
static struct w100_mem_info corgi_fb_mem = {
.ext_cntl = 0x00040003,
.sdram_mode_reg = 0x00650021,
.ext_timing_cntl = 0x10002a4a,
.io_cntl = 0x7ff87012,
.size = 0x1fffff,
};
static struct w100_gen_regs corgi_fb_regs = {
.lcd_format = 0x00000003,
.lcdd_cntl1 = 0x01CC0000,
.lcdd_cntl2 = 0x0003FFFF,
.genlcd_cntl1 = 0x00FFFF0D,
.genlcd_cntl2 = 0x003F3003,
.genlcd_cntl3 = 0x000102aa,
};
static struct w100_gpio_regs corgi_fb_gpio = {
.init_data1 = 0x000000bf,
.init_data2 = 0x00000000,
.gpio_dir1 = 0x00000000,
.gpio_oe1 = 0x03c0feff,
.gpio_dir2 = 0x00000000,
.gpio_oe2 = 0x00000000,
};
static struct w100_mode corgi_fb_modes[] = {
{
.xres = 480,
.yres = 640,
.left_margin = 0x56,
.right_margin = 0x55,
.upper_margin = 0x03,
.lower_margin = 0x00,
.crtc_ss = 0x82360056,
.crtc_ls = 0xA0280000,
.crtc_gs = 0x80280028,
.crtc_vpos_gs = 0x02830002,
.crtc_rev = 0x00400008,
.crtc_dclk = 0xA0000000,
.crtc_gclk = 0x8015010F,
.crtc_goe = 0x80100110,
.crtc_ps1_active = 0x41060010,
.pll_freq = 75,
.fast_pll_freq = 100,
.sysclk_src = CLK_SRC_PLL,
.sysclk_divider = 0,
.pixclk_src = CLK_SRC_PLL,
.pixclk_divider = 2,
.pixclk_divider_rotated = 6,
},{
.xres = 240,
.yres = 320,
.left_margin = 0x27,
.right_margin = 0x2e,
.upper_margin = 0x01,
.lower_margin = 0x00,
.crtc_ss = 0x81170027,
.crtc_ls = 0xA0140000,
.crtc_gs = 0xC0140014,
.crtc_vpos_gs = 0x00010141,
.crtc_rev = 0x00400008,
.crtc_dclk = 0xA0000000,
.crtc_gclk = 0x8015010F,
.crtc_goe = 0x80100110,
.crtc_ps1_active = 0x41060010,
.pll_freq = 0,
.fast_pll_freq = 0,
.sysclk_src = CLK_SRC_XTAL,
.sysclk_divider = 0,
.pixclk_src = CLK_SRC_XTAL,
.pixclk_divider = 1,
.pixclk_divider_rotated = 1,
},
};
static struct w100fb_mach_info corgi_fb_info = {
.tg = &corgi_lcdtg_info,
.init_mode = INIT_MODE_ROTATED,
.mem = &corgi_fb_mem,
.regs = &corgi_fb_regs,
.modelist = &corgi_fb_modes[0],
.num_modes = 2,
.gpio = &corgi_fb_gpio,
.xtal_freq = 12500000,
.xtal_dbl = 0,
};
static struct resource corgi_fb_resources[] = {
[0] = {
.start = 0x08000000,
.end = 0x08ffffff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device corgifb_device = {
.name = "w100fb",
.id = -1,
.num_resources = ARRAY_SIZE(corgi_fb_resources),
.resource = corgi_fb_resources,
.dev = {
.platform_data = &corgi_fb_info,
.parent = &corgissp_device.dev,
},
};
/*
* Corgi Backlight Device
*/
@ -154,6 +285,21 @@ static void corgi_bl_kick_battery(void)
}
}
static void corgi_bl_set_intensity(int intensity)
{
if (intensity > 0x10)
intensity += 0x10;
/* Bits 0-4 are accessed via the SSP interface */
corgi_ssp_blduty_set(intensity & 0x1f);
/* Bit 5 is via SCOOP */
if (intensity & 0x0020)
set_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_BACKLIGHT_CONT);
else
reset_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_BACKLIGHT_CONT);
}
static struct generic_bl_info corgi_bl_machinfo = {
.name = "corgi-bl",
.max_intensity = 0x2f,
@ -190,9 +336,40 @@ static struct platform_device corgiled_device = {
.id = -1,
};
/*
* Corgi Touch Screen Device
*/
static unsigned long (*get_hsync_invperiod)(struct device *dev);
static void inline sharpsl_wait_sync(int gpio)
{
while((GPLR(gpio) & GPIO_bit(gpio)) == 0);
while((GPLR(gpio) & GPIO_bit(gpio)) != 0);
}
static unsigned long corgi_get_hsync_invperiod(void)
{
if (!get_hsync_invperiod)
get_hsync_invperiod = symbol_get(w100fb_get_hsynclen);
if (!get_hsync_invperiod)
return 0;
return get_hsync_invperiod(&corgifb_device.dev);
}
static void corgi_put_hsync(void)
{
if (get_hsync_invperiod)
symbol_put(w100fb_get_hsynclen);
get_hsync_invperiod = NULL;
}
static void corgi_wait_hsync(void)
{
sharpsl_wait_sync(CORGI_GPIO_HSYNC);
}
static struct resource corgits_resources[] = {
[0] = {
.start = CORGI_IRQ_GPIO_TP_INT,
@ -202,7 +379,7 @@ static struct resource corgits_resources[] = {
};
static struct corgits_machinfo corgi_ts_machinfo = {
.get_hsync_len = corgi_get_hsync_len,
.get_hsync_invperiod = corgi_get_hsync_invperiod,
.put_hsync = corgi_put_hsync,
.wait_hsync = corgi_wait_hsync,
};
@ -242,12 +419,10 @@ static int corgi_mci_init(struct device *dev, irq_handler_t corgi_detect_int, vo
err = request_irq(CORGI_IRQ_GPIO_nSD_DETECT, corgi_detect_int,
IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"MMC card detect", data);
if (err) {
if (err)
printk(KERN_ERR "corgi_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
return -1;
}
return 0;
return err;
}
static void corgi_mci_setpower(struct device *dev, unsigned int vdd)

299
arch/arm/mach-pxa/corgi_lcd.c
View File

@ -173,7 +173,7 @@ static void lcdtg_set_phadadj(int mode)
static int lcd_inited;
static void lcdtg_hw_init(int mode)
void corgi_lcdtg_hw_init(int mode)
{
if (!lcd_inited) {
int comadj;
@ -254,7 +254,7 @@ static void lcdtg_hw_init(int mode)
}
}
static void lcdtg_suspend(void)
void corgi_lcdtg_suspend(void)
{
/* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */
mdelay(34);
@ -288,298 +288,3 @@ static void lcdtg_suspend(void)
lcd_inited = 0;
}
/*
* Corgi w100 Frame Buffer Device
*/
#ifdef CONFIG_PXA_SHARP_C7xx
#include <video/w100fb.h>
static void w100_lcdtg_suspend(struct w100fb_par *par)
{
lcdtg_suspend();
}
static void w100_lcdtg_init(struct w100fb_par *par)
{
lcdtg_hw_init(par->xres);
}
static struct w100_tg_info corgi_lcdtg_info = {
.change = w100_lcdtg_init,
.suspend = w100_lcdtg_suspend,
.resume = w100_lcdtg_init,
};
static struct w100_mem_info corgi_fb_mem = {
.ext_cntl = 0x00040003,
.sdram_mode_reg = 0x00650021,
.ext_timing_cntl = 0x10002a4a,
.io_cntl = 0x7ff87012,
.size = 0x1fffff,
};
static struct w100_gen_regs corgi_fb_regs = {
.lcd_format = 0x00000003,
.lcdd_cntl1 = 0x01CC0000,
.lcdd_cntl2 = 0x0003FFFF,
.genlcd_cntl1 = 0x00FFFF0D,
.genlcd_cntl2 = 0x003F3003,
.genlcd_cntl3 = 0x000102aa,
};
static struct w100_gpio_regs corgi_fb_gpio = {
.init_data1 = 0x000000bf,
.init_data2 = 0x00000000,
.gpio_dir1 = 0x00000000,
.gpio_oe1 = 0x03c0feff,
.gpio_dir2 = 0x00000000,
.gpio_oe2 = 0x00000000,
};
static struct w100_mode corgi_fb_modes[] = {
{
.xres = 480,
.yres = 640,
.left_margin = 0x56,
.right_margin = 0x55,
.upper_margin = 0x03,
.lower_margin = 0x00,
.crtc_ss = 0x82360056,
.crtc_ls = 0xA0280000,
.crtc_gs = 0x80280028,
.crtc_vpos_gs = 0x02830002,
.crtc_rev = 0x00400008,
.crtc_dclk = 0xA0000000,
.crtc_gclk = 0x8015010F,
.crtc_goe = 0x80100110,
.crtc_ps1_active = 0x41060010,
.pll_freq = 75,
.fast_pll_freq = 100,
.sysclk_src = CLK_SRC_PLL,
.sysclk_divider = 0,
.pixclk_src = CLK_SRC_PLL,
.pixclk_divider = 2,
.pixclk_divider_rotated = 6,
},{
.xres = 240,
.yres = 320,
.left_margin = 0x27,
.right_margin = 0x2e,
.upper_margin = 0x01,
.lower_margin = 0x00,
.crtc_ss = 0x81170027,
.crtc_ls = 0xA0140000,
.crtc_gs = 0xC0140014,
.crtc_vpos_gs = 0x00010141,
.crtc_rev = 0x00400008,
.crtc_dclk = 0xA0000000,
.crtc_gclk = 0x8015010F,
.crtc_goe = 0x80100110,
.crtc_ps1_active = 0x41060010,
.pll_freq = 0,
.fast_pll_freq = 0,
.sysclk_src = CLK_SRC_XTAL,
.sysclk_divider = 0,
.pixclk_src = CLK_SRC_XTAL,
.pixclk_divider = 1,
.pixclk_divider_rotated = 1,
},
};
static struct w100fb_mach_info corgi_fb_info = {
.tg = &corgi_lcdtg_info,
.init_mode = INIT_MODE_ROTATED,
.mem = &corgi_fb_mem,
.regs = &corgi_fb_regs,
.modelist = &corgi_fb_modes[0],
.num_modes = 2,
.gpio = &corgi_fb_gpio,
.xtal_freq = 12500000,
.xtal_dbl = 0,
};
static struct resource corgi_fb_resources[] = {
[0] = {
.start = 0x08000000,
.end = 0x08ffffff,
.flags = IORESOURCE_MEM,
},
};
struct platform_device corgifb_device = {
.name = "w100fb",
.id = -1,
.num_resources = ARRAY_SIZE(corgi_fb_resources),
.resource = corgi_fb_resources,
.dev = {
.platform_data = &corgi_fb_info,
.parent = &corgissp_device.dev,
},
};
#endif
/*
* Spitz PXA Frame Buffer Device
*/
#ifdef CONFIG_PXA_SHARP_Cxx00
#include <asm/arch/pxafb.h>
void spitz_lcd_power(int on, struct fb_var_screeninfo *var)
{
if (on)
lcdtg_hw_init(var->xres);
else
lcdtg_suspend();
}
#endif
/*
* Corgi/Spitz Touchscreen to LCD interface
*/
static unsigned long (*get_hsync_time)(struct device *dev);
static void inline sharpsl_wait_sync(int gpio)
{
while((GPLR(gpio) & GPIO_bit(gpio)) == 0);
while((GPLR(gpio) & GPIO_bit(gpio)) != 0);
}
#ifdef CONFIG_PXA_SHARP_C7xx
unsigned long corgi_get_hsync_len(void)
{
if (!get_hsync_time)
get_hsync_time = symbol_get(w100fb_get_hsynclen);
if (!get_hsync_time)
return 0;
return get_hsync_time(&corgifb_device.dev);
}
void corgi_put_hsync(void)
{
if (get_hsync_time)
symbol_put(w100fb_get_hsynclen);
get_hsync_time = NULL;
}
void corgi_wait_hsync(void)
{
sharpsl_wait_sync(CORGI_GPIO_HSYNC);
}
#endif
#ifdef CONFIG_PXA_SHARP_Cxx00
static struct device *spitz_pxafb_dev;
static int is_pxafb_device(struct device * dev, void * data)
{
struct platform_device *pdev = container_of(dev, struct platform_device, dev);
return (strncmp(pdev->name, "pxa2xx-fb", 9) == 0);
}
unsigned long spitz_get_hsync_len(void)
{
#ifdef CONFIG_FB_PXA
if (!spitz_pxafb_dev) {
spitz_pxafb_dev = bus_find_device(&platform_bus_type, NULL, NULL, is_pxafb_device);
if (!spitz_pxafb_dev)
return 0;
}
if (!get_hsync_time)
get_hsync_time = symbol_get(pxafb_get_hsync_time);
if (!get_hsync_time)
#endif
return 0;
return pxafb_get_hsync_time(spitz_pxafb_dev);
}
void spitz_put_hsync(void)
{
put_device(spitz_pxafb_dev);
if (get_hsync_time)
symbol_put(pxafb_get_hsync_time);
spitz_pxafb_dev = NULL;
get_hsync_time = NULL;
}
void spitz_wait_hsync(void)
{
sharpsl_wait_sync(SPITZ_GPIO_HSYNC);
}
#endif
/*
* Corgi/Spitz Backlight Power
*/
#ifdef CONFIG_PXA_SHARP_C7xx
void corgi_bl_set_intensity(int intensity)
{
if (intensity > 0x10)
intensity += 0x10;
/* Bits 0-4 are accessed via the SSP interface */
corgi_ssp_blduty_set(intensity & 0x1f);
/* Bit 5 is via SCOOP */
if (intensity & 0x0020)
set_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_BACKLIGHT_CONT);
else
reset_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_BACKLIGHT_CONT);
}
#endif
#if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI)
void spitz_bl_set_intensity(int intensity)
{
if (intensity > 0x10)
intensity += 0x10;
/* Bits 0-4 are accessed via the SSP interface */
corgi_ssp_blduty_set(intensity & 0x1f);
/* Bit 5 is via SCOOP */
if (intensity & 0x0020)
reset_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_CONT);
else
set_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_CONT);
if (intensity)
set_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_ON);
else
reset_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_ON);
}
#endif
#ifdef CONFIG_MACH_AKITA
void akita_bl_set_intensity(int intensity)
{
if (intensity > 0x10)
intensity += 0x10;
/* Bits 0-4 are accessed via the SSP interface */
corgi_ssp_blduty_set(intensity & 0x1f);
/* Bit 5 is via IO-Expander */
if (intensity & 0x0020)
akita_reset_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_CONT);
else
akita_set_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_CONT);
if (intensity)
akita_set_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_ON);
else
akita_reset_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_ON);
}
#endif

1
arch/arm/mach-pxa/corgi_ssp.c
View File

@ -21,6 +21,7 @@
#include <asm/arch/ssp.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/regs-ssp.h>
#include "sharpsl.h"
static DEFINE_SPINLOCK(corgi_ssp_lock);

294
arch/arm/mach-pxa/cpu-pxa.c Normal file
View File

@ -0,0 +1,294 @@
/*
* linux/arch/arm/mach-pxa/cpu-pxa.c
*
* Copyright (C) 2002,2003 Intrinsyc Software
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* History:
* 31-Jul-2002 : Initial version [FB]
* 29-Jan-2003 : added PXA255 support [FB]
* 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
*
* Note:
* This driver may change the memory bus clock rate, but will not do any
* platform specific access timing changes... for example if you have flash
* memory connected to CS0, you will need to register a platform specific
* notifier which will adjust the memory access strobes to maintain a
* minimum strobe width.
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <asm/hardware.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#ifdef DEBUG
static unsigned int freq_debug;
MODULE_PARM(freq_debug, "i");
MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
#else
#define freq_debug 0
#endif
typedef struct {
unsigned int khz;
unsigned int membus;
unsigned int cccr;
unsigned int div2;
} pxa_freqs_t;
/* Define the refresh period in mSec for the SDRAM and the number of rows */
#define SDRAM_TREF 64 /* standard 64ms SDRAM */
#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */
#define MDREFR_DRI(x) (((x) * SDRAM_TREF) / (SDRAM_ROWS * 32))
#define CCLKCFG_TURBO 0x1
#define CCLKCFG_FCS 0x2
#define PXA25x_MIN_FREQ 99500
#define PXA25x_MAX_FREQ 398100
#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
#define MDREFR_DRI_MASK 0xFFF
/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
static pxa_freqs_t pxa255_run_freqs[] =
{
/* CPU MEMBUS CCCR DIV2*/
{ 99500, 99500, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50, SDRAM=50 */
{132700, 132700, 0x123, 1}, /* run=133, turbo=133, PXbus=66, SDRAM=66 */
{199100, 99500, 0x141, 0}, /* run=199, turbo=199, PXbus=99, SDRAM=99 */
{265400, 132700, 0x143, 1}, /* run=265, turbo=265, PXbus=133, SDRAM=66 */
{331800, 165900, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */
{398100, 99500, 0x161, 0}, /* run=398, turbo=398, PXbus=196, SDRAM=99 */
{0,}
};
#define NUM_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1];
/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
static pxa_freqs_t pxa255_turbo_freqs[] =
{
/* CPU MEMBUS CCCR DIV2*/
{ 99500, 99500, 0x121, 1}, /* run=99, turbo= 99, PXbus=50, SDRAM=50 */
{199100, 99500, 0x221, 0}, /* run=99, turbo=199, PXbus=50, SDRAM=99 */
{298500, 99500, 0x321, 0}, /* run=99, turbo=287, PXbus=50, SDRAM=99 */
{298600, 99500, 0x1c1, 0}, /* run=199, turbo=287, PXbus=99, SDRAM=99 */
{398100, 99500, 0x241, 0}, /* run=199, turbo=398, PXbus=99, SDRAM=99 */
{0,}
};
#define NUM_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_TURBO_FREQS+1];
extern unsigned get_clk_frequency_khz(int info);
/* find a valid frequency point */
static int pxa_verify_policy(struct cpufreq_policy *policy)
{
struct cpufreq_frequency_table *pxa_freqs_table;
int ret;
if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
pxa_freqs_table = pxa255_run_freq_table;
} else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
pxa_freqs_table = pxa255_turbo_freq_table;
} else {
printk("CPU PXA: Unknown policy found. "
"Using CPUFREQ_POLICY_PERFORMANCE\n");
pxa_freqs_table = pxa255_run_freq_table;
}
ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
if (freq_debug)
pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
policy->min, policy->max);
return ret;
}
static int pxa_set_target(struct cpufreq_policy *policy,
unsigned int target_freq,
unsigned int relation)
{
struct cpufreq_frequency_table *pxa_freqs_table;
pxa_freqs_t *pxa_freq_settings;
struct cpufreq_freqs freqs;
int idx;
unsigned long flags;
unsigned int unused, preset_mdrefr, postset_mdrefr;
void *ramstart = phys_to_virt(0xa0000000);
/* Get the current policy */
if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
pxa_freq_settings = pxa255_run_freqs;
pxa_freqs_table = pxa255_run_freq_table;
} else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
pxa_freq_settings = pxa255_turbo_freqs;
pxa_freqs_table = pxa255_turbo_freq_table;
} else {
printk("CPU PXA: Unknown policy found. "
"Using CPUFREQ_POLICY_PERFORMANCE\n");
pxa_freq_settings = pxa255_run_freqs;
pxa_freqs_table = pxa255_run_freq_table;
}
/* Lookup the next frequency */
if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
target_freq, relation, &idx)) {
return -EINVAL;
}
freqs.old = policy->cur;
freqs.new = pxa_freq_settings[idx].khz;
freqs.cpu = policy->cpu;
if (freq_debug)
pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
(pxa_freq_settings[idx].membus / 2000) :
(pxa_freq_settings[idx].membus / 1000));
/*
* Tell everyone what we're about to do...
* you should add a notify client with any platform specific
* Vcc changing capability
*/
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
/* Calculate the next MDREFR. If we're slowing down the SDRAM clock
* we need to preset the smaller DRI before the change. If we're speeding
* up we need to set the larger DRI value after the change.
*/
preset_mdrefr = postset_mdrefr = MDREFR;
if ((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) {
preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) |
MDREFR_DRI(pxa_freq_settings[idx].membus);
}
postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) |
MDREFR_DRI(pxa_freq_settings[idx].membus);
/* If we're dividing the memory clock by two for the SDRAM clock, this
* must be set prior to the change. Clearing the divide must be done
* after the change.
*/
if (pxa_freq_settings[idx].div2) {
preset_mdrefr |= MDREFR_DB2_MASK;
postset_mdrefr |= MDREFR_DB2_MASK;
} else {
postset_mdrefr &= ~MDREFR_DB2_MASK;
}
local_irq_save(flags);
/* Set new the CCCR */
CCCR = pxa_freq_settings[idx].cccr;
asm volatile(" \n\
ldr r4, [%1] /* load MDREFR */ \n\
b 2f \n\
.align 5 \n\
1: \n\
str %4, [%1] /* preset the MDREFR */ \n\
mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
str %5, [%1] /* postset the MDREFR */ \n\
\n\
b 3f \n\
2: b 1b \n\
3: nop \n\
"
: "=&r" (unused)
: "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart),
"r" (preset_mdrefr), "r" (postset_mdrefr)
: "r4", "r5");
local_irq_restore(flags);
/*
* Tell everyone what we've just done...
* you should add a notify client with any platform specific
* SDRAM refresh timer adjustments
*/
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
return 0;
}
static int pxa_cpufreq_init(struct cpufreq_policy *policy)
{
int i;
/* set default policy and cpuinfo */
policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
policy->policy = CPUFREQ_POLICY_PERFORMANCE;
policy->cpuinfo.max_freq = PXA25x_MAX_FREQ;
policy->cpuinfo.min_freq = PXA25x_MIN_FREQ;
policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
policy->cur = get_clk_frequency_khz(0); /* current freq */
policy->min = policy->max = policy->cur;
/* Generate the run cpufreq_frequency_table struct */
for (i = 0; i < NUM_RUN_FREQS; i++) {
pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
pxa255_run_freq_table[i].index = i;
}
pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
/* Generate the turbo cpufreq_frequency_table struct */
for (i = 0; i < NUM_TURBO_FREQS; i++) {
pxa255_turbo_freq_table[i].frequency = pxa255_turbo_freqs[i].khz;
pxa255_turbo_freq_table[i].index = i;
}
pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
printk(KERN_INFO "PXA CPU frequency change support initialized\n");
return 0;
}
static struct cpufreq_driver pxa_cpufreq_driver = {
.verify = pxa_verify_policy,
.target = pxa_set_target,
.init = pxa_cpufreq_init,
.name = "PXA25x",
};
static int __init pxa_cpu_init(void)
{
int ret = -ENODEV;
if (cpu_is_pxa25x())
ret = cpufreq_register_driver(&pxa_cpufreq_driver);
return ret;
}
static void __exit pxa_cpu_exit(void)
{
if (cpu_is_pxa25x())
cpufreq_unregister_driver(&pxa_cpufreq_driver);
}
MODULE_AUTHOR ("Intrinsyc Software Inc.");
MODULE_DESCRIPTION ("CPU frequency changing driver for the PXA architecture");
MODULE_LICENSE("GPL");
module_init(pxa_cpu_init);
module_exit(pxa_cpu_exit);

662
arch/arm/mach-pxa/devices.c Normal file
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@ -0,0 +1,662 @@
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <asm/arch/gpio.h>
#include <asm/arch/udc.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/mmc.h>
#include <asm/arch/irda.h>
#include <asm/arch/i2c.h>
#include "devices.h"
void __init pxa_register_device(struct platform_device *dev, void *data)
{
int ret;
dev->dev.platform_data = data;
ret = platform_device_register(dev);
if (ret)
dev_err(&dev->dev, "unable to register device: %d\n", ret);
}
static struct resource pxamci_resources[] = {
[0] = {
.start = 0x41100000,
.end = 0x41100fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_MMC,
.end = IRQ_MMC,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = 21,
.end = 21,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = 22,
.end = 22,
.flags = IORESOURCE_DMA,
},
};
static u64 pxamci_dmamask = 0xffffffffUL;
struct platform_device pxa_device_mci = {
.name = "pxa2xx-mci",
.id = 0,
.dev = {
.dma_mask = &pxamci_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(pxamci_resources),
.resource = pxamci_resources,
};
void __init pxa_set_mci_info(struct pxamci_platform_data *info)
{
pxa_register_device(&pxa_device_mci, info);
}
static struct pxa2xx_udc_mach_info pxa_udc_info;
void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
{
memcpy(&pxa_udc_info, info, sizeof *info);
}
static struct resource pxa2xx_udc_resources[] = {
[0] = {
.start = 0x40600000,
.end = 0x4060ffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_USB,
.end = IRQ_USB,
.flags = IORESOURCE_IRQ,
},
};
static u64 udc_dma_mask = ~(u32)0;
struct platform_device pxa_device_udc = {
.name = "pxa2xx-udc",
.id = -1,
.resource = pxa2xx_udc_resources,
.num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
.dev = {
.platform_data = &pxa_udc_info,
.dma_mask = &udc_dma_mask,
}
};
static struct resource pxafb_resources[] = {
[0] = {
.start = 0x44000000,
.end = 0x4400ffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_LCD,
.end = IRQ_LCD,
.flags = IORESOURCE_IRQ,
},
};
static u64 fb_dma_mask = ~(u64)0;
struct platform_device pxa_device_fb = {
.name = "pxa2xx-fb",
.id = -1,
.dev = {
.dma_mask = &fb_dma_mask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(pxafb_resources),
.resource = pxafb_resources,
};
void __init set_pxa_fb_info(struct pxafb_mach_info *info)
{
pxa_register_device(&pxa_device_fb, info);
}
void __init set_pxa_fb_parent(struct device *parent_dev)
{
pxa_device_fb.dev.parent = parent_dev;
}
static struct resource pxa_resource_ffuart[] = {
{
.start = __PREG(FFUART),
.end = __PREG(FFUART) + 35,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_FFUART,
.end = IRQ_FFUART,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device pxa_device_ffuart= {
.name = "pxa2xx-uart",
.id = 0,
.resource = pxa_resource_ffuart,
.num_resources = ARRAY_SIZE(pxa_resource_ffuart),
};
static struct resource pxa_resource_btuart[] = {
{
.start = __PREG(BTUART),
.end = __PREG(BTUART) + 35,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_BTUART,
.end = IRQ_BTUART,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device pxa_device_btuart = {
.name = "pxa2xx-uart",
.id = 1,
.resource = pxa_resource_btuart,
.num_resources = ARRAY_SIZE(pxa_resource_btuart),
};
static struct resource pxa_resource_stuart[] = {
{
.start = __PREG(STUART),
.end = __PREG(STUART) + 35,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_STUART,
.end = IRQ_STUART,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device pxa_device_stuart = {
.name = "pxa2xx-uart",
.id = 2,
.resource = pxa_resource_stuart,
.num_resources = ARRAY_SIZE(pxa_resource_stuart),
};
static struct resource pxa_resource_hwuart[] = {
{
.start = __PREG(HWUART),
.end = __PREG(HWUART) + 47,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_HWUART,
.end = IRQ_HWUART,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device pxa_device_hwuart = {
.name = "pxa2xx-uart",
.id = 3,
.resource = pxa_resource_hwuart,
.num_resources = ARRAY_SIZE(pxa_resource_hwuart),
};
static struct resource pxai2c_resources[] = {
{
.start = 0x40301680,
.end = 0x403016a3,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_I2C,
.end = IRQ_I2C,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device pxa_device_i2c = {
.name = "pxa2xx-i2c",
.id = 0,
.resource = pxai2c_resources,
.num_resources = ARRAY_SIZE(pxai2c_resources),
};
void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
{
pxa_register_device(&pxa_device_i2c, info);
}
static struct resource pxai2s_resources[] = {
{
.start = 0x40400000,
.end = 0x40400083,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_I2S,
.end = IRQ_I2S,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device pxa_device_i2s = {
.name = "pxa2xx-i2s",
.id = -1,
.resource = pxai2s_resources,
.num_resources = ARRAY_SIZE(pxai2s_resources),
};
static u64 pxaficp_dmamask = ~(u32)0;
struct platform_device pxa_device_ficp = {
.name = "pxa2xx-ir",
.id = -1,
.dev = {
.dma_mask = &pxaficp_dmamask,
.coherent_dma_mask = 0xffffffff,
},
};
void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
{
pxa_register_device(&pxa_device_ficp, info);
}
struct platform_device pxa_device_rtc = {
.name = "sa1100-rtc",
.id = -1,
};
#ifdef CONFIG_PXA25x
static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
static struct resource pxa25x_resource_ssp[] = {
[0] = {
.start = 0x41000000,
.end = 0x4100001f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_SSP,
.end = IRQ_SSP,
.flags = IORESOURCE_IRQ,
},
[2] = {
/* DRCMR for RX */
.start = 13,
.end = 13,
.flags = IORESOURCE_DMA,
},
[3] = {
/* DRCMR for TX */
.start = 14,
.end = 14,
.flags = IORESOURCE_DMA,
},
};
struct platform_device pxa25x_device_ssp = {
.name = "pxa25x-ssp",
.id = 0,
.dev = {
.dma_mask = &pxa25x_ssp_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = pxa25x_resource_ssp,
.num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
};
static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
static struct resource pxa25x_resource_nssp[] = {
[0] = {
.start = 0x41400000,
.end = 0x4140002f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_NSSP,
.end = IRQ_NSSP,
.flags = IORESOURCE_IRQ,
},
[2] = {
/* DRCMR for RX */
.start = 15,
.end = 15,
.flags = IORESOURCE_DMA,
},
[3] = {
/* DRCMR for TX */
.start = 16,
.end = 16,
.flags = IORESOURCE_DMA,
},
};
struct platform_device pxa25x_device_nssp = {
.name = "pxa25x-nssp",
.id = 1,
.dev = {
.dma_mask = &pxa25x_nssp_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = pxa25x_resource_nssp,
.num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
};
static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
static struct resource pxa25x_resource_assp[] = {
[0] = {
.start = 0x41500000,
.end = 0x4150002f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_ASSP,
.end = IRQ_ASSP,
.flags = IORESOURCE_IRQ,
},
[2] = {
/* DRCMR for RX */
.start = 23,
.end = 23,
.flags = IORESOURCE_DMA,
},
[3] = {
/* DRCMR for TX */
.start = 24,
.end = 24,
.flags = IORESOURCE_DMA,
},
};
struct platform_device pxa25x_device_assp = {
/* ASSP is basically equivalent to NSSP */
.name = "pxa25x-nssp",
.id = 2,
.dev = {
.dma_mask = &pxa25x_assp_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = pxa25x_resource_assp,
.num_resources = ARRAY_SIZE(pxa25x_resource_assp),
};
#endif /* CONFIG_PXA25x */
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
static struct resource pxa27x_resource_ohci[] = {
[0] = {
.start = 0x4C000000,
.end = 0x4C00ff6f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_USBH1,
.end = IRQ_USBH1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device pxa27x_device_ohci = {
.name = "pxa27x-ohci",
.id = -1,
.dev = {
.dma_mask = &pxa27x_ohci_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
.resource = pxa27x_resource_ohci,
};
void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
{
pxa_register_device(&pxa27x_device_ohci, info);
}
static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
static struct resource pxa27x_resource_ssp1[] = {
[0] = {
.start = 0x41000000,
.end = 0x4100003f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_SSP,
.end = IRQ_SSP,
.flags = IORESOURCE_IRQ,
},
[2] = {
/* DRCMR for RX */
.start = 13,
.end = 13,
.flags = IORESOURCE_DMA,
},
[3] = {
/* DRCMR for TX */
.start = 14,
.end = 14,
.flags = IORESOURCE_DMA,
},
};
struct platform_device pxa27x_device_ssp1 = {
.name = "pxa27x-ssp",
.id = 0,
.dev = {
.dma_mask = &pxa27x_ssp1_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = pxa27x_resource_ssp1,
.num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
};
static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
static struct resource pxa27x_resource_ssp2[] = {
[0] = {
.start = 0x41700000,
.end = 0x4170003f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_SSP2,
.end = IRQ_SSP2,
.flags = IORESOURCE_IRQ,
},
[2] = {
/* DRCMR for RX */
.start = 15,
.end = 15,
.flags = IORESOURCE_DMA,
},
[3] = {
/* DRCMR for TX */
.start = 16,
.end = 16,
.flags = IORESOURCE_DMA,
},
};
struct platform_device pxa27x_device_ssp2 = {
.name = "pxa27x-ssp",
.id = 1,
.dev = {
.dma_mask = &pxa27x_ssp2_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = pxa27x_resource_ssp2,
.num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
};
static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
static struct resource pxa27x_resource_ssp3[] = {
[0] = {
.start = 0x41900000,
.end = 0x4190003f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_SSP3,
.end = IRQ_SSP3,
.flags = IORESOURCE_IRQ,
},
[2] = {
/* DRCMR for RX */
.start = 66,
.end = 66,
.flags = IORESOURCE_DMA,
},
[3] = {
/* DRCMR for TX */
.start = 67,
.end = 67,
.flags = IORESOURCE_DMA,
},
};
struct platform_device pxa27x_device_ssp3 = {
.name = "pxa27x-ssp",
.id = 2,
.dev = {
.dma_mask = &pxa27x_ssp3_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = pxa27x_resource_ssp3,
.num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
};
#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
#ifdef CONFIG_PXA3xx
static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
static struct resource pxa3xx_resource_ssp4[] = {
[0] = {
.start = 0x41a00000,
.end = 0x41a0003f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_SSP4,
.end = IRQ_SSP4,
.flags = IORESOURCE_IRQ,
},
[2] = {
/* DRCMR for RX */
.start = 2,
.end = 2,
.flags = IORESOURCE_DMA,
},
[3] = {
/* DRCMR for TX */
.start = 3,
.end = 3,
.flags = IORESOURCE_DMA,
},
};
struct platform_device pxa3xx_device_ssp4 = {
/* PXA3xx SSP is basically equivalent to PXA27x */
.name = "pxa27x-ssp",
.id = 3,
.dev = {
.dma_mask = &pxa3xx_ssp4_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = pxa3xx_resource_ssp4,
.num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
};
static struct resource pxa3xx_resources_mci2[] = {
[0] = {
.start = 0x42000000,
.end = 0x42000fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_MMC2,
.end = IRQ_MMC2,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = 93,
.end = 93,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = 94,
.end = 94,
.flags = IORESOURCE_DMA,
},
};
struct platform_device pxa3xx_device_mci2 = {
.name = "pxa2xx-mci",
.id = 1,
.dev = {
.dma_mask = &pxamci_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
.resource = pxa3xx_resources_mci2,
};
void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
{
pxa_register_device(&pxa3xx_device_mci2, info);
}
static struct resource pxa3xx_resources_mci3[] = {
[0] = {
.start = 0x42500000,
.end = 0x42500fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_MMC3,
.end = IRQ_MMC3,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = 100,
.end = 100,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = 101,
.end = 101,
.flags = IORESOURCE_DMA,
},
};
struct platform_device pxa3xx_device_mci3 = {
.name = "pxa2xx-mci",
.id = 2,
.dev = {
.dma_mask = &pxamci_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
.resource = pxa3xx_resources_mci3,
};
void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
{
pxa_register_device(&pxa3xx_device_mci3, info);
}
#endif /* CONFIG_PXA3xx */

12
arch/arm/mach-pxa/devices.h
View File

@ -1,4 +1,6 @@
extern struct platform_device pxa_device_mci;
extern struct platform_device pxa3xx_device_mci2;
extern struct platform_device pxa3xx_device_mci3;
extern struct platform_device pxa_device_udc;
extern struct platform_device pxa_device_fb;
extern struct platform_device pxa_device_ffuart;
@ -12,3 +14,13 @@ extern struct platform_device pxa_device_rtc;
extern struct platform_device pxa27x_device_i2c_power;
extern struct platform_device pxa27x_device_ohci;
extern struct platform_device pxa25x_device_ssp;
extern struct platform_device pxa25x_device_nssp;
extern struct platform_device pxa25x_device_assp;
extern struct platform_device pxa27x_device_ssp1;
extern struct platform_device pxa27x_device_ssp2;
extern struct platform_device pxa27x_device_ssp3;
extern struct platform_device pxa3xx_device_ssp4;
void __init pxa_register_device(struct platform_device *dev, void *data);

101
arch/arm/mach-pxa/eseries.c Normal file
View File

@ -0,0 +1,101 @@
/*
* Hardware definitions for the Toshiba eseries PDAs
*
* Copyright (c) 2003 Ian Molton <spyro@f2s.com>
*
* This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*
*/
#include <linux/init.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
#include <asm/arch/hardware.h>
#include <asm/mach-types.h>
#include <generic.h>
/* Only e800 has 128MB RAM */
static void __init eseries_fixup(struct machine_desc *desc,
struct tag *tags, char **cmdline, struct meminfo *mi)
{
mi->nr_banks=1;
mi->bank[0].start = 0xa0000000;
mi->bank[0].node = 0;
if (machine_is_e800())
mi->bank[0].size = (128*1024*1024);
else
mi->bank[0].size = (64*1024*1024);
}
/* e-series machine definitions */
#ifdef CONFIG_MACH_E330
MACHINE_START(E330, "Toshiba e330")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.timer = &pxa_timer,
MACHINE_END
#endif
#ifdef CONFIG_MACH_E740
MACHINE_START(E740, "Toshiba e740")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.timer = &pxa_timer,
MACHINE_END
#endif
#ifdef CONFIG_MACH_E750
MACHINE_START(E750, "Toshiba e750")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.timer = &pxa_timer,
MACHINE_END
#endif
#ifdef CONFIG_MACH_E400
MACHINE_START(E400, "Toshiba e400")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.timer = &pxa_timer,
MACHINE_END
#endif
#ifdef CONFIG_MACH_E800
MACHINE_START(E800, "Toshiba e800")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.timer = &pxa_timer,
MACHINE_END
#endif

251
arch/arm/mach-pxa/generic.c
View File

@ -20,7 +20,6 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/ioport.h>
#include <linux/pm.h>
#include <linux/string.h>
@ -33,13 +32,7 @@
#include <asm/arch/pxa-regs.h>
#include <asm/arch/gpio.h>
#include <asm/arch/udc.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/mmc.h>
#include <asm/arch/irda.h>
#include <asm/arch/i2c.h>
#include "devices.h"
#include "generic.h"
/*
@ -203,7 +196,7 @@ static struct map_desc standard_io_desc[] __initdata = {
}, { /* Mem Ctl */
.virtual = 0xf6000000,
.pfn = __phys_to_pfn(0x48000000),
.length = 0x00100000,
.length = 0x00200000,
.type = MT_DEVICE
}, { /* USB host */
.virtual = 0xf8000000,
@ -233,245 +226,3 @@ void __init pxa_map_io(void)
iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
get_clk_frequency_khz(1);
}
static struct resource pxamci_resources[] = {
[0] = {
.start = 0x41100000,
.end = 0x41100fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_MMC,
.end = IRQ_MMC,
.flags = IORESOURCE_IRQ,
},
};
static u64 pxamci_dmamask = 0xffffffffUL;
struct platform_device pxa_device_mci = {
.name = "pxa2xx-mci",
.id = -1,
.dev = {
.dma_mask = &pxamci_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(pxamci_resources),
.resource = pxamci_resources,
};
void __init pxa_set_mci_info(struct pxamci_platform_data *info)
{
pxa_device_mci.dev.platform_data = info;
}
static struct pxa2xx_udc_mach_info pxa_udc_info;
void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
{
memcpy(&pxa_udc_info, info, sizeof *info);
}
static struct resource pxa2xx_udc_resources[] = {
[0] = {
.start = 0x40600000,
.end = 0x4060ffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_USB,
.end = IRQ_USB,
.flags = IORESOURCE_IRQ,
},
};
static u64 udc_dma_mask = ~(u32)0;
struct platform_device pxa_device_udc = {
.name = "pxa2xx-udc",
.id = -1,
.resource = pxa2xx_udc_resources,
.num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
.dev = {
.platform_data = &pxa_udc_info,
.dma_mask = &udc_dma_mask,
}
};
static struct resource pxafb_resources[] = {
[0] = {
.start = 0x44000000,
.end = 0x4400ffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_LCD,
.end = IRQ_LCD,
.flags = IORESOURCE_IRQ,
},
};
static u64 fb_dma_mask = ~(u64)0;
struct platform_device pxa_device_fb = {
.name = "pxa2xx-fb",
.id = -1,
.dev = {
.dma_mask = &fb_dma_mask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(pxafb_resources),
.resource = pxafb_resources,
};
void __init set_pxa_fb_info(struct pxafb_mach_info *info)
{
pxa_device_fb.dev.platform_data = info;
}
void __init set_pxa_fb_parent(struct device *parent_dev)
{
pxa_device_fb.dev.parent = parent_dev;
}
static struct resource pxa_resource_ffuart[] = {
{
.start = __PREG(FFUART),
.end = __PREG(FFUART) + 35,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_FFUART,
.end = IRQ_FFUART,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device pxa_device_ffuart= {
.name = "pxa2xx-uart",
.id = 0,
.resource = pxa_resource_ffuart,
.num_resources = ARRAY_SIZE(pxa_resource_ffuart),
};
static struct resource pxa_resource_btuart[] = {
{
.start = __PREG(BTUART),
.end = __PREG(BTUART) + 35,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_BTUART,
.end = IRQ_BTUART,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device pxa_device_btuart = {
.name = "pxa2xx-uart",
.id = 1,
.resource = pxa_resource_btuart,
.num_resources = ARRAY_SIZE(pxa_resource_btuart),
};
static struct resource pxa_resource_stuart[] = {
{
.start = __PREG(STUART),
.end = __PREG(STUART) + 35,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_STUART,
.end = IRQ_STUART,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device pxa_device_stuart = {
.name = "pxa2xx-uart",
.id = 2,
.resource = pxa_resource_stuart,
.num_resources = ARRAY_SIZE(pxa_resource_stuart),
};
static struct resource pxa_resource_hwuart[] = {
{
.start = __PREG(HWUART),
.end = __PREG(HWUART) + 47,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_HWUART,
.end = IRQ_HWUART,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device pxa_device_hwuart = {
.name = "pxa2xx-uart",
.id = 3,
.resource = pxa_resource_hwuart,
.num_resources = ARRAY_SIZE(pxa_resource_hwuart),
};
static struct resource pxai2c_resources[] = {
{
.start = 0x40301680,
.end = 0x403016a3,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_I2C,
.end = IRQ_I2C,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device pxa_device_i2c = {
.name = "pxa2xx-i2c",
.id = 0,
.resource = pxai2c_resources,
.num_resources = ARRAY_SIZE(pxai2c_resources),
};
void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
{
pxa_device_i2c.dev.platform_data = info;
}
static struct resource pxai2s_resources[] = {
{
.start = 0x40400000,
.end = 0x40400083,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_I2S,
.end = IRQ_I2S,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device pxa_device_i2s = {
.name = "pxa2xx-i2s",
.id = -1,
.resource = pxai2s_resources,
.num_resources = ARRAY_SIZE(pxai2s_resources),
};
static u64 pxaficp_dmamask = ~(u32)0;
struct platform_device pxa_device_ficp = {
.name = "pxa2xx-ir",
.id = -1,
.dev = {
.dma_mask = &pxaficp_dmamask,
.coherent_dma_mask = 0xffffffff,
},
};
void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
{
pxa_device_ficp.dev.platform_data = info;
}
struct platform_device pxa_device_rtc = {
.name = "sa1100-rtc",
.id = -1,
};

2
arch/arm/mach-pxa/idp.c
View File

@ -54,7 +54,7 @@ static struct resource smc91x_resources[] = {
[1] = {
.start = IRQ_GPIO(4),
.end = IRQ_GPIO(4),
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
}
};

325
arch/arm/mach-pxa/littleton.c Normal file
View File

@ -0,0 +1,325 @@
/*
* linux/arch/arm/mach-pxa/littleton.c
*
* Support for the Marvell Littleton Development Platform.
*
* Author: Jason Chagas (largely modified code)
* Created: Nov 20, 2006
* Copyright: (C) Copyright 2006 Marvell International Ltd.
*
* 2007-11-22 modified to align with latest kernel
* eric miao <eric.miao@marvell.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/mach-types.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/mfp-pxa300.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/ssp.h>
#include <asm/arch/littleton.h>
#include "generic.h"
#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
/* Littleton MFP configurations */
static mfp_cfg_t littleton_mfp_cfg[] __initdata = {
/* LCD */
GPIO54_LCD_LDD_0,
GPIO55_LCD_LDD_1,
GPIO56_LCD_LDD_2,
GPIO57_LCD_LDD_3,
GPIO58_LCD_LDD_4,
GPIO59_LCD_LDD_5,
GPIO60_LCD_LDD_6,
GPIO61_LCD_LDD_7,
GPIO62_LCD_LDD_8,
GPIO63_LCD_LDD_9,
GPIO64_LCD_LDD_10,
GPIO65_LCD_LDD_11,
GPIO66_LCD_LDD_12,
GPIO67_LCD_LDD_13,
GPIO68_LCD_LDD_14,
GPIO69_LCD_LDD_15,
GPIO70_LCD_LDD_16,
GPIO71_LCD_LDD_17,
GPIO72_LCD_FCLK,
GPIO73_LCD_LCLK,
GPIO74_LCD_PCLK,
GPIO75_LCD_BIAS,
/* SSP2 */
GPIO25_SSP2_SCLK,
GPIO17_SSP2_FRM,
GPIO27_SSP2_TXD,
/* Debug Ethernet */
GPIO90_GPIO,
};
static struct resource smc91x_resources[] = {
[0] = {
.start = (LITTLETON_ETH_PHYS + 0x300),
.end = (LITTLETON_ETH_PHYS + 0xfffff),
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)),
.end = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
}
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULES)
/* use bit 30, 31 as the indicator of command parameter number */
#define CMD0(x) ((0x00000000) | ((x) << 9))
#define CMD1(x, x1) ((0x40000000) | ((x) << 9) | 0x100 | (x1))
#define CMD2(x, x1, x2) ((0x80000000) | ((x) << 18) | 0x20000 |\
((x1) << 9) | 0x100 | (x2))
static uint32_t lcd_panel_reset[] = {
CMD0(0x1), /* reset */
CMD0(0x0), /* nop */
CMD0(0x0), /* nop */
CMD0(0x0), /* nop */
};
static uint32_t lcd_panel_on[] = {
CMD0(0x29), /* Display ON */
CMD2(0xB8, 0xFF, 0xF9), /* Output Control */
CMD0(0x11), /* Sleep out */
CMD1(0xB0, 0x16), /* Wake */
};
static uint32_t lcd_panel_off[] = {
CMD0(0x28), /* Display OFF */
CMD2(0xB8, 0x80, 0x02), /* Output Control */
CMD0(0x10), /* Sleep in */
CMD1(0xB0, 0x00), /* Deep stand by in */
};
static uint32_t lcd_vga_pass_through[] = {
CMD1(0xB0, 0x16),
CMD1(0xBC, 0x80),
CMD1(0xE1, 0x00),
CMD1(0x36, 0x50),
CMD1(0x3B, 0x00),
};
static uint32_t lcd_qvga_pass_through[] = {
CMD1(0xB0, 0x16),
CMD1(0xBC, 0x81),
CMD1(0xE1, 0x00),
CMD1(0x36, 0x50),
CMD1(0x3B, 0x22),
};
static uint32_t lcd_vga_transfer[] = {
CMD1(0xcf, 0x02), /* Blanking period control (1) */
CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
CMD1(0xd1, 0x01), /* CKV timing control on/off */
CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
CMD1(0xd5, 0x14), /* ASW timing control (2) */
CMD0(0x21), /* Invert for normally black display */
CMD0(0x29), /* Display on */
};
static uint32_t lcd_qvga_transfer[] = {
CMD1(0xd6, 0x02), /* Blanking period control (1) */
CMD2(0xd7, 0x08, 0x04), /* Blanking period control (2) */
CMD1(0xd8, 0x01), /* CKV timing control on/off */
CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
CMD2(0xde, 0x05, 0x0a), /* OEV timing control */
CMD2(0xdf, 0x0a, 0x19), /* ASW timing control (1) */
CMD1(0xe0, 0x0a), /* ASW timing control (2) */
CMD0(0x21), /* Invert for normally black display */
CMD0(0x29), /* Display on */
};
static uint32_t lcd_panel_config[] = {
CMD2(0xb8, 0xff, 0xf9), /* Output control */
CMD0(0x11), /* sleep out */
CMD1(0xba, 0x01), /* Display mode (1) */
CMD1(0xbb, 0x00), /* Display mode (2) */
CMD1(0x3a, 0x60), /* Display mode 18-bit RGB */
CMD1(0xbf, 0x10), /* Drive system change control */
CMD1(0xb1, 0x56), /* Booster operation setup */
CMD1(0xb2, 0x33), /* Booster mode setup */
CMD1(0xb3, 0x11), /* Booster frequency setup */
CMD1(0xb4, 0x02), /* Op amp/system clock */
CMD1(0xb5, 0x35), /* VCS voltage */
CMD1(0xb6, 0x40), /* VCOM voltage */
CMD1(0xb7, 0x03), /* External display signal */
CMD1(0xbd, 0x00), /* ASW slew rate */
CMD1(0xbe, 0x00), /* Dummy data for QuadData operation */
CMD1(0xc0, 0x11), /* Sleep out FR count (A) */
CMD1(0xc1, 0x11), /* Sleep out FR count (B) */
CMD1(0xc2, 0x11), /* Sleep out FR count (C) */
CMD2(0xc3, 0x20, 0x40), /* Sleep out FR count (D) */
CMD2(0xc4, 0x60, 0xc0), /* Sleep out FR count (E) */
CMD2(0xc5, 0x10, 0x20), /* Sleep out FR count (F) */
CMD1(0xc6, 0xc0), /* Sleep out FR count (G) */
CMD2(0xc7, 0x33, 0x43), /* Gamma 1 fine tuning (1) */
CMD1(0xc8, 0x44), /* Gamma 1 fine tuning (2) */
CMD1(0xc9, 0x33), /* Gamma 1 inclination adjustment */
CMD1(0xca, 0x00), /* Gamma 1 blue offset adjustment */
CMD2(0xec, 0x01, 0xf0), /* Horizontal clock cycles */
};
static void ssp_reconfig(struct ssp_dev *dev, int nparam)
{
static int last_nparam = -1;
/* check if it is necessary to re-config SSP */
if (nparam == last_nparam)
return;
ssp_disable(dev);
ssp_config(dev, (nparam == 2) ? 0x0010058a : 0x00100581, 0x18, 0, 0);
last_nparam = nparam;
}
static void ssp_send_cmd(uint32_t *cmd, int num)
{
static int ssp_initialized;
static struct ssp_dev ssp2;
int i;
if (!ssp_initialized) {
ssp_init(&ssp2, 2, SSP_NO_IRQ);
ssp_initialized = 1;
}
clk_enable(ssp2.ssp->clk);
for (i = 0; i < num; i++, cmd++) {
ssp_reconfig(&ssp2, (*cmd >> 30) & 0x3);
ssp_write_word(&ssp2, *cmd & 0x3fffffff);
/* FIXME: ssp_flush() is mandatory here to work */
ssp_flush(&ssp2);
}
clk_disable(ssp2.ssp->clk);
}
static void littleton_lcd_power(int on, struct fb_var_screeninfo *var)
{
if (on) {
ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_on));
ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_reset));
if (var->xres > 240) {
/* VGA */
ssp_send_cmd(ARRAY_AND_SIZE(lcd_vga_pass_through));
ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_config));
ssp_send_cmd(ARRAY_AND_SIZE(lcd_vga_transfer));
} else {
/* QVGA */
ssp_send_cmd(ARRAY_AND_SIZE(lcd_qvga_pass_through));
ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_config));
ssp_send_cmd(ARRAY_AND_SIZE(lcd_qvga_transfer));
}
} else
ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_off));
}
static struct pxafb_mode_info tpo_tdo24mtea1_modes[] = {
[0] = {
/* VGA */
.pixclock = 38250,
.xres = 480,
.yres = 640,
.bpp = 16,
.hsync_len = 8,
.left_margin = 8,
.right_margin = 24,
.vsync_len = 2,
.upper_margin = 2,
.lower_margin = 4,
.sync = 0,
},
[1] = {
/* QVGA */
.pixclock = 153000,
.xres = 240,
.yres = 320,
.bpp = 16,
.hsync_len = 8,
.left_margin = 8,
.right_margin = 88,
.vsync_len = 2,
.upper_margin = 2,
.lower_margin = 2,
.sync = 0,
},
};
static struct pxafb_mach_info littleton_lcd_info = {
.modes = tpo_tdo24mtea1_modes,
.num_modes = 2,
.lccr0 = LCCR0_Act,
.lccr3 = LCCR3_HSP | LCCR3_VSP,
.pxafb_lcd_power = littleton_lcd_power,
};
static void littleton_init_lcd(void)
{
set_pxa_fb_info(&littleton_lcd_info);
}
#else
static inline void littleton_init_lcd(void) {};
#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULES */
static void __init littleton_init(void)
{
/* initialize MFP configurations */
pxa3xx_mfp_config(ARRAY_AND_SIZE(littleton_mfp_cfg));
/*
* Note: we depend bootloader set the correct
* value to MSC register for SMC91x.
*/
platform_device_register(&smc91x_device);
littleton_init_lcd();
}
MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)")
.phys_io = 0x40000000,
.boot_params = 0xa0000100,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.map_io = pxa_map_io,
.init_irq = pxa3xx_init_irq,
.timer = &pxa_timer,
.init_machine = littleton_init,
MACHINE_END

1
arch/arm/mach-pxa/lpd270.c
View File

@ -38,6 +38,7 @@
#include <asm/mach/flash.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/lpd270.h>
#include <asm/arch/audio.h>
#include <asm/arch/pxafb.h>

26
arch/arm/mach-pxa/lubbock.c
View File

@ -41,6 +41,7 @@
#include <asm/hardware/sa1111.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/lubbock.h>
#include <asm/arch/udc.h>
#include <asm/arch/irda.h>
@ -136,9 +137,13 @@ static struct sys_device lubbock_irq_device = {
static int __init lubbock_irq_device_init(void)
{
int ret = sysdev_class_register(&lubbock_irq_sysclass);
int ret = -ENODEV;
if (machine_is_lubbock()) {
ret = sysdev_class_register(&lubbock_irq_sysclass);
if (ret == 0)
ret = sysdev_register(&lubbock_irq_device);
}
return ret;
}
@ -191,7 +196,7 @@ static struct resource smc91x_resources[] = {
[1] = {
.start = LUBBOCK_ETH_IRQ,
.end = LUBBOCK_ETH_IRQ,
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
[2] = {
.name = "smc91x-attrib",
@ -206,30 +211,13 @@ static struct resource smc91x_resources[] = {
* (to J5) and poking board registers (as done below). Else it's only useful
* for the temperature sensors.
*/
static struct resource pxa_ssp_resources[] = {
[0] = {
.start = __PREG(SSCR0_P(1)),
.end = __PREG(SSCR0_P(1)) + 0x14,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_SSP,
.end = IRQ_SSP,
.flags = IORESOURCE_IRQ,
},
};
static struct pxa2xx_spi_master pxa_ssp_master_info = {
.ssp_type = PXA25x_SSP,
.clock_enable = CKEN_SSP,
.num_chipselect = 0,
};
static struct platform_device pxa_ssp = {
.name = "pxa2xx-spi",
.id = 1,
.resource = pxa_ssp_resources,
.num_resources = ARRAY_SIZE(pxa_ssp_resources),
.dev = {
.platform_data = &pxa_ssp_master_info,
},

218
arch/arm/mach-pxa/magician.c Normal file
View File

@ -0,0 +1,218 @@
/*
* Support for HTC Magician PDA phones:
* i-mate JAM, O2 Xda mini, Orange SPV M500, Qtek s100, Qtek s110
* and T-Mobile MDA Compact.
*
* Copyright (c) 2006-2007 Philipp Zabel
*
* Based on hx4700.c, spitz.c and others.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/physmap.h>
#include <asm/gpio.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/arch/magician.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/irda.h>
#include <asm/arch/ohci.h>
#include "generic.h"
/*
* IRDA
*/
static void magician_irda_transceiver_mode(struct device *dev, int mode)
{
gpio_set_value(GPIO83_MAGICIAN_nIR_EN, mode & IR_OFF);
}
static struct pxaficp_platform_data magician_ficp_info = {
.transceiver_cap = IR_SIRMODE | IR_OFF,
.transceiver_mode = magician_irda_transceiver_mode,
};
/*
* GPIO Keys
*/
static struct gpio_keys_button magician_button_table[] = {
{KEY_POWER, GPIO0_MAGICIAN_KEY_POWER, 0, "Power button"},
{KEY_ESC, GPIO37_MAGICIAN_KEY_HANGUP, 0, "Hangup button"},
{KEY_F10, GPIO38_MAGICIAN_KEY_CONTACTS, 0, "Contacts button"},
{KEY_CALENDAR, GPIO90_MAGICIAN_KEY_CALENDAR, 0, "Calendar button"},
{KEY_CAMERA, GPIO91_MAGICIAN_KEY_CAMERA, 0, "Camera button"},
{KEY_UP, GPIO93_MAGICIAN_KEY_UP, 0, "Up button"},
{KEY_DOWN, GPIO94_MAGICIAN_KEY_DOWN, 0, "Down button"},
{KEY_LEFT, GPIO95_MAGICIAN_KEY_LEFT, 0, "Left button"},
{KEY_RIGHT, GPIO96_MAGICIAN_KEY_RIGHT, 0, "Right button"},
{KEY_KPENTER, GPIO97_MAGICIAN_KEY_ENTER, 0, "Action button"},
{KEY_RECORD, GPIO98_MAGICIAN_KEY_RECORD, 0, "Record button"},
{KEY_VOLUMEUP, GPIO100_MAGICIAN_KEY_VOL_UP, 0, "Volume up"},
{KEY_VOLUMEDOWN, GPIO101_MAGICIAN_KEY_VOL_DOWN, 0, "Volume down"},
{KEY_PHONE, GPIO102_MAGICIAN_KEY_PHONE, 0, "Phone button"},
{KEY_PLAY, GPIO99_MAGICIAN_HEADPHONE_IN, 0, "Headset button"},
};
static struct gpio_keys_platform_data gpio_keys_data = {
.buttons = magician_button_table,
.nbuttons = ARRAY_SIZE(magician_button_table),
};
static struct platform_device gpio_keys = {
.name = "gpio-keys",
.dev = {
.platform_data = &gpio_keys_data,
},
.id = -1,
};
/*
* LCD - Toppoly TD028STEB1
*/
static struct pxafb_mode_info toppoly_modes[] = {
{
.pixclock = 96153,
.bpp = 16,
.xres = 240,
.yres = 320,
.hsync_len = 11,
.vsync_len = 3,
.left_margin = 19,
.upper_margin = 2,
.right_margin = 10,
.lower_margin = 2,
.sync = 0,
},
};
static struct pxafb_mach_info toppoly_info = {
.modes = toppoly_modes,
.num_modes = 1,
.fixed_modes = 1,
.lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
.lccr3 = LCCR3_PixRsEdg,
};
/*
* Backlight
*/
static void magician_set_bl_intensity(int intensity)
{
if (intensity) {
PWM_CTRL0 = 1;
PWM_PERVAL0 = 0xc8;
PWM_PWDUTY0 = intensity;
pxa_set_cken(CKEN_PWM0, 1);
} else {
pxa_set_cken(CKEN_PWM0, 0);
}
}
static struct generic_bl_info backlight_info = {
.default_intensity = 0x64,
.limit_mask = 0x0b,
.max_intensity = 0xc7,
.set_bl_intensity = magician_set_bl_intensity,
};
static struct platform_device backlight = {
.name = "corgi-bl",
.dev = {
.platform_data = &backlight_info,
},
.id = -1,
};
/*
* USB OHCI
*/
static int magician_ohci_init(struct device *dev)
{
UHCHR = (UHCHR | UHCHR_SSEP2 | UHCHR_PCPL | UHCHR_CGR) &
~(UHCHR_SSEP1 | UHCHR_SSEP3 | UHCHR_SSE);
return 0;
}
static struct pxaohci_platform_data magician_ohci_info = {
.port_mode = PMM_PERPORT_MODE,
.init = magician_ohci_init,
.power_budget = 0,
};
/*
* StrataFlash
*/
#define PXA_CS_SIZE 0x04000000
static struct resource strataflash_resource = {
.start = PXA_CS0_PHYS,
.end = PXA_CS0_PHYS + PXA_CS_SIZE - 1,
.flags = IORESOURCE_MEM,
};
static struct physmap_flash_data strataflash_data = {
.width = 4,
};
static struct platform_device strataflash = {
.name = "physmap-flash",
.id = -1,
.num_resources = 1,
.resource = &strataflash_resource,
.dev = {
.platform_data = &strataflash_data,
},
};
/*
* Platform devices
*/
static struct platform_device *devices[] __initdata = {
&gpio_keys,
&backlight,
&strataflash,
};
static void __init magician_init(void)
{
platform_add_devices(devices, ARRAY_SIZE(devices));
pxa_set_ohci_info(&magician_ohci_info);
pxa_set_ficp_info(&magician_ficp_info);
set_pxa_fb_info(&toppoly_info);
}
MACHINE_START(MAGICIAN, "HTC Magician")
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa27x_init_irq,
.init_machine = magician_init,
.timer = &pxa_timer,
MACHINE_END

77
arch/arm/mach-pxa/mainstone.c
View File

@ -23,6 +23,7 @@
#include <linux/ioport.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/backlight.h>
#include <asm/types.h>
#include <asm/setup.h>
@ -38,6 +39,7 @@
#include <asm/mach/flash.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/mainstone.h>
#include <asm/arch/audio.h>
#include <asm/arch/pxafb.h>
@ -130,9 +132,13 @@ static struct sys_device mainstone_irq_device = {
static int __init mainstone_irq_device_init(void)
{
int ret = sysdev_class_register(&mainstone_irq_sysclass);
int ret = -ENODEV;
if (machine_is_mainstone()) {
ret = sysdev_class_register(&mainstone_irq_sysclass);
if (ret == 0)
ret = sysdev_register(&mainstone_irq_device);
}
return ret;
}
@ -150,7 +156,7 @@ static struct resource smc91x_resources[] = {
[1] = {
.start = MAINSTONE_IRQ(3),
.end = MAINSTONE_IRQ(3),
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
}
};
@ -263,22 +269,61 @@ static struct platform_device mst_flash_device[2] = {
},
};
static void mainstone_backlight_power(int on)
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
static int mainstone_backlight_update_status(struct backlight_device *bl)
{
if (on) {
int brightness = bl->props.brightness;
if (bl->props.power != FB_BLANK_UNBLANK ||
bl->props.fb_blank != FB_BLANK_UNBLANK)
brightness = 0;
if (brightness != 0) {
pxa_gpio_mode(GPIO16_PWM0_MD);
pxa_set_cken(CKEN_PWM0, 1);
PWM_CTRL0 = 0;
PWM_PWDUTY0 = 0x3ff;
PWM_PERVAL0 = 0x3ff;
} else {
PWM_CTRL0 = 0;
PWM_PWDUTY0 = 0x0;
PWM_PERVAL0 = 0x3FF;
pxa_set_cken(CKEN_PWM0, 0);
}
PWM_CTRL0 = 0;
PWM_PWDUTY0 = brightness;
PWM_PERVAL0 = bl->props.max_brightness;
if (brightness == 0)
pxa_set_cken(CKEN_PWM0, 0);
return 0; /* pointless return value */
}
static int mainstone_backlight_get_brightness(struct backlight_device *bl)
{
return PWM_PWDUTY0;
}
static /*const*/ struct backlight_ops mainstone_backlight_ops = {
.update_status = mainstone_backlight_update_status,
.get_brightness = mainstone_backlight_get_brightness,
};
static void __init mainstone_backlight_register(void)
{
struct backlight_device *bl;
bl = backlight_device_register("mainstone-bl", &pxa_device_fb.dev,
NULL, &mainstone_backlight_ops);
if (IS_ERR(bl)) {
printk(KERN_ERR "mainstone: unable to register backlight: %ld\n",
PTR_ERR(bl));
return;
}
/*
* broken design - register-then-setup interfaces are
* utterly broken by definition.
*/
bl->props.max_brightness = 1023;
bl->props.brightness = 1023;
backlight_update_status(bl);
}
#else
#define mainstone_backlight_register() do { } while (0)
#endif
static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
.pixclock = 50000,
.xres = 640,
@ -311,7 +356,6 @@ static struct pxafb_mach_info mainstone_pxafb_info = {
.num_modes = 1,
.lccr0 = LCCR0_Act,
.lccr3 = LCCR3_PCP,
.pxafb_backlight_power = mainstone_backlight_power,
};
static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_int, void *data)
@ -335,12 +379,10 @@ static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_in
err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, IRQF_DISABLED,
"MMC card detect", data);
if (err) {
if (err)
printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
return -1;
}
return 0;
return err;
}
static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
@ -473,6 +515,7 @@ static void __init mainstone_init(void)
mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode;
set_pxa_fb_info(&mainstone_pxafb_info);
mainstone_backlight_register();
pxa_set_mci_info(&mainstone_mci_platform_data);
pxa_set_ficp_info(&mainstone_ficp_platform_data);

263
arch/arm/mach-pxa/mfp.c
View File

@ -17,9 +17,11 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/sysdev.h>
#include <asm/hardware.h>
#include <asm/arch/mfp.h>
#include <asm/arch/mfp-pxa3xx.h>
/* mfp_spin_lock is used to ensure that MFP register configuration
* (most likely a read-modify-write operation) is atomic, and that
@ -28,43 +30,110 @@
static DEFINE_SPINLOCK(mfp_spin_lock);
static void __iomem *mfpr_mmio_base = (void __iomem *)&__REG(MFPR_BASE);
struct pxa3xx_mfp_pin {
unsigned long config; /* -1 for not configured */
unsigned long mfpr_off; /* MFPRxx Register offset */
unsigned long mfpr_run; /* Run-Mode Register Value */
unsigned long mfpr_lpm; /* Low Power Mode Register Value */
};
static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX];
/* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */
const static unsigned long mfpr_lpm[] = {
MFPR_LPM_INPUT,
MFPR_LPM_DRIVE_LOW,
MFPR_LPM_DRIVE_HIGH,
MFPR_LPM_PULL_LOW,
MFPR_LPM_PULL_HIGH,
MFPR_LPM_FLOAT,
};
/* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */
const static unsigned long mfpr_pull[] = {
MFPR_PULL_NONE,
MFPR_PULL_LOW,
MFPR_PULL_HIGH,
MFPR_PULL_BOTH,
};
/* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */
const static unsigned long mfpr_edge[] = {
MFPR_EDGE_NONE,
MFPR_EDGE_RISE,
MFPR_EDGE_FALL,
MFPR_EDGE_BOTH,
};
#define mfpr_readl(off) \
__raw_readl(mfpr_mmio_base + (off))
#define mfpr_writel(off, val) \
__raw_writel(val, mfpr_mmio_base + (off))
#define mfp_configured(p) ((p)->config != -1)
/*
* perform a read-back of any MFPR register to make sure the
* previous writings are finished
*/
#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0)
static inline void __mfp_config(int pin, unsigned long val)
static inline void __mfp_config_run(struct pxa3xx_mfp_pin *p)
{
unsigned long off = mfp_table[pin].mfpr_off;
mfp_table[pin].mfpr_val = val;
mfpr_writel(off, val);
if (mfp_configured(p))
mfpr_writel(p->mfpr_off, p->mfpr_run);
}
void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num)
static inline void __mfp_config_lpm(struct pxa3xx_mfp_pin *p)
{
int i, pin;
unsigned long val, flags;
mfp_cfg_t *mfp_cfg = mfp_cfgs;
if (mfp_configured(p)) {
unsigned long mfpr_clr = (p->mfpr_run & ~MFPR_EDGE_BOTH) | MFPR_EDGE_CLEAR;
if (mfpr_clr != p->mfpr_run)
mfpr_writel(p->mfpr_off, mfpr_clr);
if (p->mfpr_lpm != mfpr_clr)
mfpr_writel(p->mfpr_off, p->mfpr_lpm);
}
}
void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num)
{
unsigned long flags;
int i;
spin_lock_irqsave(&mfp_spin_lock, flags);
for (i = 0; i < num; i++, mfp_cfg++) {
pin = MFP_CFG_PIN(*mfp_cfg);
val = MFP_CFG_VAL(*mfp_cfg);
for (i = 0; i < num; i++, mfp_cfgs++) {
unsigned long tmp, c = *mfp_cfgs;
struct pxa3xx_mfp_pin *p;
int pin, af, drv, lpm, edge, pull;
pin = MFP_PIN(c);
BUG_ON(pin >= MFP_PIN_MAX);
p = &mfp_table[pin];
__mfp_config(pin, val);
af = MFP_AF(c);
drv = MFP_DS(c);
lpm = MFP_LPM_STATE(c);
edge = MFP_LPM_EDGE(c);
pull = MFP_PULL(c);
/* run-mode pull settings will conflict with MFPR bits of
* low power mode state, calculate mfpr_run and mfpr_lpm
* individually if pull != MFP_PULL_NONE
*/
tmp = MFPR_AF_SEL(af) | MFPR_DRIVE(drv);
if (likely(pull == MFP_PULL_NONE)) {
p->mfpr_run = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
p->mfpr_lpm = p->mfpr_run;
} else {
p->mfpr_lpm = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
p->mfpr_run = tmp | mfpr_pull[pull];
}
p->config = c; __mfp_config_run(p);
}
mfpr_sync();
@ -96,117 +165,6 @@ void pxa3xx_mfp_write(int mfp, unsigned long val)
spin_unlock_irqrestore(&mfp_spin_lock, flags);
}
void pxa3xx_mfp_set_afds(int mfp, int af, int ds)
{
uint32_t mfpr_off, mfpr_val;
unsigned long flags;
BUG_ON(mfp >= MFP_PIN_MAX);
spin_lock_irqsave(&mfp_spin_lock, flags);
mfpr_off = mfp_table[mfp].mfpr_off;
mfpr_val = mfpr_readl(mfpr_off);
mfpr_val &= ~(MFPR_AF_MASK | MFPR_DRV_MASK);
mfpr_val |= (((af & 0x7) << MFPR_ALT_OFFSET) |
((ds & 0x7) << MFPR_DRV_OFFSET));
mfpr_writel(mfpr_off, mfpr_val);
mfpr_sync();
spin_unlock_irqrestore(&mfp_spin_lock, flags);
}
void pxa3xx_mfp_set_rdh(int mfp, int rdh)
{
uint32_t mfpr_off, mfpr_val;
unsigned long flags;
BUG_ON(mfp >= MFP_PIN_MAX);
spin_lock_irqsave(&mfp_spin_lock, flags);
mfpr_off = mfp_table[mfp].mfpr_off;
mfpr_val = mfpr_readl(mfpr_off);
mfpr_val &= ~MFPR_RDH_MASK;
if (likely(rdh))
mfpr_val |= (1u << MFPR_SS_OFFSET);
mfpr_writel(mfpr_off, mfpr_val);
mfpr_sync();
spin_unlock_irqrestore(&mfp_spin_lock, flags);
}
void pxa3xx_mfp_set_lpm(int mfp, int lpm)
{
uint32_t mfpr_off, mfpr_val;
unsigned long flags;
BUG_ON(mfp >= MFP_PIN_MAX);
spin_lock_irqsave(&mfp_spin_lock, flags);
mfpr_off = mfp_table[mfp].mfpr_off;
mfpr_val = mfpr_readl(mfpr_off);
mfpr_val &= ~MFPR_LPM_MASK;
if (lpm & 0x1) mfpr_val |= 1u << MFPR_SON_OFFSET;
if (lpm & 0x2) mfpr_val |= 1u << MFPR_SD_OFFSET;
if (lpm & 0x4) mfpr_val |= 1u << MFPR_PU_OFFSET;
if (lpm & 0x8) mfpr_val |= 1u << MFPR_PD_OFFSET;
if (lpm &0x10) mfpr_val |= 1u << MFPR_PS_OFFSET;
mfpr_writel(mfpr_off, mfpr_val);
mfpr_sync();
spin_unlock_irqrestore(&mfp_spin_lock, flags);
}
void pxa3xx_mfp_set_pull(int mfp, int pull)
{
uint32_t mfpr_off, mfpr_val;
unsigned long flags;
BUG_ON(mfp >= MFP_PIN_MAX);
spin_lock_irqsave(&mfp_spin_lock, flags);
mfpr_off = mfp_table[mfp].mfpr_off;
mfpr_val = mfpr_readl(mfpr_off);
mfpr_val &= ~MFPR_PULL_MASK;
mfpr_val |= ((pull & 0x7u) << MFPR_PD_OFFSET);
mfpr_writel(mfpr_off, mfpr_val);
mfpr_sync();
spin_unlock_irqrestore(&mfp_spin_lock, flags);
}
void pxa3xx_mfp_set_edge(int mfp, int edge)
{
uint32_t mfpr_off, mfpr_val;
unsigned long flags;
BUG_ON(mfp >= MFP_PIN_MAX);
spin_lock_irqsave(&mfp_spin_lock, flags);
mfpr_off = mfp_table[mfp].mfpr_off;
mfpr_val = mfpr_readl(mfpr_off);
mfpr_val &= ~MFPR_EDGE_MASK;
mfpr_val |= (edge & 0x3u) << MFPR_ERE_OFFSET;
mfpr_val |= (!edge & 0x1) << MFPR_EC_OFFSET;
mfpr_writel(mfpr_off, mfpr_val);
mfpr_sync();
spin_unlock_irqrestore(&mfp_spin_lock, flags);
}
void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map)
{
struct pxa3xx_mfp_addr_map *p;
@ -221,7 +179,8 @@ void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map)
do {
mfp_table[i].mfpr_off = offset;
mfp_table[i].mfpr_val = 0;
mfp_table[i].mfpr_run = 0;
mfp_table[i].mfpr_lpm = 0;
offset += 4; i++;
} while ((i <= p->end) && (p->end != -1));
}
@ -231,5 +190,57 @@ void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map)
void __init pxa3xx_init_mfp(void)
{
memset(mfp_table, 0, sizeof(mfp_table));
int i;
for (i = 0; i < ARRAY_SIZE(mfp_table); i++)
mfp_table[i].config = -1;
}
#ifdef CONFIG_PM
/*
* Configure the MFPs appropriately for suspend/resume.
* FIXME: this should probably depend on which system state we're
* entering - for instance, we might not want to place MFP pins in
* a pull-down mode if they're an active low chip select, and we're
* just entering standby.
*/
static int pxa3xx_mfp_suspend(struct sys_device *d, pm_message_t state)
{
int pin;
for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++) {
struct pxa3xx_mfp_pin *p = &mfp_table[pin];
__mfp_config_lpm(p);
}
return 0;
}
static int pxa3xx_mfp_resume(struct sys_device *d)
{
int pin;
for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++) {
struct pxa3xx_mfp_pin *p = &mfp_table[pin];
__mfp_config_run(p);
}
return 0;
}
static struct sysdev_class mfp_sysclass = {
set_kset_name("mfp"),
.suspend = pxa3xx_mfp_suspend,
.resume = pxa3xx_mfp_resume,
};
static struct sys_device mfp_device = {
.id = 0,
.cls = &mfp_sysclass,
};
static int __init mfp_init_devicefs(void)
{
sysdev_class_register(&mfp_sysclass);
return sysdev_register(&mfp_device);
}
device_initcall(mfp_init_devicefs);
#endif

216
arch/arm/mach-pxa/pcm027.c Normal file
View File

@ -0,0 +1,216 @@
/*
* linux/arch/arm/mach-pxa/pcm027.c
* Support for the Phytec phyCORE-PXA270 CPU card (aka PCM-027).
*
* Refer
* http://www.phytec.com/products/sbc/ARM-XScale/phyCORE-XScale-PXA270.html
* for additional hardware info
*
* Author: Juergen Kilb
* Created: April 05, 2005
* Copyright: Phytec Messtechnik GmbH
* e-Mail: armlinux@phytec.de
*
* based on Intel Mainstone Board
*
* Copyright 2007 Juergen Beisert @ Pengutronix (j.beisert@pengutronix.de)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/spi/spi.h>
#include <linux/leds.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/arch/hardware.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx_spi.h>
#include <asm/arch/pcm027.h>
#include "generic.h"
/*
* ABSTRACT:
*
* The PXA270 processor comes with a bunch of hardware on its silicon.
* Not all of this hardware can be used at the same time and not all
* is routed to module's connectors. Also it depends on the baseboard, what
* kind of hardware can be used in which way.
* -> So this file supports the main devices on the CPU card only!
* Refer pcm990-baseboard.c how to extend this features to get a full
* blown system with many common interfaces.
*
* The PCM-027 supports the following interfaces through its connectors and
* will be used in pcm990-baseboard.c:
*
* - LCD support
* - MMC support
* - IDE/CF card
* - FFUART
* - BTUART
* - IRUART
* - AC97
* - SSP
* - SSP3
*
* Claimed GPIOs:
* GPIO0 -> IRQ input from RTC
* GPIO2 -> SYS_ENA*)
* GPIO3 -> PWR_SCL
* GPIO4 -> PWR_SDA
* GPIO5 -> PowerCap0*)
* GPIO6 -> PowerCap1*)
* GPIO7 -> PowerCap2*)
* GPIO8 -> PowerCap3*)
* GPIO15 -> /CS1
* GPIO20 -> /CS2
* GPIO21 -> /CS3
* GPIO33 -> /CS5 network controller select
* GPIO52 -> IRQ from network controller
* GPIO78 -> /CS2
* GPIO80 -> /CS4
* GPIO90 -> LED0
* GPIO91 -> LED1
* GPIO114 -> IRQ from CAN controller
* GPIO117 -> SCL
* GPIO118 -> SDA
*
* *) CPU internal use only
*/
/*
* SMC91x network controller specific stuff
*/
static struct resource smc91x_resources[] = {
[0] = {
.start = PCM027_ETH_PHYS + 0x300,
.end = PCM027_ETH_PHYS + PCM027_ETH_SIZE,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = PCM027_ETH_IRQ,
.end = PCM027_ETH_IRQ,
/* note: smc91x's driver doesn't use the trigger bits yet */
.flags = IORESOURCE_IRQ | PCM027_ETH_IRQ_EDGE,
}
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
static struct physmap_flash_data pcm027_flash_data = {
.width = 4,
};
static struct resource pcm027_flash_resource = {
.start = PCM027_FLASH_PHYS,
.end = PCM027_FLASH_PHYS + PCM027_FLASH_SIZE - 1 ,
.flags = IORESOURCE_MEM,
};
static struct platform_device pcm027_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &pcm027_flash_data,
},
.resource = &pcm027_flash_resource,
.num_resources = 1,
};
#ifdef CONFIG_LEDS_GPIO
static struct gpio_led pcm027_led[] = {
{
.name = "led0:red", /* FIXME */
.gpio = PCM027_LED_CPU
},
{
.name = "led1:green", /* FIXME */
.gpio = PCM027_LED_HEARD_BEAT
},
};
static struct gpio_led_platform_data pcm027_led_data = {
.num_leds = ARRAY_SIZE(pcm027_led),
.leds = pcm027_led
};
static struct platform_device pcm027_led_dev = {
.name = "leds-gpio",
.id = 0,
.dev = {
.platform_data = &pcm027_led_data,
},
};
#endif /* CONFIG_LEDS_GPIO */
/*
* declare the available device resources on this board
*/
static struct platform_device *devices[] __initdata = {
&smc91x_device,
&pcm027_flash,
#ifdef CONFIG_LEDS_GPIO
&pcm027_led_dev
#endif
};
/*
* pcm027_init - breath some life into the board
*/
static void __init pcm027_init(void)
{
/* system bus arbiter setting
* - Core_Park
* - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
*/
ARB_CNTRL = ARB_CORE_PARK | 0x234;
platform_add_devices(devices, ARRAY_SIZE(devices));
/* LEDs (on demand only) */
#ifdef CONFIG_LEDS_GPIO
pxa_gpio_mode(PCM027_LED_CPU | GPIO_OUT);
pxa_gpio_mode(PCM027_LED_HEARD_BEAT | GPIO_OUT);
#endif /* CONFIG_LEDS_GPIO */
/* at last call the baseboard to initialize itself */
#ifdef CONFIG_MACH_PCM990_BASEBOARD
pcm990_baseboard_init();
#endif
}
static void __init pcm027_map_io(void)
{
pxa_map_io();
/* initialize sleep mode regs (wake-up sources, etc) */
PGSR0 = 0x01308000;
PGSR1 = 0x00CF0002;
PGSR2 = 0x0E294000;
PGSR3 = 0x0000C000;
PWER = 0x40000000 | PWER_GPIO0 | PWER_GPIO1;
PRER = 0x00000000;
PFER = 0x00000003;
}
MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270")
/* Maintainer: Pengutronix */
.boot_params = 0xa0000100,
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.map_io = pcm027_map_io,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
.init_machine = pcm027_init,
MACHINE_END

330
arch/arm/mach-pxa/pcm990-baseboard.c Normal file
View File

@ -0,0 +1,330 @@
/*
* arch/arm/mach-pxa/pcm990-baseboard.c
* Support for the Phytec phyCORE-PXA270 Development Platform (PCM-990).
*
* Refer
* http://www.phytec.com/products/rdk/ARM-XScale/phyCORE-XScale-PXA270.html
* for additional hardware info
*
* Author: Juergen Kilb
* Created: April 05, 2005
* Copyright: Phytec Messtechnik GmbH
* e-Mail: armlinux@phytec.de
*
* based on Intel Mainstone Board
*
* Copyright 2007 Juergen Beisert @ Pengutronix (j.beisert@pengutronix.de)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/ide.h>
#include <asm/mach/map.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/mmc.h>
#include <asm/arch/ohci.h>
#include <asm/arch/pcm990_baseboard.h>
/*
* The PCM-990 development baseboard uses PCM-027's hardeware in the
* following way:
*
* - LCD support is in use
* - GPIO16 is output for back light on/off with PWM
* - GPIO58 ... GPIO73 are outputs for display data
* - GPIO74 is output output for LCDFCLK
* - GPIO75 is output for LCDLCLK
* - GPIO76 is output for LCDPCLK
* - GPIO77 is output for LCDBIAS
* - MMC support is in use
* - GPIO32 is output for MMCCLK
* - GPIO92 is MMDAT0
* - GPIO109 is MMDAT1
* - GPIO110 is MMCS0
* - GPIO111 is MMCS1
* - GPIO112 is MMCMD
* - IDE/CF card is in use
* - GPIO48 is output /POE
* - GPIO49 is output /PWE
* - GPIO50 is output /PIOR
* - GPIO51 is output /PIOW
* - GPIO54 is output /PCE2
* - GPIO55 is output /PREG
* - GPIO56 is input /PWAIT
* - GPIO57 is output /PIOS16
* - GPIO79 is output PSKTSEL
* - GPIO85 is output /PCE1
* - FFUART is in use
* - GPIO34 is input FFRXD
* - GPIO35 is input FFCTS
* - GPIO36 is input FFDCD
* - GPIO37 is input FFDSR
* - GPIO38 is input FFRI
* - GPIO39 is output FFTXD
* - GPIO40 is output FFDTR
* - GPIO41 is output FFRTS
* - BTUART is in use
* - GPIO42 is input BTRXD
* - GPIO43 is output BTTXD
* - GPIO44 is input BTCTS
* - GPIO45 is output BTRTS
* - IRUART is in use
* - GPIO46 is input STDRXD
* - GPIO47 is output STDTXD
* - AC97 is in use*)
* - GPIO28 is input AC97CLK
* - GPIO29 is input AC97DatIn
* - GPIO30 is output AC97DatO
* - GPIO31 is output AC97SYNC
* - GPIO113 is output AC97_RESET
* - SSP is in use
* - GPIO23 is output SSPSCLK
* - GPIO24 is output chip select to Max7301
* - GPIO25 is output SSPTXD
* - GPIO26 is input SSPRXD
* - GPIO27 is input for Max7301 IRQ
* - GPIO53 is input SSPSYSCLK
* - SSP3 is in use
* - GPIO81 is output SSPTXD3
* - GPIO82 is input SSPRXD3
* - GPIO83 is output SSPSFRM
* - GPIO84 is output SSPCLK3
*
* Otherwise claimed GPIOs:
* GPIO1 -> IRQ from user switch
* GPIO9 -> IRQ from power management
* GPIO10 -> IRQ from WML9712 AC97 controller
* GPIO11 -> IRQ from IDE controller
* GPIO12 -> IRQ from CF controller
* GPIO13 -> IRQ from CF controller
* GPIO14 -> GPIO free
* GPIO15 -> /CS1 selects baseboard's Control CPLD (U7, 16 bit wide data path)
* GPIO19 -> GPIO free
* GPIO20 -> /SDCS2
* GPIO21 -> /CS3 PC card socket select
* GPIO33 -> /CS5 network controller select
* GPIO78 -> /CS2 (16 bit wide data path)
* GPIO80 -> /CS4 (16 bit wide data path)
* GPIO86 -> GPIO free
* GPIO87 -> GPIO free
* GPIO90 -> LED0 on CPU module
* GPIO91 -> LED1 on CPI module
* GPIO117 -> SCL
* GPIO118 -> SDA
*/
static unsigned long pcm990_irq_enabled;
static void pcm990_mask_ack_irq(unsigned int irq)
{
int pcm990_irq = (irq - PCM027_IRQ(0));
PCM990_INTMSKENA = (pcm990_irq_enabled &= ~(1 << pcm990_irq));
}
static void pcm990_unmask_irq(unsigned int irq)
{
int pcm990_irq = (irq - PCM027_IRQ(0));
/* the irq can be acknowledged only if deasserted, so it's done here */
PCM990_INTSETCLR |= 1 << pcm990_irq;
PCM990_INTMSKENA = (pcm990_irq_enabled |= (1 << pcm990_irq));
}
static struct irq_chip pcm990_irq_chip = {
.mask_ack = pcm990_mask_ack_irq,
.unmask = pcm990_unmask_irq,
};
static void pcm990_irq_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned long pending = (~PCM990_INTSETCLR) & pcm990_irq_enabled;
do {
GEDR(PCM990_CTRL_INT_IRQ_GPIO) =
GPIO_bit(PCM990_CTRL_INT_IRQ_GPIO);
if (likely(pending)) {
irq = PCM027_IRQ(0) + __ffs(pending);
desc = irq_desc + irq;
desc_handle_irq(irq, desc);
}
pending = (~PCM990_INTSETCLR) & pcm990_irq_enabled;
} while (pending);
}
static void __init pcm990_init_irq(void)
{
int irq;
/* setup extra PCM990 irqs */
for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) {
set_irq_chip(irq, &pcm990_irq_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
PCM990_INTMSKENA = 0x00; /* disable all Interrupts */
PCM990_INTSETCLR = 0xFF;
set_irq_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler);
set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE);
}
static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
void *data)
{
int err;
/*
* enable GPIO for PXA27x MMC controller
*/
pxa_gpio_mode(GPIO32_MMCCLK_MD);
pxa_gpio_mode(GPIO112_MMCCMD_MD);
pxa_gpio_mode(GPIO92_MMCDAT0_MD);
pxa_gpio_mode(GPIO109_MMCDAT1_MD);
pxa_gpio_mode(GPIO110_MMCDAT2_MD);
pxa_gpio_mode(GPIO111_MMCDAT3_MD);
err = request_irq(PCM027_MMCDET_IRQ, mci_detect_int, IRQF_DISABLED,
"MMC card detect", data);
if (err)
printk(KERN_ERR "pcm990_mci_init: MMC/SD: can't request MMC "
"card detect IRQ\n");
return err;
}
static void pcm990_mci_setpower(struct device *dev, unsigned int vdd)
{
struct pxamci_platform_data *p_d = dev->platform_data;
if ((1 << vdd) & p_d->ocr_mask)
__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5) =
PCM990_CTRL_MMC2PWR;
else
__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5) =
~PCM990_CTRL_MMC2PWR;
}
static void pcm990_mci_exit(struct device *dev, void *data)
{
free_irq(PCM027_MMCDET_IRQ, data);
}
#define MSECS_PER_JIFFY (1000/HZ)
static struct pxamci_platform_data pcm990_mci_platform_data = {
.detect_delay = 250 / MSECS_PER_JIFFY,
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
.init = pcm990_mci_init,
.setpower = pcm990_mci_setpower,
.exit = pcm990_mci_exit,
};
/*
* init OHCI hardware to work with
*
* Note: Only USB port 1 (host only) is connected
*
* GPIO88 (USBHPWR#1): overcurrent in, overcurrent when low
* GPIO89 (USBHPEN#1): power-on out, on when low
*/
static int pcm990_ohci_init(struct device *dev)
{
pxa_gpio_mode(PCM990_USB_OVERCURRENT);
pxa_gpio_mode(PCM990_USB_PWR_EN);
/*
* disable USB port 2 and 3
* power sense is active low
*/
UHCHR = ((UHCHR) | UHCHR_PCPL | UHCHR_PSPL | UHCHR_SSEP2 |
UHCHR_SSEP3) & ~(UHCHR_SSEP1 | UHCHR_SSE);
/*
* wait 10ms after Power on
* overcurrent per port
* power switch per port
*/
UHCRHDA = (5<<24) | (1<<11) | (1<<8); /* FIXME: Required? */
return 0;
}
static struct pxaohci_platform_data pcm990_ohci_platform_data = {
.port_mode = PMM_PERPORT_MODE,
.init = pcm990_ohci_init,
.exit = NULL,
};
/*
* AC97 support
* Note: The connected AC97 mixer also reports interrupts at PCM990_AC97_IRQ
*/
static struct resource pxa27x_ac97_resources[] = {
[0] = {
.start = 0x40500000,
.end = 0x40500000 + 0xfff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_AC97,
.end = IRQ_AC97,
.flags = IORESOURCE_IRQ,
},
};
static u64 pxa_ac97_dmamask = 0xffffffffUL;
static struct platform_device pxa27x_device_ac97 = {
.name = "pxa2xx-ac97",
.id = -1,
.dev = {
.dma_mask = &pxa_ac97_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(pxa27x_ac97_resources),
.resource = pxa27x_ac97_resources,
};
/*
* enable generic access to the base board control CPLDs U6 and U7
*/
static struct map_desc pcm990_io_desc[] __initdata = {
{
.virtual = PCM990_CTRL_BASE,
.pfn = __phys_to_pfn(PCM990_CTRL_PHYS),
.length = PCM990_CTRL_SIZE,
.type = MT_DEVICE /* CPLD */
}, {
.virtual = PCM990_CF_PLD_BASE,
.pfn = __phys_to_pfn(PCM990_CF_PLD_PHYS),
.length = PCM990_CF_PLD_SIZE,
.type = MT_DEVICE /* CPLD */
}
};
/*
* system init for baseboard usage. Will be called by pcm027 init.
*
* Add platform devices present on this baseboard and init
* them from CPU side as far as required to use them later on
*/
void __init pcm990_baseboard_init(void)
{
/* register CPLD access */
iotable_init(pcm990_io_desc, ARRAY_SIZE(pcm990_io_desc));
/* register CPLD's IRQ controller */
pcm990_init_irq();
platform_device_register(&pxa27x_device_ac97);
/* MMC */
pxa_set_mci_info(&pcm990_mci_platform_data);
/* USB host */
pxa_set_ohci_info(&pcm990_ohci_platform_data);
printk(KERN_INFO"PCM-990 Evaluation baseboard initialized\n");
}

13
arch/arm/mach-pxa/pm.c
View File

@ -38,19 +38,22 @@ int pxa_pm_enter(suspend_state_t state)
iwmmxt_task_disable(NULL);
#endif
/* skip registers saving for standby */
if (state != PM_SUSPEND_STANDBY) {
pxa_cpu_pm_fns->save(sleep_save);
/* Clear sleep reset status */
RCSR = RCSR_SMR;
/* before sleeping, calculate and save a checksum */
for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++)
sleep_save_checksum += sleep_save[i];
}
/* Clear sleep reset status */
RCSR = RCSR_SMR;
/* *** go zzz *** */
pxa_cpu_pm_fns->enter(state);
cpu_init();
if (state != PM_SUSPEND_STANDBY) {
/* after sleeping, validate the checksum */
for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++)
checksum += sleep_save[i];
@ -63,8 +66,8 @@ int pxa_pm_enter(suspend_state_t state)
while (1)
pxa_cpu_pm_fns->enter(state);
}
pxa_cpu_pm_fns->restore(sleep_save);
}
pr_debug("*** made it back from resume\n");

6
arch/arm/mach-pxa/poodle.c
View File

@ -215,12 +215,10 @@ static int poodle_mci_init(struct device *dev, irq_handler_t poodle_detect_int,
err = request_irq(POODLE_IRQ_GPIO_nSD_DETECT, poodle_detect_int,
IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"MMC card detect", data);
if (err) {
if (err)
printk(KERN_ERR "poodle_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
return -1;
}
return 0;
return err;
}
static void poodle_mci_setpower(struct device *dev, unsigned int vdd)

22
arch/arm/mach-pxa/pxa25x.c
View File

@ -123,12 +123,15 @@ static struct clk pxa25x_clks[] = {
INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev),
INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev),
INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
/*
INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
INIT_CKEN("SSPCLK", SSP, 3686400, 0, NULL),
INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL),
INIT_CKEN("NSSPCLK", NSSP, 3686400, 0, NULL),
*/
INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
};
@ -216,8 +219,6 @@ static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
static void pxa25x_cpu_pm_enter(suspend_state_t state)
{
CKEN = 0;
switch (state) {
case PM_SUSPEND_MEM:
/* set resume return address */
@ -239,6 +240,8 @@ static void __init pxa25x_init_pm(void)
{
pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
}
#else
static inline void pxa25x_init_pm(void) {}
#endif
/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
@ -290,16 +293,15 @@ void __init pxa25x_init_irq(void)
}
static struct platform_device *pxa25x_devices[] __initdata = {
&pxa_device_mci,
&pxa_device_udc,
&pxa_device_fb,
&pxa_device_ffuart,
&pxa_device_btuart,
&pxa_device_stuart,
&pxa_device_i2c,
&pxa_device_i2s,
&pxa_device_ficp,
&pxa_device_rtc,
&pxa25x_device_ssp,
&pxa25x_device_nssp,
&pxa25x_device_assp,
};
static int __init pxa25x_init(void)
@ -315,9 +317,9 @@ static int __init pxa25x_init(void)
if ((ret = pxa_init_dma(16)))
return ret;
#ifdef CONFIG_PM
pxa25x_init_pm();
#endif
ret = platform_add_devices(pxa25x_devices,
ARRAY_SIZE(pxa25x_devices));
}

59
arch/arm/mach-pxa/pxa27x.c
View File

@ -21,6 +21,7 @@
#include <asm/irq.h>
#include <asm/arch/irqs.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/ohci.h>
#include <asm/arch/pm.h>
#include <asm/arch/dma.h>
@ -151,11 +152,12 @@ static struct clk pxa27x_clks[] = {
INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL),
INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
/*
INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL),
INIT_CKEN("SSPCLK", SSP1, 13000000, 0, NULL),
INIT_CKEN("SSPCLK", SSP2, 13000000, 0, NULL),
INIT_CKEN("SSPCLK", SSP3, 13000000, 0, NULL),
INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL),
INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
@ -264,12 +266,6 @@ void pxa27x_cpu_pm_enter(suspend_state_t state)
{
extern void pxa_cpu_standby(void);
if (state == PM_SUSPEND_STANDBY)
CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) |
(1 << CKEN_LCD) | (1 << CKEN_PWM0);
else
CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER);
/* ensure voltage-change sequencer not initiated, which hangs */
PCFR &= ~PCFR_FVC;
@ -305,6 +301,8 @@ static void __init pxa27x_init_pm(void)
{
pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
}
#else
static inline void pxa27x_init_pm(void) {}
#endif
/* PXA27x: Various gpios can issue wakeup events. This logic only
@ -374,37 +372,6 @@ void __init pxa27x_init_irq(void)
* device registration specific to PXA27x.
*/
static u64 pxa27x_dmamask = 0xffffffffUL;
static struct resource pxa27x_ohci_resources[] = {
[0] = {
.start = 0x4C000000,
.end = 0x4C00ff6f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_USBH1,
.end = IRQ_USBH1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device pxa27x_device_ohci = {
.name = "pxa27x-ohci",
.id = -1,
.dev = {
.dma_mask = &pxa27x_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(pxa27x_ohci_resources),
.resource = pxa27x_ohci_resources,
};
void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
{
pxa27x_device_ohci.dev.platform_data = info;
}
static struct resource i2c_power_resources[] = {
{
.start = 0x40f00180,
@ -430,18 +397,16 @@ void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info)
}
static struct platform_device *devices[] __initdata = {
&pxa_device_mci,
&pxa_device_udc,
&pxa_device_fb,
&pxa_device_ffuart,
&pxa_device_btuart,
&pxa_device_stuart,
&pxa_device_i2c,
&pxa_device_i2s,
&pxa_device_ficp,
&pxa_device_rtc,
&pxa27x_device_i2c_power,
&pxa27x_device_ohci,
&pxa27x_device_ssp1,
&pxa27x_device_ssp2,
&pxa27x_device_ssp3,
};
static int __init pxa27x_init(void)
@ -452,9 +417,9 @@ static int __init pxa27x_init(void)
if ((ret = pxa_init_dma(32)))
return ret;
#ifdef CONFIG_PM
pxa27x_init_pm();
#endif
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
}
return ret;

241
arch/arm/mach-pxa/pxa3xx.c
View File

@ -19,6 +19,7 @@
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/hardware.h>
#include <asm/arch/pxa3xx-regs.h>
@ -189,8 +190,237 @@ static struct clk pxa3xx_clks[] = {
PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev),
PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev),
};
#ifdef CONFIG_PM
#define SLEEP_SAVE_SIZE 4
#define ISRAM_START 0x5c000000
#define ISRAM_SIZE SZ_256K
static void __iomem *sram;
static unsigned long wakeup_src;
static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
{
pr_debug("PM: CKENA=%08x CKENB=%08x\n", CKENA, CKENB);
if (CKENA & (1 << CKEN_USBH)) {
printk(KERN_ERR "PM: USB host clock not stopped?\n");
CKENA &= ~(1 << CKEN_USBH);
}
// CKENA |= 1 << (CKEN_ISC & 31);
/*
* Low power modes require the HSIO2 clock to be enabled.
*/
CKENB |= 1 << (CKEN_HSIO2 & 31);
}
static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
{
CKENB &= ~(1 << (CKEN_HSIO2 & 31));
}
/*
* Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
* memory controller has to be reinitialised, so we place some code
* in the SRAM to perform this function.
*
* We disable FIQs across the standby - otherwise, we might receive a
* FIQ while the SDRAM is unavailable.
*/
static void pxa3xx_cpu_standby(unsigned int pwrmode)
{
extern const char pm_enter_standby_start[], pm_enter_standby_end[];
void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
memcpy_toio(sram + 0x8000, pm_enter_standby_start,
pm_enter_standby_end - pm_enter_standby_start);
AD2D0SR = ~0;
AD2D1SR = ~0;
AD2D0ER = wakeup_src;
AD2D1ER = 0;
ASCR = ASCR;
ARSR = ARSR;
local_fiq_disable();
fn(pwrmode);
local_fiq_enable();
AD2D0ER = 0;
AD2D1ER = 0;
printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR);
}
static void pxa3xx_cpu_pm_enter(suspend_state_t state)
{
/*
* Don't sleep if no wakeup sources are defined
*/
if (wakeup_src == 0)
return;
switch (state) {
case PM_SUSPEND_STANDBY:
pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
break;
case PM_SUSPEND_MEM:
break;
}
}
static int pxa3xx_cpu_pm_valid(suspend_state_t state)
{
return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}
static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
.save_size = SLEEP_SAVE_SIZE,
.save = pxa3xx_cpu_pm_save,
.restore = pxa3xx_cpu_pm_restore,
.valid = pxa3xx_cpu_pm_valid,
.enter = pxa3xx_cpu_pm_enter,
};
static void __init pxa3xx_init_pm(void)
{
sram = ioremap(ISRAM_START, ISRAM_SIZE);
if (!sram) {
printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
return;
}
/*
* Since we copy wakeup code into the SRAM, we need to ensure
* that it is preserved over the low power modes. Note: bit 8
* is undocumented in the developer manual, but must be set.
*/
AD1R |= ADXR_L2 | ADXR_R0;
AD2R |= ADXR_L2 | ADXR_R0;
AD3R |= ADXR_L2 | ADXR_R0;
/*
* Clear the resume enable registers.
*/
AD1D0ER = 0;
AD2D0ER = 0;
AD2D1ER = 0;
AD3ER = 0;
pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
}
static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
{
unsigned long flags, mask = 0;
switch (irq) {
case IRQ_SSP3:
mask = ADXER_MFP_WSSP3;
break;
case IRQ_MSL:
mask = ADXER_WMSL0;
break;
case IRQ_USBH2:
case IRQ_USBH1:
mask = ADXER_WUSBH;
break;
case IRQ_KEYPAD:
mask = ADXER_WKP;
break;
case IRQ_AC97:
mask = ADXER_MFP_WAC97;
break;
case IRQ_USIM:
mask = ADXER_WUSIM0;
break;
case IRQ_SSP2:
mask = ADXER_MFP_WSSP2;
break;
case IRQ_I2C:
mask = ADXER_MFP_WI2C;
break;
case IRQ_STUART:
mask = ADXER_MFP_WUART3;
break;
case IRQ_BTUART:
mask = ADXER_MFP_WUART2;
break;
case IRQ_FFUART:
mask = ADXER_MFP_WUART1;
break;
case IRQ_MMC:
mask = ADXER_MFP_WMMC1;
break;
case IRQ_SSP:
mask = ADXER_MFP_WSSP1;
break;
case IRQ_RTCAlrm:
mask = ADXER_WRTC;
break;
case IRQ_SSP4:
mask = ADXER_MFP_WSSP4;
break;
case IRQ_TSI:
mask = ADXER_WTSI;
break;
case IRQ_USIM2:
mask = ADXER_WUSIM1;
break;
case IRQ_MMC2:
mask = ADXER_MFP_WMMC2;
break;
case IRQ_NAND:
mask = ADXER_MFP_WFLASH;
break;
case IRQ_USB2:
mask = ADXER_WUSB2;
break;
case IRQ_WAKEUP0:
mask = ADXER_WEXTWAKE0;
break;
case IRQ_WAKEUP1:
mask = ADXER_WEXTWAKE1;
break;
case IRQ_MMC3:
mask = ADXER_MFP_GEN12;
break;
}
local_irq_save(flags);
if (on)
wakeup_src |= mask;
else
wakeup_src &= ~mask;
local_irq_restore(flags);
return 0;
}
static void pxa3xx_init_irq_pm(void)
{
pxa_init_irq_set_wake(pxa3xx_set_wake);
}
#else
static inline void pxa3xx_init_pm(void) {}
static inline void pxa3xx_init_irq_pm(void) {}
#endif
void __init pxa3xx_init_irq(void)
{
/* enable CP6 access */
@ -202,6 +432,7 @@ void __init pxa3xx_init_irq(void)
pxa_init_irq_low();
pxa_init_irq_high();
pxa_init_irq_gpio(128);
pxa3xx_init_irq_pm();
}
/*
@ -209,16 +440,16 @@ void __init pxa3xx_init_irq(void)
*/
static struct platform_device *devices[] __initdata = {
&pxa_device_mci,
&pxa_device_udc,
&pxa_device_fb,
&pxa_device_ffuart,
&pxa_device_btuart,
&pxa_device_stuart,
&pxa_device_i2c,
&pxa_device_i2s,
&pxa_device_ficp,
&pxa_device_rtc,
&pxa27x_device_ssp1,
&pxa27x_device_ssp2,
&pxa27x_device_ssp3,
&pxa3xx_device_ssp4,
};
static int __init pxa3xx_init(void)
@ -231,6 +462,8 @@ static int __init pxa3xx_init(void)
if ((ret = pxa_init_dma(32)))
return ret;
pxa3xx_init_pm();
return platform_add_devices(devices, ARRAY_SIZE(devices));
}
return 0;

19
arch/arm/mach-pxa/sharpsl.h
View File

@ -26,28 +26,15 @@ void corgi_ssp_set_machinfo(struct corgissp_machinfo *machinfo);
/*
* SharpSL Backlight
* SharpSL/Corgi LCD Driver
*/
void corgi_bl_set_intensity(int intensity);
void spitz_bl_set_intensity(int intensity);
void akita_bl_set_intensity(int intensity);
/*
* SharpSL Touchscreen Driver
*/
unsigned long corgi_get_hsync_len(void);
unsigned long spitz_get_hsync_len(void);
void corgi_put_hsync(void);
void spitz_put_hsync(void);
void corgi_wait_hsync(void);
void spitz_wait_hsync(void);
void corgi_lcdtg_suspend(void);
void corgi_lcdtg_hw_init(int mode);
/*
* SharpSL Battery/PM Driver
*/
#define READ_GPIO_BIT(x) (GPLR(x) & GPIO_bit(x))
/* MAX1111 Channel Definitions */

9
arch/arm/mach-pxa/sleep.S
View File

@ -16,6 +16,7 @@
#include <asm/hardware.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#define MDREFR_KDIV 0x200a4000 // all banks
#define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
@ -49,6 +50,7 @@ pxa_cpu_save_sp:
str r0, [r1]
ldr pc, [sp], #4
#ifdef CONFIG_PXA27x
/*
* pxa27x_cpu_suspend()
*
@ -104,9 +106,11 @@ ENTRY(pxa27x_cpu_suspend)
@ align execution to a cache line
b pxa_cpu_do_suspend
#endif
#ifdef CONFIG_PXA25x
/*
* pxa27x_cpu_suspend()
* pxa25x_cpu_suspend()
*
* Forces CPU into sleep state.
*
@ -169,6 +173,7 @@ ENTRY(pxa25x_cpu_suspend)
mcr p14, 0, r0, c6, c0, 0
orr r0, r0, #2 @ initiate change bit
b pxa_cpu_do_suspend
#endif
.ltorg
.align 5
@ -208,7 +213,7 @@ pxa_cpu_do_suspend:
20: b 20b @ loop waiting for sleep
/*
* cpu_pxa_resume()
* pxa_cpu_resume()
*
* entry point from bootloader into kernel during resume
*

108
arch/arm/mach-pxa/spitz.c
View File

@ -271,6 +271,55 @@ static struct platform_device spitzled_device = {
/*
* Spitz Touch Screen Device
*/
static unsigned long (*get_hsync_invperiod)(struct device *dev);
static void inline sharpsl_wait_sync(int gpio)
{
while((GPLR(gpio) & GPIO_bit(gpio)) == 0);
while((GPLR(gpio) & GPIO_bit(gpio)) != 0);
}
static struct device *spitz_pxafb_dev;
static int is_pxafb_device(struct device * dev, void * data)
{
struct platform_device *pdev = container_of(dev, struct platform_device, dev);
return (strncmp(pdev->name, "pxa2xx-fb", 9) == 0);
}
static unsigned long spitz_get_hsync_invperiod(void)
{
#ifdef CONFIG_FB_PXA
if (!spitz_pxafb_dev) {
spitz_pxafb_dev = bus_find_device(&platform_bus_type, NULL, NULL, is_pxafb_device);
if (!spitz_pxafb_dev)
return 0;
}
if (!get_hsync_invperiod)
get_hsync_invperiod = symbol_get(pxafb_get_hsync_time);
if (!get_hsync_invperiod)
#endif
return 0;
return get_hsync_invperiod(spitz_pxafb_dev);
}
static void spitz_put_hsync(void)
{
put_device(spitz_pxafb_dev);
if (get_hsync_invperiod)
symbol_put(pxafb_get_hsync_time);
spitz_pxafb_dev = NULL;
get_hsync_invperiod = NULL;
}
static void spitz_wait_hsync(void)
{
sharpsl_wait_sync(SPITZ_GPIO_HSYNC);
}
static struct resource spitzts_resources[] = {
[0] = {
.start = SPITZ_IRQ_GPIO_TP_INT,
@ -280,7 +329,7 @@ static struct resource spitzts_resources[] = {
};
static struct corgits_machinfo spitz_ts_machinfo = {
.get_hsync_len = spitz_get_hsync_len,
.get_hsync_invperiod = spitz_get_hsync_invperiod,
.put_hsync = spitz_put_hsync,
.wait_hsync = spitz_wait_hsync,
};
@ -325,12 +374,10 @@ static int spitz_mci_init(struct device *dev, irq_handler_t spitz_detect_int, vo
err = request_irq(SPITZ_IRQ_GPIO_nSD_DETECT, spitz_detect_int,
IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"MMC card detect", data);
if (err) {
if (err)
printk(KERN_ERR "spitz_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
return -1;
}
return 0;
return err;
}
static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
@ -423,6 +470,14 @@ static struct pxaficp_platform_data spitz_ficp_platform_data = {
* Spitz PXA Framebuffer
*/
static void spitz_lcd_power(int on, struct fb_var_screeninfo *var)
{
if (on)
corgi_lcdtg_hw_init(var->xres);
else
corgi_lcdtg_suspend();
}
static struct pxafb_mode_info spitz_pxafb_modes[] = {
{
.pixclock = 19231,
@ -520,6 +575,27 @@ static void __init common_init(void)
set_pxa_fb_info(&spitz_pxafb_info);
}
#if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI)
static void spitz_bl_set_intensity(int intensity)
{
if (intensity > 0x10)
intensity += 0x10;
/* Bits 0-4 are accessed via the SSP interface */
corgi_ssp_blduty_set(intensity & 0x1f);
/* Bit 5 is via SCOOP */
if (intensity & 0x0020)
reset_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_CONT);
else
set_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_CONT);
if (intensity)
set_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_ON);
else
reset_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_ON);
}
static void __init spitz_init(void)
{
platform_scoop_config = &spitz_pcmcia_config;
@ -530,6 +606,7 @@ static void __init spitz_init(void)
platform_device_register(&spitzscoop2_device);
}
#endif
#ifdef CONFIG_MACH_AKITA
/*
@ -542,6 +619,26 @@ struct platform_device akitaioexp_device = {
EXPORT_SYMBOL_GPL(akitaioexp_device);
static void akita_bl_set_intensity(int intensity)
{
if (intensity > 0x10)
intensity += 0x10;
/* Bits 0-4 are accessed via the SSP interface */
corgi_ssp_blduty_set(intensity & 0x1f);
/* Bit 5 is via IO-Expander */
if (intensity & 0x0020)
akita_reset_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_CONT);
else
akita_set_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_CONT);
if (intensity)
akita_set_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_ON);
else
akita_reset_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_ON);
}
static void __init akita_init(void)
{
spitz_ficp_platform_data.transceiver_mode = akita_irda_transceiver_mode;
@ -558,7 +655,6 @@ static void __init akita_init(void)
}
#endif
static void __init fixup_spitz(struct machine_desc *desc,
struct tag *tags, char **cmdline, struct meminfo *mi)
{

386
arch/arm/mach-pxa/ssp.c
View File

@ -32,45 +32,27 @@
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/mutex.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/hardware.h>
#include <asm/arch/ssp.h>
#include <asm/arch/pxa-regs.h>
#define PXA_SSP_PORTS 3
#include <asm/arch/regs-ssp.h>
#define TIMEOUT 100000
struct ssp_info_ {
int irq;
u32 clock;
};
/*
* SSP port clock and IRQ settings
*/
static const struct ssp_info_ ssp_info[PXA_SSP_PORTS] = {
#if defined (CONFIG_PXA27x)
{IRQ_SSP, CKEN_SSP1},
{IRQ_SSP2, CKEN_SSP2},
{IRQ_SSP3, CKEN_SSP3},
#else
{IRQ_SSP, CKEN_SSP},
{IRQ_NSSP, CKEN_NSSP},
{IRQ_ASSP, CKEN_ASSP},
#endif
};
static DEFINE_MUTEX(mutex);
static int use_count[PXA_SSP_PORTS] = {0, 0, 0};
static irqreturn_t ssp_interrupt(int irq, void *dev_id)
{
struct ssp_dev *dev = dev_id;
unsigned int status = SSSR_P(dev->port);
struct ssp_device *ssp = dev->ssp;
unsigned int status;
SSSR_P(dev->port) = status; /* clear status bits */
status = __raw_readl(ssp->mmio_base + SSSR);
__raw_writel(status, ssp->mmio_base + SSSR);
if (status & SSSR_ROR)
printk(KERN_WARNING "SSP(%d): receiver overrun\n", dev->port);
@ -99,15 +81,16 @@ static irqreturn_t ssp_interrupt(int irq, void *dev_id)
*/
int ssp_write_word(struct ssp_dev *dev, u32 data)
{
struct ssp_device *ssp = dev->ssp;
int timeout = TIMEOUT;
while (!(SSSR_P(dev->port) & SSSR_TNF)) {
while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_TNF)) {
if (!--timeout)
return -ETIMEDOUT;
cpu_relax();
}
SSDR_P(dev->port) = data;
__raw_writel(data, ssp->mmio_base + SSDR);
return 0;
}
@ -129,15 +112,16 @@ int ssp_write_word(struct ssp_dev *dev, u32 data)
*/
int ssp_read_word(struct ssp_dev *dev, u32 *data)
{
struct ssp_device *ssp = dev->ssp;
int timeout = TIMEOUT;
while (!(SSSR_P(dev->port) & SSSR_RNE)) {
while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE)) {
if (!--timeout)
return -ETIMEDOUT;
cpu_relax();
}
*data = SSDR_P(dev->port);
*data = __raw_readl(ssp->mmio_base + SSDR);
return 0;
}
@ -151,17 +135,28 @@ int ssp_read_word(struct ssp_dev *dev, u32 *data)
*/
int ssp_flush(struct ssp_dev *dev)
{
struct ssp_device *ssp = dev->ssp;
int timeout = TIMEOUT * 2;
do {
while (SSSR_P(dev->port) & SSSR_RNE) {
/* ensure TX FIFO is empty instead of not full */
if (cpu_is_pxa3xx()) {
while (__raw_readl(ssp->mmio_base + SSSR) & 0xf00) {
if (!--timeout)
return -ETIMEDOUT;
(void) SSDR_P(dev->port);
cpu_relax();
}
timeout = TIMEOUT * 2;
}
do {
while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE) {
if (!--timeout)
return -ETIMEDOUT;
(void)__raw_readl(ssp->mmio_base + SSDR);
}
if (!--timeout)
return -ETIMEDOUT;
} while (SSSR_P(dev->port) & SSSR_BSY);
} while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_BSY);
return 0;
}
@ -173,7 +168,12 @@ int ssp_flush(struct ssp_dev *dev)
*/
void ssp_enable(struct ssp_dev *dev)
{
SSCR0_P(dev->port) |= SSCR0_SSE;
struct ssp_device *ssp = dev->ssp;
uint32_t sscr0;
sscr0 = __raw_readl(ssp->mmio_base + SSCR0);
sscr0 |= SSCR0_SSE;
__raw_writel(sscr0, ssp->mmio_base + SSCR0);
}
/**
@ -183,7 +183,12 @@ void ssp_enable(struct ssp_dev *dev)
*/
void ssp_disable(struct ssp_dev *dev)
{
SSCR0_P(dev->port) &= ~SSCR0_SSE;
struct ssp_device *ssp = dev->ssp;
uint32_t sscr0;
sscr0 = __raw_readl(ssp->mmio_base + SSCR0);
sscr0 &= ~SSCR0_SSE;
__raw_writel(sscr0, ssp->mmio_base + SSCR0);
}
/**
@ -192,14 +197,16 @@ void ssp_disable(struct ssp_dev *dev)
*
* Save the configured SSP state for suspend.
*/
void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp)
void ssp_save_state(struct ssp_dev *dev, struct ssp_state *state)
{
ssp->cr0 = SSCR0_P(dev->port);
ssp->cr1 = SSCR1_P(dev->port);
ssp->to = SSTO_P(dev->port);
ssp->psp = SSPSP_P(dev->port);
struct ssp_device *ssp = dev->ssp;
SSCR0_P(dev->port) &= ~SSCR0_SSE;
state->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
state->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
state->to = __raw_readl(ssp->mmio_base + SSTO);
state->psp = __raw_readl(ssp->mmio_base + SSPSP);
ssp_disable(dev);
}
/**
@ -208,16 +215,18 @@ void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp)
*
* Restore the SSP configuration saved previously by ssp_save_state.
*/
void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp)
void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *state)
{
SSSR_P(dev->port) = SSSR_ROR | SSSR_TUR | SSSR_BCE;
struct ssp_device *ssp = dev->ssp;
uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
SSCR0_P(dev->port) = ssp->cr0 & ~SSCR0_SSE;
SSCR1_P(dev->port) = ssp->cr1;
SSTO_P(dev->port) = ssp->to;
SSPSP_P(dev->port) = ssp->psp;
__raw_writel(sssr, ssp->mmio_base + SSSR);
SSCR0_P(dev->port) = ssp->cr0;
__raw_writel(state->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
__raw_writel(state->cr1, ssp->mmio_base + SSCR1);
__raw_writel(state->to, ssp->mmio_base + SSTO);
__raw_writel(state->psp, ssp->mmio_base + SSPSP);
__raw_writel(state->cr0, ssp->mmio_base + SSCR0);
}
/**
@ -231,15 +240,17 @@ void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp)
*/
int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed)
{
struct ssp_device *ssp = dev->ssp;
dev->mode = mode;
dev->flags = flags;
dev->psp_flags = psp_flags;
dev->speed = speed;
/* set up port type, speed, port settings */
SSCR0_P(dev->port) = (dev->speed | dev->mode);
SSCR1_P(dev->port) = dev->flags;
SSPSP_P(dev->port) = dev->psp_flags;
__raw_writel((dev->speed | dev->mode), ssp->mmio_base + SSCR0);
__raw_writel(dev->flags, ssp->mmio_base + SSCR1);
__raw_writel(dev->psp_flags, ssp->mmio_base + SSPSP);
return 0;
}
@ -256,44 +267,32 @@ int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 spee
*/
int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags)
{
struct ssp_device *ssp;
int ret;
if (port > PXA_SSP_PORTS || port == 0)
ssp = ssp_request(port, "SSP");
if (ssp == NULL)
return -ENODEV;
mutex_lock(&mutex);
if (use_count[port - 1]) {
mutex_unlock(&mutex);
return -EBUSY;
}
use_count[port - 1]++;
if (!request_mem_region(__PREG(SSCR0_P(port)), 0x2c, "SSP")) {
use_count[port - 1]--;
mutex_unlock(&mutex);
return -EBUSY;
}
dev->ssp = ssp;
dev->port = port;
/* do we need to get irq */
if (!(init_flags & SSP_NO_IRQ)) {
ret = request_irq(ssp_info[port-1].irq, ssp_interrupt,
ret = request_irq(ssp->irq, ssp_interrupt,
0, "SSP", dev);
if (ret)
goto out_region;
dev->irq = ssp_info[port-1].irq;
dev->irq = ssp->irq;
} else
dev->irq = 0;
/* turn on SSP port clock */
pxa_set_cken(ssp_info[port-1].clock, 1);
mutex_unlock(&mutex);
clk_enable(ssp->clk);
return 0;
out_region:
release_mem_region(__PREG(SSCR0_P(port)), 0x2c);
use_count[port - 1]--;
mutex_unlock(&mutex);
ssp_free(ssp);
return ret;
}
@ -304,22 +303,239 @@ out_region:
*/
void ssp_exit(struct ssp_dev *dev)
{
mutex_lock(&mutex);
SSCR0_P(dev->port) &= ~SSCR0_SSE;
struct ssp_device *ssp = dev->ssp;
if (dev->port > PXA_SSP_PORTS || dev->port == 0) {
printk(KERN_WARNING "SSP: tried to close invalid port\n");
mutex_unlock(&mutex);
return;
ssp_disable(dev);
free_irq(dev->irq, dev);
clk_disable(ssp->clk);
ssp_free(ssp);
}
static DEFINE_MUTEX(ssp_lock);
static LIST_HEAD(ssp_list);
struct ssp_device *ssp_request(int port, const char *label)
{
struct ssp_device *ssp = NULL;
mutex_lock(&ssp_lock);
list_for_each_entry(ssp, &ssp_list, node) {
if (ssp->port_id == port && ssp->use_count == 0) {
ssp->use_count++;
ssp->label = label;
break;
}
}
pxa_set_cken(ssp_info[dev->port-1].clock, 0);
if (dev->irq)
free_irq(dev->irq, dev);
release_mem_region(__PREG(SSCR0_P(dev->port)), 0x2c);
use_count[dev->port - 1]--;
mutex_unlock(&mutex);
mutex_unlock(&ssp_lock);
if (ssp->port_id != port)
return NULL;
return ssp;
}
EXPORT_SYMBOL(ssp_request);
void ssp_free(struct ssp_device *ssp)
{
mutex_lock(&ssp_lock);
if (ssp->use_count) {
ssp->use_count--;
ssp->label = NULL;
} else
dev_err(&ssp->pdev->dev, "device already free\n");
mutex_unlock(&ssp_lock);
}
EXPORT_SYMBOL(ssp_free);
static int __devinit ssp_probe(struct platform_device *pdev, int type)
{
struct resource *res;
struct ssp_device *ssp;
int ret = 0;
ssp = kzalloc(sizeof(struct ssp_device), GFP_KERNEL);
if (ssp == NULL) {
dev_err(&pdev->dev, "failed to allocate memory");
return -ENOMEM;
}
ssp->clk = clk_get(&pdev->dev, "SSPCLK");
if (IS_ERR(ssp->clk)) {
ret = PTR_ERR(ssp->clk);
goto err_free;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL) {
dev_err(&pdev->dev, "no memory resource defined\n");
ret = -ENODEV;
goto err_free_clk;
}
res = request_mem_region(res->start, res->end - res->start + 1,
pdev->name);
if (res == NULL) {
dev_err(&pdev->dev, "failed to request memory resource\n");
ret = -EBUSY;
goto err_free_clk;
}
ssp->phys_base = res->start;
ssp->mmio_base = ioremap(res->start, res->end - res->start + 1);
if (ssp->mmio_base == NULL) {
dev_err(&pdev->dev, "failed to ioremap() registers\n");
ret = -ENODEV;
goto err_free_mem;
}
ssp->irq = platform_get_irq(pdev, 0);
if (ssp->irq < 0) {
dev_err(&pdev->dev, "no IRQ resource defined\n");
ret = -ENODEV;
goto err_free_io;
}
res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
if (res == NULL) {
dev_err(&pdev->dev, "no SSP RX DRCMR defined\n");
ret = -ENODEV;
goto err_free_io;
}
ssp->drcmr_rx = res->start;
res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
if (res == NULL) {
dev_err(&pdev->dev, "no SSP TX DRCMR defined\n");
ret = -ENODEV;
goto err_free_io;
}
ssp->drcmr_tx = res->start;
/* PXA2xx/3xx SSP ports starts from 1 and the internal pdev->id
* starts from 0, do a translation here
*/
ssp->port_id = pdev->id + 1;
ssp->use_count = 0;
ssp->type = type;
mutex_lock(&ssp_lock);
list_add(&ssp->node, &ssp_list);
mutex_unlock(&ssp_lock);
platform_set_drvdata(pdev, ssp);
return 0;
err_free_io:
iounmap(ssp->mmio_base);
err_free_mem:
release_mem_region(res->start, res->end - res->start + 1);
err_free_clk:
clk_put(ssp->clk);
err_free:
kfree(ssp);
return ret;
}
static int __devexit ssp_remove(struct platform_device *pdev)
{
struct resource *res;
struct ssp_device *ssp;
ssp = platform_get_drvdata(pdev);
if (ssp == NULL)
return -ENODEV;
iounmap(ssp->mmio_base);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(res->start, res->end - res->start + 1);
clk_put(ssp->clk);
mutex_lock(&ssp_lock);
list_del(&ssp->node);
mutex_unlock(&ssp_lock);
kfree(ssp);
return 0;
}
static int __devinit pxa25x_ssp_probe(struct platform_device *pdev)
{
return ssp_probe(pdev, PXA25x_SSP);
}
static int __devinit pxa25x_nssp_probe(struct platform_device *pdev)
{
return ssp_probe(pdev, PXA25x_NSSP);
}
static int __devinit pxa27x_ssp_probe(struct platform_device *pdev)
{
return ssp_probe(pdev, PXA27x_SSP);
}
static struct platform_driver pxa25x_ssp_driver = {
.driver = {
.name = "pxa25x-ssp",
},
.probe = pxa25x_ssp_probe,
.remove = __devexit_p(ssp_remove),
};
static struct platform_driver pxa25x_nssp_driver = {
.driver = {
.name = "pxa25x-nssp",
},
.probe = pxa25x_nssp_probe,
.remove = __devexit_p(ssp_remove),
};
static struct platform_driver pxa27x_ssp_driver = {
.driver = {
.name = "pxa27x-ssp",
},
.probe = pxa27x_ssp_probe,
.remove = __devexit_p(ssp_remove),
};
static int __init pxa_ssp_init(void)
{
int ret = 0;
ret = platform_driver_register(&pxa25x_ssp_driver);
if (ret) {
printk(KERN_ERR "failed to register pxa25x_ssp_driver");
return ret;
}
ret = platform_driver_register(&pxa25x_nssp_driver);
if (ret) {
printk(KERN_ERR "failed to register pxa25x_nssp_driver");
return ret;
}
ret = platform_driver_register(&pxa27x_ssp_driver);
if (ret) {
printk(KERN_ERR "failed to register pxa27x_ssp_driver");
return ret;
}
return ret;
}
static void __exit pxa_ssp_exit(void)
{
platform_driver_unregister(&pxa25x_ssp_driver);
platform_driver_unregister(&pxa25x_nssp_driver);
platform_driver_unregister(&pxa27x_ssp_driver);
}
arch_initcall(pxa_ssp_init);
module_exit(pxa_ssp_exit);
EXPORT_SYMBOL(ssp_write_word);
EXPORT_SYMBOL(ssp_read_word);

83
arch/arm/mach-pxa/standby.S
View File

@ -17,6 +17,7 @@
.text
#ifdef CONFIG_PXA27x
ENTRY(pxa_cpu_standby)
ldr r0, =PSSR
mov r1, #(PSSR_PH | PSSR_STS)
@ -29,3 +30,85 @@ ENTRY(pxa_cpu_standby)
1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby
str r1, [r0] @ make sure PSSR_PH/STS are clear
mov pc, lr
#endif
#ifdef CONFIG_PXA3xx
#define MDCNFG 0x0000
#define MDCNFG_DMCEN (1 << 30)
#define DDR_HCAL 0x0060
#define DDR_HCAL_HCRNG 0x1f
#define DDR_HCAL_HCPROG (1 << 28)
#define DDR_HCAL_HCEN (1 << 31)
#define DMCIER 0x0070
#define DMCIER_EDLP (1 << 29)
#define DMCISR 0x0078
#define RCOMP 0x0100
#define RCOMP_SWEVAL (1 << 31)
ENTRY(pm_enter_standby_start)
mov r1, #0xf6000000 @ DMEMC_REG_BASE (MDCNFG)
add r1, r1, #0x00100000
/*
* Preload the TLB entry for accessing the dynamic memory
* controller registers. Note that page table lookups will
* fail until the dynamic memory controller has been
* reinitialised - and that includes MMU page table walks.
* This also means that only the dynamic memory controller
* can be reliably accessed in the code following standby.
*/
ldr r2, [r1] @ Dummy read MDCNFG
mcr p14, 0, r0, c7, c0, 0
.rept 8
nop
.endr
ldr r0, [r1, #DDR_HCAL] @ Clear (and wait for) HCEN
bic r0, r0, #DDR_HCAL_HCEN
str r0, [r1, #DDR_HCAL]
1: ldr r0, [r1, #DDR_HCAL]
tst r0, #DDR_HCAL_HCEN
bne 1b
ldr r0, [r1, #RCOMP] @ Initiate RCOMP
orr r0, r0, #RCOMP_SWEVAL
str r0, [r1, #RCOMP]
mov r0, #~0 @ Clear interrupts
str r0, [r1, #DMCISR]
ldr r0, [r1, #DMCIER] @ set DMIER[EDLP]
orr r0, r0, #DMCIER_EDLP
str r0, [r1, #DMCIER]
ldr r0, [r1, #DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
bic r0, r0, #DDR_HCAL_HCRNG
orr r0, r0, #DDR_HCAL_HCEN | DDR_HCAL_HCPROG
str r0, [r1, #DDR_HCAL]
1: ldr r0, [r1, #DMCISR]
tst r0, #DMCIER_EDLP
beq 1b
ldr r0, [r1, #MDCNFG] @ set MDCNFG[DMCEN]
orr r0, r0, #MDCNFG_DMCEN
str r0, [r1, #MDCNFG]
1: ldr r0, [r1, #MDCNFG]
tst r0, #MDCNFG_DMCEN
beq 1b
ldr r0, [r1, #DDR_HCAL] @ set DDR_HCAL[HCRNG]
orr r0, r0, #2 @ HCRNG
str r0, [r1, #DDR_HCAL]
ldr r0, [r1, #DMCIER] @ Clear the interrupt
bic r0, r0, #0x20000000
str r0, [r1, #DMCIER]
mov pc, lr
ENTRY(pm_enter_standby_end)
#endif

76
arch/arm/mach-pxa/time.c
View File

@ -59,55 +59,17 @@ unsigned long long sched_clock(void)
}
#define MIN_OSCR_DELTA 16
static irqreturn_t
pxa_ost0_interrupt(int irq, void *dev_id)
{
int next_match;
struct clock_event_device *c = dev_id;
if (c->mode == CLOCK_EVT_MODE_ONESHOT) {
/* Disarm the compare/match, signal the event. */
OIER &= ~OIER_E0;
OSSR = OSSR_M0;
c->event_handler(c);
} else if (c->mode == CLOCK_EVT_MODE_PERIODIC) {
/* Call the event handler as many times as necessary
* to recover missed events, if any (if we update
* OSMR0 and OSCR0 is still ahead of us, we've missed
* the event). As we're dealing with that, re-arm the
* compare/match for the next event.
*
* HACK ALERT:
*
* There's a latency between the instruction that
* writes to OSMR0 and the actual commit to the
* physical hardware, because the CPU doesn't (have
* to) run at bus speed, there's a write buffer
* between the CPU and the bus, etc. etc. So if the
* target OSCR0 is "very close", to the OSMR0 load
* value, the update to OSMR0 might not get to the
* hardware in time and we'll miss that interrupt.
*
* To be safe, if the new OSMR0 is "very close" to the
* target OSCR0 value, we call the event_handler as
* though the event actually happened. According to
* Nico's comment in the previous version of this
* code, experience has shown that 6 OSCR ticks is
* "very close" but he went with 8. We will use 16,
* based on the results of testing on PXA270.
*
* To be doubly sure, we also tell clkevt via
* clockevents_register_device() not to ask for
* anything that might put us "very close".
*/
#define MIN_OSCR_DELTA 16
do {
OSSR = OSSR_M0;
next_match = (OSMR0 += LATCH);
c->event_handler(c);
} while (((signed long)(next_match - OSCR) <= MIN_OSCR_DELTA)
&& (c->mode == CLOCK_EVT_MODE_PERIODIC));
}
return IRQ_HANDLED;
}
@ -133,14 +95,6 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
unsigned long irqflags;
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
raw_local_irq_save(irqflags);
OSSR = OSSR_M0;
OIER |= OIER_E0;
OSMR0 = OSCR + LATCH;
raw_local_irq_restore(irqflags);
break;
case CLOCK_EVT_MODE_ONESHOT:
raw_local_irq_save(irqflags);
OIER &= ~OIER_E0;
@ -158,13 +112,14 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
break;
case CLOCK_EVT_MODE_RESUME:
case CLOCK_EVT_MODE_PERIODIC:
break;
}
}
static struct clock_event_device ckevt_pxa_osmr0 = {
.name = "osmr0",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.features = CLOCK_EVT_FEAT_ONESHOT,
.shift = 32,
.rating = 200,
.cpumask = CPU_MASK_CPU0,
@ -214,7 +169,7 @@ static void __init pxa_timer_init(void)
ckevt_pxa_osmr0.max_delta_ns =
clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
ckevt_pxa_osmr0.min_delta_ns =
clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1;
clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
cksrc_pxa_oscr0.mult =
clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift);
@ -226,7 +181,7 @@ static void __init pxa_timer_init(void)
}
#ifdef CONFIG_PM
static unsigned long osmr[4], oier;
static unsigned long osmr[4], oier, oscr;
static void pxa_timer_suspend(void)
{
@ -235,23 +190,26 @@ static void pxa_timer_suspend(void)
osmr[2] = OSMR2;
osmr[3] = OSMR3;
oier = OIER;
oscr = OSCR;
}
static void pxa_timer_resume(void)
{
/*
* Ensure that we have at least MIN_OSCR_DELTA between match
* register 0 and the OSCR, to guarantee that we will receive
* the one-shot timer interrupt. We adjust OSMR0 in preference
* to OSCR to guarantee that OSCR is monotonically incrementing.
*/
if (osmr[0] - oscr < MIN_OSCR_DELTA)
osmr[0] += MIN_OSCR_DELTA;
OSMR0 = osmr[0];
OSMR1 = osmr[1];
OSMR2 = osmr[2];
OSMR3 = osmr[3];
OIER = oier;
/*
* OSCR0 is the system timer, which has to increase
* monotonically until it rolls over in hardware. The value
* (OSMR0 - LATCH) is OSCR0 at the most recent system tick,
* which is a handy value to restore to OSCR0.
*/
OSCR = OSMR0 - LATCH;
OSCR = oscr;
}
#else
#define pxa_timer_suspend NULL

11
arch/arm/mach-pxa/tosa.c
View File

@ -184,16 +184,13 @@ static int tosa_mci_init(struct device *dev, irq_handler_t tosa_detect_int, void
tosa_mci_platform_data.detect_delay = msecs_to_jiffies(250);
err = request_irq(TOSA_IRQ_GPIO_nSD_DETECT, tosa_detect_int, IRQF_DISABLED,
err = request_irq(TOSA_IRQ_GPIO_nSD_DETECT, tosa_detect_int,
IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"MMC/SD card detect", data);
if (err) {
if (err)
printk(KERN_ERR "tosa_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
return -1;
}
set_irq_type(TOSA_IRQ_GPIO_nSD_DETECT, IRQT_BOTHEDGE);
return 0;
return err;
}
static void tosa_mci_setpower(struct device *dev, unsigned int vdd)

7
arch/arm/mach-pxa/trizeps4.c
View File

@ -296,11 +296,10 @@ static int trizeps4_mci_init(struct device *dev, irq_handler_t mci_detect_int, v
err = request_irq(TRIZEPS4_MMC_IRQ, mci_detect_int,
IRQF_DISABLED | IRQF_TRIGGER_RISING,
"MMC card detect", data);
if (err) {
if (err)
printk(KERN_ERR "trizeps4_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
return -1;
}
return 0;
return err;
}
static void trizeps4_mci_exit(struct device *dev, void *data)

96
arch/arm/mach-pxa/zylonite.c
View File

@ -25,9 +25,13 @@
#include <asm/arch/gpio.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/zylonite.h>
#include <asm/arch/mmc.h>
#include "generic.h"
#define MAX_SLOTS 3
struct platform_mmc_slot zylonite_mmc_slot[MAX_SLOTS];
int gpio_backlight;
int gpio_eth_irq;
@ -43,7 +47,7 @@ static struct resource smc91x_resources[] = {
[1] = {
.start = -1, /* for run-time assignment */
.end = -1,
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
}
};
@ -156,6 +160,95 @@ static void __init zylonite_init_lcd(void)
static inline void zylonite_init_lcd(void) {}
#endif
#if defined(CONFIG_MMC)
static int zylonite_mci_ro(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
return gpio_get_value(zylonite_mmc_slot[pdev->id].gpio_wp);
}
static int zylonite_mci_init(struct device *dev,
irq_handler_t zylonite_detect_int,
void *data)
{
struct platform_device *pdev = to_platform_device(dev);
int err, cd_irq, gpio_cd, gpio_wp;
cd_irq = gpio_to_irq(zylonite_mmc_slot[pdev->id].gpio_cd);
gpio_cd = zylonite_mmc_slot[pdev->id].gpio_cd;
gpio_wp = zylonite_mmc_slot[pdev->id].gpio_wp;
/*
* setup GPIO for Zylonite MMC controller
*/
err = gpio_request(gpio_cd, "mmc card detect");
if (err)
goto err_request_cd;
gpio_direction_input(gpio_cd);
err = gpio_request(gpio_wp, "mmc write protect");
if (err)
goto err_request_wp;
gpio_direction_input(gpio_wp);
err = request_irq(cd_irq, zylonite_detect_int,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"MMC card detect", data);
if (err) {
printk(KERN_ERR "%s: MMC/SD/SDIO: "
"can't request card detect IRQ\n", __func__);
goto err_request_irq;
}
return 0;
err_request_irq:
gpio_free(gpio_wp);
err_request_wp:
gpio_free(gpio_cd);
err_request_cd:
return err;
}
static void zylonite_mci_exit(struct device *dev, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
int cd_irq, gpio_cd, gpio_wp;
cd_irq = gpio_to_irq(zylonite_mmc_slot[pdev->id].gpio_cd);
gpio_cd = zylonite_mmc_slot[pdev->id].gpio_cd;
gpio_wp = zylonite_mmc_slot[pdev->id].gpio_wp;
free_irq(cd_irq, data);
gpio_free(gpio_cd);
gpio_free(gpio_wp);
}
static struct pxamci_platform_data zylonite_mci_platform_data = {
.detect_delay = 20,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.init = zylonite_mci_init,
.exit = zylonite_mci_exit,
.get_ro = zylonite_mci_ro,
};
static struct pxamci_platform_data zylonite_mci2_platform_data = {
.detect_delay = 20,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
};
static void __init zylonite_init_mmc(void)
{
pxa_set_mci_info(&zylonite_mci_platform_data);
pxa3xx_set_mci2_info(&zylonite_mci2_platform_data);
if (cpu_is_pxa310())
pxa3xx_set_mci3_info(&zylonite_mci_platform_data);
}
#else
static inline void zylonite_init_mmc(void) {}
#endif
static void __init zylonite_init(void)
{
/* board-processor specific initialization */
@ -171,6 +264,7 @@ static void __init zylonite_init(void)
platform_device_register(&smc91x_device);
zylonite_init_lcd();
zylonite_init_mmc();
}
MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")

65
arch/arm/mach-pxa/zylonite_pxa300.c
View File

@ -53,13 +53,13 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
/* BTUART */
GPIO111_UART2_RTS,
GPIO112_UART2_RXD,
GPIO112_UART2_RXD | MFP_LPM_EDGE_FALL,
GPIO113_UART2_TXD,
GPIO114_UART2_CTS,
GPIO114_UART2_CTS | MFP_LPM_EDGE_BOTH,
/* STUART */
GPIO109_UART3_TXD,
GPIO110_UART3_RXD,
GPIO110_UART3_RXD | MFP_LPM_EDGE_FALL,
/* AC97 */
GPIO23_AC97_nACRESET,
@ -70,16 +70,16 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
GPIO28_AC97_SYNC,
/* Keypad */
GPIO107_KP_DKIN_0,
GPIO108_KP_DKIN_1,
GPIO115_KP_MKIN_0,
GPIO116_KP_MKIN_1,
GPIO117_KP_MKIN_2,
GPIO118_KP_MKIN_3,
GPIO119_KP_MKIN_4,
GPIO120_KP_MKIN_5,
GPIO2_2_KP_MKIN_6,
GPIO3_2_KP_MKIN_7,
GPIO107_KP_DKIN_0 | MFP_LPM_EDGE_BOTH,
GPIO108_KP_DKIN_1 | MFP_LPM_EDGE_BOTH,
GPIO115_KP_MKIN_0 | MFP_LPM_EDGE_BOTH,
GPIO116_KP_MKIN_1 | MFP_LPM_EDGE_BOTH,
GPIO117_KP_MKIN_2 | MFP_LPM_EDGE_BOTH,
GPIO118_KP_MKIN_3 | MFP_LPM_EDGE_BOTH,
GPIO119_KP_MKIN_4 | MFP_LPM_EDGE_BOTH,
GPIO120_KP_MKIN_5 | MFP_LPM_EDGE_BOTH,
GPIO2_2_KP_MKIN_6 | MFP_LPM_EDGE_BOTH,
GPIO3_2_KP_MKIN_7 | MFP_LPM_EDGE_BOTH,
GPIO121_KP_MKOUT_0,
GPIO122_KP_MKOUT_1,
GPIO123_KP_MKOUT_2,
@ -88,16 +88,33 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
GPIO4_2_KP_MKOUT_5,
GPIO5_2_KP_MKOUT_6,
GPIO6_2_KP_MKOUT_7,
/* MMC1 */
GPIO3_MMC1_DAT0,
GPIO4_MMC1_DAT1 | MFP_LPM_EDGE_BOTH,
GPIO5_MMC1_DAT2,
GPIO6_MMC1_DAT3,
GPIO7_MMC1_CLK,
GPIO8_MMC1_CMD, /* CMD0 for slot 0 */
GPIO15_GPIO, /* CMD1 default as GPIO for slot 0 */
/* MMC2 */
GPIO9_MMC2_DAT0,
GPIO10_MMC2_DAT1 | MFP_LPM_EDGE_BOTH,
GPIO11_MMC2_DAT2,
GPIO12_MMC2_DAT3,
GPIO13_MMC2_CLK,
GPIO14_MMC2_CMD,
};
static mfp_cfg_t pxa300_mfp_cfg[] __initdata = {
/* FFUART */
GPIO30_UART1_RXD,
GPIO30_UART1_RXD | MFP_LPM_EDGE_FALL,
GPIO31_UART1_TXD,
GPIO32_UART1_CTS,
GPIO37_UART1_RTS,
GPIO33_UART1_DCD,
GPIO34_UART1_DSR,
GPIO34_UART1_DSR | MFP_LPM_EDGE_FALL,
GPIO35_UART1_RI,
GPIO36_UART1_DTR,
@ -108,7 +125,7 @@ static mfp_cfg_t pxa300_mfp_cfg[] __initdata = {
static mfp_cfg_t pxa310_mfp_cfg[] __initdata = {
/* FFUART */
GPIO99_UART1_RXD,
GPIO99_UART1_RXD | MFP_LPM_EDGE_FALL,
GPIO100_UART1_TXD,
GPIO101_UART1_CTS,
GPIO106_UART1_RTS,
@ -116,6 +133,14 @@ static mfp_cfg_t pxa310_mfp_cfg[] __initdata = {
/* Ethernet */
GPIO2_nCS3,
GPIO102_GPIO,
/* MMC3 */
GPIO7_2_MMC3_DAT0,
GPIO8_2_MMC3_DAT1 | MFP_LPM_EDGE_BOTH,
GPIO9_2_MMC3_DAT2,
GPIO10_2_MMC3_DAT3,
GPIO103_MMC3_CLK,
GPIO105_MMC3_CMD,
};
#define NUM_LCD_DETECT_PINS 7
@ -174,6 +199,10 @@ void __init zylonite_pxa300_init(void)
/* GPIO pin assignment */
gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO20);
/* MMC card detect & write protect for controller 0 */
zylonite_mmc_slot[0].gpio_cd = EXT_GPIO(0);
zylonite_mmc_slot[0].gpio_wp = EXT_GPIO(2);
}
if (cpu_is_pxa300()) {
@ -184,5 +213,9 @@ void __init zylonite_pxa300_init(void)
if (cpu_is_pxa310()) {
pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa310_mfp_cfg));
gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO102);
/* MMC card detect & write protect for controller 2 */
zylonite_mmc_slot[2].gpio_cd = EXT_GPIO(30);
zylonite_mmc_slot[2].gpio_wp = EXT_GPIO(31);
}
}

45
arch/arm/mach-pxa/zylonite_pxa320.c
View File

@ -51,11 +51,11 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
GPIO17_2_LCD_BIAS,
/* FFUART */
GPIO41_UART1_RXD,
GPIO41_UART1_RXD | MFP_LPM_EDGE_FALL,
GPIO42_UART1_TXD,
GPIO43_UART1_CTS,
GPIO44_UART1_DCD,
GPIO45_UART1_DSR,
GPIO45_UART1_DSR | MFP_LPM_EDGE_FALL,
GPIO46_UART1_RI,
GPIO47_UART1_DTR,
GPIO48_UART1_RTS,
@ -73,16 +73,16 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
GPIO33_I2C_SDA,
/* Keypad */
GPIO105_KP_DKIN_0,
GPIO106_KP_DKIN_1,
GPIO113_KP_MKIN_0,
GPIO114_KP_MKIN_1,
GPIO115_KP_MKIN_2,
GPIO116_KP_MKIN_3,
GPIO117_KP_MKIN_4,
GPIO118_KP_MKIN_5,
GPIO119_KP_MKIN_6,
GPIO120_KP_MKIN_7,
GPIO105_KP_DKIN_0 | MFP_LPM_EDGE_BOTH,
GPIO106_KP_DKIN_1 | MFP_LPM_EDGE_BOTH,
GPIO113_KP_MKIN_0 | MFP_LPM_EDGE_BOTH,
GPIO114_KP_MKIN_1 | MFP_LPM_EDGE_BOTH,
GPIO115_KP_MKIN_2 | MFP_LPM_EDGE_BOTH,
GPIO116_KP_MKIN_3 | MFP_LPM_EDGE_BOTH,
GPIO117_KP_MKIN_4 | MFP_LPM_EDGE_BOTH,
GPIO118_KP_MKIN_5 | MFP_LPM_EDGE_BOTH,
GPIO119_KP_MKIN_6 | MFP_LPM_EDGE_BOTH,
GPIO120_KP_MKIN_7 | MFP_LPM_EDGE_BOTH,
GPIO121_KP_MKOUT_0,
GPIO122_KP_MKOUT_1,
GPIO123_KP_MKOUT_2,
@ -95,6 +95,23 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
/* Ethernet */
GPIO4_nCS3,
GPIO90_GPIO,
/* MMC1 */
GPIO18_MMC1_DAT0,
GPIO19_MMC1_DAT1 | MFP_LPM_EDGE_BOTH,
GPIO20_MMC1_DAT2,
GPIO21_MMC1_DAT3,
GPIO22_MMC1_CLK,
GPIO23_MMC1_CMD,/* CMD0 for slot 0 */
GPIO31_GPIO, /* CMD1 default as GPIO for slot 0 */
/* MMC2 */
GPIO24_MMC2_DAT0,
GPIO25_MMC2_DAT1 | MFP_LPM_EDGE_BOTH,
GPIO26_MMC2_DAT2,
GPIO27_MMC2_DAT3,
GPIO28_MMC2_CLK,
GPIO29_MMC2_CMD,
};
#define NUM_LCD_DETECT_PINS 7
@ -169,5 +186,9 @@ void __init zylonite_pxa320_init(void)
/* GPIO pin assignment */
gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO14);
gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO9);
/* MMC card detect & write protect for controller 0 */
zylonite_mmc_slot[0].gpio_cd = mfp_to_gpio(MFP_PIN_GPIO1);
zylonite_mmc_slot[0].gpio_wp = mfp_to_gpio(MFP_PIN_GPIO5);
}
}

2
arch/arm/plat-omap/debug-devices.c
View File

@ -29,7 +29,7 @@ static struct resource smc91x_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};

8
drivers/input/touchscreen/corgi_ts.c
View File

@ -74,10 +74,10 @@ extern unsigned int get_clk_frequency_khz(int info);
static unsigned long calc_waittime(struct corgi_ts *corgi_ts)
{
unsigned long hsync_len = corgi_ts->machinfo->get_hsync_len();
unsigned long hsync_invperiod = corgi_ts->machinfo->get_hsync_invperiod();
if (hsync_len)
return get_clk_frequency_khz(0)*1000/hsync_len;
if (hsync_invperiod)
return get_clk_frequency_khz(0)*1000/hsync_invperiod;
else
return 0;
}
@ -114,7 +114,7 @@ static int sync_receive_data_send_cmd(struct corgi_ts *corgi_ts, int doRecive, i
if (timer2-timer1 > wait_time) {
/* too slow - timeout, try again */
corgi_ts->machinfo->wait_hsync();
/* get OSCR */
/* get CCNT */
CCNT(timer1);
/* Wait after HSync */
CCNT(timer2);

45
drivers/mmc/host/pxamci.c
View File

@ -65,6 +65,8 @@ struct pxamci_host {
unsigned int dma_len;
unsigned int dma_dir;
unsigned int dma_drcmrrx;
unsigned int dma_drcmrtx;
};
static void pxamci_stop_clock(struct pxamci_host *host)
@ -131,13 +133,13 @@ static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
if (data->flags & MMC_DATA_READ) {
host->dma_dir = DMA_FROM_DEVICE;
dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG;
DRCMRTXMMC = 0;
DRCMRRXMMC = host->dma | DRCMR_MAPVLD;
DRCMR(host->dma_drcmrtx) = 0;
DRCMR(host->dma_drcmrrx) = host->dma | DRCMR_MAPVLD;
} else {
host->dma_dir = DMA_TO_DEVICE;
dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC;
DRCMRRXMMC = 0;
DRCMRTXMMC = host->dma | DRCMR_MAPVLD;
DRCMR(host->dma_drcmrrx) = 0;
DRCMR(host->dma_drcmrtx) = host->dma | DRCMR_MAPVLD;
}
dcmd |= DCMD_BURST32 | DCMD_WIDTH1;
@ -375,6 +377,14 @@ static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
if (host->clkrt == CLKRT_OFF)
clk_enable(host->clk);
if (ios->clock == 26000000) {
/* to support 26MHz on pxa300/pxa310 */
host->clkrt = 7;
} else {
/* to handle (19.5MHz, 26MHz) */
if (!clk)
clk = 1;
/*
* clk might result in a lower divisor than we
* desire. check for that condition and adjust
@ -383,6 +393,7 @@ static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
if (rate / clk > ios->clock)
clk <<= 1;
host->clkrt = fls(clk) - 1;
}
/*
* we write clkrt on the next command
@ -459,7 +470,7 @@ static int pxamci_probe(struct platform_device *pdev)
{
struct mmc_host *mmc;
struct pxamci_host *host = NULL;
struct resource *r;
struct resource *r, *dmarx, *dmatx;
int ret, irq;
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@ -519,7 +530,8 @@ static int pxamci_probe(struct platform_device *pdev)
* Calculate minimum clock rate, rounding up.
*/
mmc->f_min = (host->clkrate + 63) / 64;
mmc->f_max = host->clkrate;
mmc->f_max = (cpu_is_pxa300() || cpu_is_pxa310()) ? 26000000
: host->clkrate;
mmc->ocr_avail = host->pdata ?
host->pdata->ocr_mask :
@ -529,6 +541,9 @@ static int pxamci_probe(struct platform_device *pdev)
if (!cpu_is_pxa21x() && !cpu_is_pxa25x()) {
mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
host->cmdat |= CMDAT_SDIO_INT_EN;
if (cpu_is_pxa300() || cpu_is_pxa310())
mmc->caps |= MMC_CAP_MMC_HIGHSPEED |
MMC_CAP_SD_HIGHSPEED;
}
host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
@ -570,6 +585,20 @@ static int pxamci_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, mmc);
dmarx = platform_get_resource(pdev, IORESOURCE_DMA, 0);
if (!dmarx) {
ret = -ENXIO;
goto out;
}
host->dma_drcmrrx = dmarx->start;
dmatx = platform_get_resource(pdev, IORESOURCE_DMA, 1);
if (!dmatx) {
ret = -ENXIO;
goto out;
}
host->dma_drcmrtx = dmatx->start;
if (host->pdata && host->pdata->init)
host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);
@ -613,8 +642,8 @@ static int pxamci_remove(struct platform_device *pdev)
END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
host->base + MMC_I_MASK);
DRCMRRXMMC = 0;
DRCMRTXMMC = 0;
DRCMR(host->dma_drcmrrx) = 0;
DRCMR(host->dma_drcmrtx) = 0;
free_irq(host->irq, host);
pxa_free_dma(host->dma);

2
drivers/mmc/host/pxamci.h
View File

@ -68,7 +68,7 @@
#define PRG_DONE (1 << 1)
#define DATA_TRAN_DONE (1 << 0)
#ifdef CONFIG_PXA27x
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
#define MMC_I_MASK_ALL 0x00001fff
#else
#define MMC_I_MASK_ALL 0x0000007f

3
drivers/net/dm9000.c
View File

@ -66,6 +66,7 @@
#include <linux/dm9000.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <asm/delay.h>
#include <asm/irq.h>
@ -113,7 +114,7 @@
#define writesl outsl
#define DM9000_IRQ_FLAGS (IRQF_SHARED | IRQF_TRIGGER_HIGH)
#else
#define DM9000_IRQ_FLAGS IRQF_SHARED
#define DM9000_IRQ_FLAGS (IRQF_SHARED | IRQT_RISING)
#endif
/*

19
drivers/net/smc91x.c
View File

@ -1775,7 +1775,8 @@ static int __init smc_findirq(void __iomem *ioaddr)
* o actually GRAB the irq.
* o GRAB the region
*/
static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr)
static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr,
unsigned long irq_flags)
{
struct smc_local *lp = netdev_priv(dev);
static int version_printed = 0;
@ -1941,7 +1942,7 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr)
}
/* Grab the IRQ */
retval = request_irq(dev->irq, &smc_interrupt, SMC_IRQ_FLAGS, dev->name, dev);
retval = request_irq(dev->irq, &smc_interrupt, irq_flags, dev->name, dev);
if (retval)
goto err_out;
@ -2123,8 +2124,9 @@ static void smc_release_datacs(struct platform_device *pdev, struct net_device *
static int smc_drv_probe(struct platform_device *pdev)
{
struct net_device *ndev;
struct resource *res;
struct resource *res, *ires;
unsigned int __iomem *addr;
unsigned long irq_flags = SMC_IRQ_FLAGS;
int ret;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
@ -2150,12 +2152,17 @@ static int smc_drv_probe(struct platform_device *pdev)
SET_NETDEV_DEV(ndev, &pdev->dev);
ndev->dma = (unsigned char)-1;
ndev->irq = platform_get_irq(pdev, 0);
if (ndev->irq < 0) {
ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (!ires) {
ret = -ENODEV;
goto out_free_netdev;
}
ndev->irq = ires->start;
if (SMC_IRQ_FLAGS == -1)
irq_flags = ires->flags & IRQF_TRIGGER_MASK;
ret = smc_request_attrib(pdev);
if (ret)
goto out_free_netdev;
@ -2181,7 +2188,7 @@ static int smc_drv_probe(struct platform_device *pdev)
#endif
platform_set_drvdata(pdev, ndev);
ret = smc_probe(ndev, addr);
ret = smc_probe(ndev, addr, irq_flags);
if (ret != 0)
goto out_iounmap;

24
drivers/net/smc91x.h
View File

@ -54,6 +54,7 @@
#define SMC_outw(v, a, r) writew(v, (a) + (r))
#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
#define SMC_IRQ_FLAGS (-1) /* from resource */
#elif defined(CONFIG_BLACKFIN)
@ -158,7 +159,7 @@
#define SMC_outw(v, a, r) writew(v, (a) + (r))
#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
#define SMC_IRQ_FLAGS (0)
#define SMC_IRQ_FLAGS (-1)
#elif defined(CONFIG_SA1100_ASSABET)
@ -177,6 +178,7 @@
#define SMC_outb(v, a, r) writeb(v, (a) + (r))
#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
#define SMC_IRQ_FLAGS (-1) /* from resource */
#elif defined(CONFIG_MACH_LOGICPD_PXA270)
@ -194,7 +196,8 @@
#elif defined(CONFIG_ARCH_INNOKOM) || \
defined(CONFIG_MACH_MAINSTONE) || \
defined(CONFIG_ARCH_PXA_IDP) || \
defined(CONFIG_ARCH_RAMSES)
defined(CONFIG_ARCH_RAMSES) || \
defined(CONFIG_ARCH_PCM027)
#define SMC_CAN_USE_8BIT 1
#define SMC_CAN_USE_16BIT 1
@ -210,6 +213,7 @@
#define SMC_outl(v, a, r) writel(v, (a) + (r))
#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
#define SMC_IRQ_FLAGS (-1) /* from resource */
/* We actually can't write halfwords properly if not word aligned */
static inline void
@ -238,6 +242,7 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
#define SMC_outb(v, a, r) writeb(v, (a) + (r))
#define SMC_outw(v, a, r) writew(v, (a) + (r))
#define SMC_IRQ_FLAGS (-1) /* from resource */
#elif defined(CONFIG_ARCH_OMAP)
@ -252,17 +257,7 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
#define SMC_outw(v, a, r) writew(v, (a) + (r))
#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
#include <asm/mach-types.h>
#include <asm/arch/cpu.h>
#define SMC_IRQ_FLAGS (( \
machine_is_omap_h2() \
|| machine_is_omap_h3() \
|| machine_is_omap_h4() \
|| (machine_is_omap_innovator() && !cpu_is_omap1510()) \
) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING)
#define SMC_IRQ_FLAGS (-1) /* from resource */
#elif defined(CONFIG_SH_SH4202_MICRODEV)
@ -453,8 +448,7 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
#define SMC_outl(v, a, r) writel(v, (a) + (r))
#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
#define SMC_IRQ_FLAGS (0)
#define SMC_IRQ_FLAGS (-1) /* from resource */
#else

1
drivers/pcmcia/pxa2xx_base.c
View File

@ -29,6 +29,7 @@
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <pcmcia/cs_types.h>
#include <pcmcia/ss.h>

31
drivers/rtc/rtc-sa1100.c
View File

@ -337,6 +337,8 @@ static int sa1100_rtc_probe(struct platform_device *pdev)
if (IS_ERR(rtc))
return PTR_ERR(rtc);
device_init_wakeup(&pdev->dev, 1);
platform_set_drvdata(pdev, rtc);
return 0;
@ -352,9 +354,38 @@ static int sa1100_rtc_remove(struct platform_device *pdev)
return 0;
}
#ifdef CONFIG_PM
static int sa1100_rtc_suspend(struct platform_device *pdev, pm_message_t state)
{
if (pdev->dev.power.power_state.event != state.event) {
if (state.event == PM_EVENT_SUSPEND &&
device_may_wakeup(&pdev->dev))
enable_irq_wake(IRQ_RTCAlrm);
pdev->dev.power.power_state = state;
}
return 0;
}
static int sa1100_rtc_resume(struct platform_device *pdev)
{
if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
if (device_may_wakeup(&pdev->dev))
disable_irq_wake(IRQ_RTCAlrm);
pdev->dev.power.power_state = PMSG_ON;
}
return 0;
}
#else
#define sa1100_rtc_suspend NULL
#define sa1100_rtc_resume NULL
#endif
static struct platform_driver sa1100_rtc_driver = {
.probe = sa1100_rtc_probe,
.remove = sa1100_rtc_remove,
.suspend = sa1100_rtc_suspend,
.resume = sa1100_rtc_resume,
.driver = {
.name = "sa1100-rtc",
},

1
drivers/spi/Kconfig
View File

@ -153,6 +153,7 @@ config SPI_OMAP24XX
config SPI_PXA2XX
tristate "PXA2xx SSP SPI master"
depends on SPI_MASTER && ARCH_PXA && EXPERIMENTAL
select PXA_SSP
help
This enables using a PXA2xx SSP port as a SPI master controller.
The driver can be configured to use any SSP port and additional

139
drivers/spi/pxa2xx_spi.c
View File

@ -27,6 +27,7 @@
#include <linux/spi/spi.h>
#include <linux/workqueue.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <asm/io.h>
#include <asm/irq.h>
@ -36,6 +37,8 @@
#include <asm/arch/hardware.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/regs-ssp.h>
#include <asm/arch/ssp.h>
#include <asm/arch/pxa2xx_spi.h>
MODULE_AUTHOR("Stephen Street");
@ -80,6 +83,9 @@ struct driver_data {
/* Driver model hookup */
struct platform_device *pdev;
/* SSP Info */
struct ssp_device *ssp;
/* SPI framework hookup */
enum pxa_ssp_type ssp_type;
struct spi_master *master;
@ -778,6 +784,16 @@ int set_dma_burst_and_threshold(struct chip_data *chip, struct spi_device *spi,
return retval;
}
static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
{
unsigned long ssp_clk = clk_get_rate(ssp->clk);
if (ssp->type == PXA25x_SSP)
return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
else
return ((ssp_clk / rate - 1) & 0xfff) << 8;
}
static void pump_transfers(unsigned long data)
{
struct driver_data *drv_data = (struct driver_data *)data;
@ -785,6 +801,7 @@ static void pump_transfers(unsigned long data)
struct spi_transfer *transfer = NULL;
struct spi_transfer *previous = NULL;
struct chip_data *chip = NULL;
struct ssp_device *ssp = drv_data->ssp;
void *reg = drv_data->ioaddr;
u32 clk_div = 0;
u8 bits = 0;
@ -866,12 +883,7 @@ static void pump_transfers(unsigned long data)
if (transfer->bits_per_word)
bits = transfer->bits_per_word;
if (reg == SSP1_VIRT)
clk_div = SSP1_SerClkDiv(speed);
else if (reg == SSP2_VIRT)
clk_div = SSP2_SerClkDiv(speed);
else if (reg == SSP3_VIRT)
clk_div = SSP3_SerClkDiv(speed);
clk_div = ssp_get_clk_div(ssp, speed);
if (bits <= 8) {
drv_data->n_bytes = 1;
@ -1074,6 +1086,7 @@ static int setup(struct spi_device *spi)
struct pxa2xx_spi_chip *chip_info = NULL;
struct chip_data *chip;
struct driver_data *drv_data = spi_master_get_devdata(spi->master);
struct ssp_device *ssp = drv_data->ssp;
unsigned int clk_div;
if (!spi->bits_per_word)
@ -1157,18 +1170,7 @@ static int setup(struct spi_device *spi)
}
}
if (drv_data->ioaddr == SSP1_VIRT)
clk_div = SSP1_SerClkDiv(spi->max_speed_hz);
else if (drv_data->ioaddr == SSP2_VIRT)
clk_div = SSP2_SerClkDiv(spi->max_speed_hz);
else if (drv_data->ioaddr == SSP3_VIRT)
clk_div = SSP3_SerClkDiv(spi->max_speed_hz);
else
{
dev_err(&spi->dev, "failed setup: unknown IO address=0x%p\n",
drv_data->ioaddr);
return -ENODEV;
}
clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
chip->speed_hz = spi->max_speed_hz;
chip->cr0 = clk_div
@ -1183,15 +1185,15 @@ static int setup(struct spi_device *spi)
/* NOTE: PXA25x_SSP _could_ use external clocking ... */
if (drv_data->ssp_type != PXA25x_SSP)
dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",
dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
spi->bits_per_word,
(CLOCK_SPEED_HZ)
clk_get_rate(ssp->clk)
/ (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
spi->mode & 0x3);
else
dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",
dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
spi->bits_per_word,
(CLOCK_SPEED_HZ/2)
clk_get_rate(ssp->clk)
/ (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
spi->mode & 0x3);
@ -1323,14 +1325,14 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev)
struct pxa2xx_spi_master *platform_info;
struct spi_master *master;
struct driver_data *drv_data = 0;
struct resource *memory_resource;
int irq;
struct ssp_device *ssp;
int status = 0;
platform_info = dev->platform_data;
if (platform_info->ssp_type == SSP_UNDEFINED) {
dev_err(&pdev->dev, "undefined SSP\n");
ssp = ssp_request(pdev->id, pdev->name);
if (ssp == NULL) {
dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
return -ENODEV;
}
@ -1338,12 +1340,14 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev)
master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
if (!master) {
dev_err(&pdev->dev, "can not alloc spi_master\n");
ssp_free(ssp);
return -ENOMEM;
}
drv_data = spi_master_get_devdata(master);
drv_data->master = master;
drv_data->master_info = platform_info;
drv_data->pdev = pdev;
drv_data->ssp = ssp;
master->bus_num = pdev->id;
master->num_chipselect = platform_info->num_chipselect;
@ -1351,21 +1355,13 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev)
master->setup = setup;
master->transfer = transfer;
drv_data->ssp_type = platform_info->ssp_type;
drv_data->ssp_type = ssp->type;
drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
sizeof(struct driver_data)), 8);
/* Setup register addresses */
memory_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!memory_resource) {
dev_err(&pdev->dev, "memory resources not defined\n");
status = -ENODEV;
goto out_error_master_alloc;
}
drv_data->ioaddr = (void *)io_p2v((unsigned long)(memory_resource->start));
drv_data->ssdr_physical = memory_resource->start + 0x00000010;
if (platform_info->ssp_type == PXA25x_SSP) {
drv_data->ioaddr = ssp->mmio_base;
drv_data->ssdr_physical = ssp->phys_base + SSDR;
if (ssp->type == PXA25x_SSP) {
drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
drv_data->dma_cr1 = 0;
drv_data->clear_sr = SSSR_ROR;
@ -1377,15 +1373,7 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev)
drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
}
/* Attach to IRQ */
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "irq resource not defined\n");
status = -ENODEV;
goto out_error_master_alloc;
}
status = request_irq(irq, ssp_int, 0, dev->bus_id, drv_data);
status = request_irq(ssp->irq, ssp_int, 0, dev->bus_id, drv_data);
if (status < 0) {
dev_err(&pdev->dev, "can not get IRQ\n");
goto out_error_master_alloc;
@ -1418,29 +1406,12 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev)
goto out_error_dma_alloc;
}
if (drv_data->ioaddr == SSP1_VIRT) {
DRCMRRXSSDR = DRCMR_MAPVLD
| drv_data->rx_channel;
DRCMRTXSSDR = DRCMR_MAPVLD
| drv_data->tx_channel;
} else if (drv_data->ioaddr == SSP2_VIRT) {
DRCMRRXSS2DR = DRCMR_MAPVLD
| drv_data->rx_channel;
DRCMRTXSS2DR = DRCMR_MAPVLD
| drv_data->tx_channel;
} else if (drv_data->ioaddr == SSP3_VIRT) {
DRCMRRXSS3DR = DRCMR_MAPVLD
| drv_data->rx_channel;
DRCMRTXSS3DR = DRCMR_MAPVLD
| drv_data->tx_channel;
} else {
dev_err(dev, "bad SSP type\n");
goto out_error_dma_alloc;
}
DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
}
/* Enable SOC clock */
pxa_set_cken(platform_info->clock_enable, 1);
clk_enable(ssp->clk);
/* Load default SSP configuration */
write_SSCR0(0, drv_data->ioaddr);
@ -1479,7 +1450,7 @@ out_error_queue_alloc:
destroy_queue(drv_data);
out_error_clock_enabled:
pxa_set_cken(platform_info->clock_enable, 0);
clk_disable(ssp->clk);
out_error_dma_alloc:
if (drv_data->tx_channel != -1)
@ -1488,17 +1459,18 @@ out_error_dma_alloc:
pxa_free_dma(drv_data->rx_channel);
out_error_irq_alloc:
free_irq(irq, drv_data);
free_irq(ssp->irq, drv_data);
out_error_master_alloc:
spi_master_put(master);
ssp_free(ssp);
return status;
}
static int pxa2xx_spi_remove(struct platform_device *pdev)
{
struct driver_data *drv_data = platform_get_drvdata(pdev);
int irq;
struct ssp_device *ssp = drv_data->ssp;
int status = 0;
if (!drv_data)
@ -1520,28 +1492,21 @@ static int pxa2xx_spi_remove(struct platform_device *pdev)
/* Disable the SSP at the peripheral and SOC level */
write_SSCR0(0, drv_data->ioaddr);
pxa_set_cken(drv_data->master_info->clock_enable, 0);
clk_disable(ssp->clk);
/* Release DMA */
if (drv_data->master_info->enable_dma) {
if (drv_data->ioaddr == SSP1_VIRT) {
DRCMRRXSSDR = 0;
DRCMRTXSSDR = 0;
} else if (drv_data->ioaddr == SSP2_VIRT) {
DRCMRRXSS2DR = 0;
DRCMRTXSS2DR = 0;
} else if (drv_data->ioaddr == SSP3_VIRT) {
DRCMRRXSS3DR = 0;
DRCMRTXSS3DR = 0;
}
DRCMR(ssp->drcmr_rx) = 0;
DRCMR(ssp->drcmr_tx) = 0;
pxa_free_dma(drv_data->tx_channel);
pxa_free_dma(drv_data->rx_channel);
}
/* Release IRQ */
irq = platform_get_irq(pdev, 0);
if (irq >= 0)
free_irq(irq, drv_data);
free_irq(ssp->irq, drv_data);
/* Release SSP */
ssp_free(ssp);
/* Disconnect from the SPI framework */
spi_unregister_master(drv_data->master);
@ -1576,6 +1541,7 @@ static int suspend_devices(struct device *dev, void *pm_message)
static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
{
struct driver_data *drv_data = platform_get_drvdata(pdev);
struct ssp_device *ssp = drv_data->ssp;
int status = 0;
/* Check all childern for current power state */
@ -1588,7 +1554,7 @@ static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
if (status != 0)
return status;
write_SSCR0(0, drv_data->ioaddr);
pxa_set_cken(drv_data->master_info->clock_enable, 0);
clk_disable(ssp->clk);
return 0;
}
@ -1596,10 +1562,11 @@ static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
static int pxa2xx_spi_resume(struct platform_device *pdev)
{
struct driver_data *drv_data = platform_get_drvdata(pdev);
struct ssp_device *ssp = drv_data->ssp;
int status = 0;
/* Enable the SSP clock */
pxa_set_cken(drv_data->master_info->clock_enable, 1);
clk_disable(ssp->clk);
/* Start the queue running */
status = start_queue(drv_data);

1
drivers/usb/Kconfig
View File

@ -33,6 +33,7 @@ config USB_ARCH_HAS_OHCI
default y if ARCH_LH7A404
default y if ARCH_S3C2410
default y if PXA27x
default y if PXA3xx
default y if ARCH_EP93XX
default y if ARCH_AT91
default y if ARCH_PNX4008

2
drivers/usb/host/ohci-hcd.c
View File

@ -997,7 +997,7 @@ MODULE_LICENSE ("GPL");
#define PLATFORM_DRIVER ohci_hcd_lh7a404_driver
#endif
#ifdef CONFIG_PXA27x
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
#include "ohci-pxa27x.c"
#define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
#endif

13
drivers/usb/host/ohci-pxa27x.c
View File

@ -22,6 +22,7 @@
#include <linux/device.h>
#include <linux/signal.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <asm/mach-types.h>
#include <asm/hardware.h>
@ -32,6 +33,8 @@
#define UHCRHPS(x) __REG2( 0x4C000050, (x)<<2 )
static struct clk *usb_clk;
/*
PMM_NPS_MODE -- PMM Non-power switching mode
Ports are powered continuously.
@ -80,7 +83,7 @@ static int pxa27x_start_hc(struct device *dev)
inf = dev->platform_data;
pxa_set_cken(CKEN_USBHOST, 1);
clk_enable(usb_clk);
UHCHR |= UHCHR_FHR;
udelay(11);
@ -123,7 +126,7 @@ static void pxa27x_stop_hc(struct device *dev)
UHCCOMS |= 1;
udelay(10);
pxa_set_cken(CKEN_USBHOST, 0);
clk_disable(usb_clk);
}
@ -158,6 +161,10 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device
return -ENOMEM;
}
usb_clk = clk_get(&pdev->dev, "USBCLK");
if (IS_ERR(usb_clk))
return PTR_ERR(usb_clk);
hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
if (!hcd)
return -ENOMEM;
@ -201,6 +208,7 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
err1:
usb_put_hcd(hcd);
clk_put(usb_clk);
return retval;
}
@ -225,6 +233,7 @@ void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev)
iounmap(hcd->regs);
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
usb_put_hcd(hcd);
clk_put(usb_clk);
}
/*-------------------------------------------------------------------------*/

19
include/asm-arm/arch-pxa/colibri.h Normal file
View File

@ -0,0 +1,19 @@
#ifndef _COLIBRI_H_
#define _COLIBRI_H_
/* physical memory regions */
#define COLIBRI_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */
#define COLIBRI_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */
#define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */
/* virtual memory regions */
#define COLIBRI_DISK_VIRT 0xF0000000 /* Disk On Chip region */
/* size of flash */
#define COLIBRI_FLASH_SIZE 0x02000000 /* Flash size 32 MB */
/* Ethernet Controller Davicom DM9000 */
#define GPIO_DM9000 114
#define COLIBRI_ETH_IRQ IRQ_GPIO(GPIO_DM9000)
#endif /* _COLIBRI_H_ */

1
include/asm-arm/arch-pxa/corgi.h
View File

@ -104,7 +104,6 @@
*/
extern struct platform_device corgiscoop_device;
extern struct platform_device corgissp_device;
extern struct platform_device corgifb_device;
#endif /* __ASM_ARCH_CORGI_H */

10
include/asm-arm/arch-pxa/irqs.h
View File

@ -180,7 +180,8 @@
#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
#elif defined(CONFIG_ARCH_LUBBOCK) || \
defined(CONFIG_MACH_LOGICPD_PXA270) || \
defined(CONFIG_MACH_MAINSTONE)
defined(CONFIG_MACH_MAINSTONE) || \
defined(CONFIG_MACH_PCM027)
#define NR_IRQS (IRQ_BOARD_END)
#else
#define NR_IRQS (IRQ_BOARD_START)
@ -227,6 +228,13 @@
#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2)
#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3)
/* phyCORE-PXA270 (PCM027) Interrupts */
#define PCM027_IRQ(x) (IRQ_BOARD_START + (x))
#define PCM027_BTDET_IRQ PCM027_IRQ(0)
#define PCM027_FF_RI_IRQ PCM027_IRQ(1)
#define PCM027_MMCDET_IRQ PCM027_IRQ(2)
#define PCM027_PM_5V_IRQ PCM027_IRQ(3)
/* ITE8152 irqs */
/* add IT8152 IRQs beyond BOARD_END */
#ifdef CONFIG_PCI_HOST_ITE8152

6
include/asm-arm/arch-pxa/littleton.h Normal file
View File

@ -0,0 +1,6 @@
#ifndef __ASM_ARCH_ZYLONITE_H
#define __ASM_ARCH_ZYLONITE_H
#define LITTLETON_ETH_PHYS 0x30000000
#endif /* __ASM_ARCH_ZYLONITE_H */

111
include/asm-arm/arch-pxa/magician.h Normal file
View File

@ -0,0 +1,111 @@
/*
* GPIO and IRQ definitions for HTC Magician PDA phones
*
* Copyright (c) 2007 Philipp Zabel
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _MAGICIAN_H_
#define _MAGICIAN_H_
#include <asm/arch/pxa-regs.h>
/*
* PXA GPIOs
*/
#define GPIO0_MAGICIAN_KEY_POWER 0
#define GPIO9_MAGICIAN_UNKNOWN 9
#define GPIO10_MAGICIAN_GSM_IRQ 10
#define GPIO11_MAGICIAN_GSM_OUT1 11
#define GPIO13_MAGICIAN_CPLD_IRQ 13
#define GPIO18_MAGICIAN_UNKNOWN 18
#define GPIO22_MAGICIAN_VIBRA_EN 22
#define GPIO26_MAGICIAN_GSM_POWER 26
#define GPIO27_MAGICIAN_USBC_PUEN 27
#define GPIO30_MAGICIAN_nCHARGE_EN 30
#define GPIO37_MAGICIAN_KEY_HANGUP 37
#define GPIO38_MAGICIAN_KEY_CONTACTS 38
#define GPIO40_MAGICIAN_GSM_OUT2 40
#define GPIO48_MAGICIAN_UNKNOWN 48
#define GPIO56_MAGICIAN_UNKNOWN 56
#define GPIO57_MAGICIAN_CAM_RESET 57
#define GPIO83_MAGICIAN_nIR_EN 83
#define GPIO86_MAGICIAN_GSM_RESET 86
#define GPIO87_MAGICIAN_GSM_SELECT 87
#define GPIO90_MAGICIAN_KEY_CALENDAR 90
#define GPIO91_MAGICIAN_KEY_CAMERA 91
#define GPIO93_MAGICIAN_KEY_UP 93
#define GPIO94_MAGICIAN_KEY_DOWN 94
#define GPIO95_MAGICIAN_KEY_LEFT 95
#define GPIO96_MAGICIAN_KEY_RIGHT 96
#define GPIO97_MAGICIAN_KEY_ENTER 97
#define GPIO98_MAGICIAN_KEY_RECORD 98
#define GPIO99_MAGICIAN_HEADPHONE_IN 99
#define GPIO100_MAGICIAN_KEY_VOL_UP 100
#define GPIO101_MAGICIAN_KEY_VOL_DOWN 101
#define GPIO102_MAGICIAN_KEY_PHONE 102
#define GPIO103_MAGICIAN_LED_KP 103
#define GPIO104_MAGICIAN_LCD_POWER_1 104
#define GPIO105_MAGICIAN_LCD_POWER_2 105
#define GPIO106_MAGICIAN_LCD_POWER_3 106
#define GPIO107_MAGICIAN_DS1WM_IRQ 107
#define GPIO108_MAGICIAN_GSM_READY 108
#define GPIO114_MAGICIAN_UNKNOWN 114
#define GPIO115_MAGICIAN_nPEN_IRQ 115
#define GPIO116_MAGICIAN_nCAM_EN 116
#define GPIO119_MAGICIAN_UNKNOWN 119
#define GPIO120_MAGICIAN_UNKNOWN 120
/*
* PXA GPIO alternate function mode & direction
*/
#define GPIO0_MAGICIAN_KEY_POWER_MD (0 | GPIO_IN)
#define GPIO9_MAGICIAN_UNKNOWN_MD (9 | GPIO_IN)
#define GPIO10_MAGICIAN_GSM_IRQ_MD (10 | GPIO_IN)
#define GPIO11_MAGICIAN_GSM_OUT1_MD (11 | GPIO_OUT)
#define GPIO13_MAGICIAN_CPLD_IRQ_MD (13 | GPIO_IN)
#define GPIO18_MAGICIAN_UNKNOWN_MD (18 | GPIO_OUT)
#define GPIO22_MAGICIAN_VIBRA_EN_MD (22 | GPIO_OUT)
#define GPIO26_MAGICIAN_GSM_POWER_MD (26 | GPIO_OUT)
#define GPIO27_MAGICIAN_USBC_PUEN_MD (27 | GPIO_OUT)
#define GPIO30_MAGICIAN_nCHARGE_EN_MD (30 | GPIO_OUT)
#define GPIO37_MAGICIAN_KEY_HANGUP_MD (37 | GPIO_OUT)
#define GPIO38_MAGICIAN_KEY_CONTACTS_MD (38 | GPIO_OUT)
#define GPIO40_MAGICIAN_GSM_OUT2_MD (40 | GPIO_OUT)
#define GPIO48_MAGICIAN_UNKNOWN_MD (48 | GPIO_OUT)
#define GPIO56_MAGICIAN_UNKNOWN_MD (56 | GPIO_OUT)
#define GPIO57_MAGICIAN_CAM_RESET_MD (57 | GPIO_OUT)
#define GPIO83_MAGICIAN_nIR_EN_MD (83 | GPIO_OUT)
#define GPIO86_MAGICIAN_GSM_RESET_MD (86 | GPIO_OUT)
#define GPIO87_MAGICIAN_GSM_SELECT_MD (87 | GPIO_OUT)
#define GPIO90_MAGICIAN_KEY_CALENDAR_MD (90 | GPIO_OUT)
#define GPIO91_MAGICIAN_KEY_CAMERA_MD (91 | GPIO_OUT)
#define GPIO93_MAGICIAN_KEY_UP_MD (93 | GPIO_IN)
#define GPIO94_MAGICIAN_KEY_DOWN_MD (94 | GPIO_IN)
#define GPIO95_MAGICIAN_KEY_LEFT_MD (95 | GPIO_IN)
#define GPIO96_MAGICIAN_KEY_RIGHT_MD (96 | GPIO_IN)
#define GPIO97_MAGICIAN_KEY_ENTER_MD (97 | GPIO_IN)
#define GPIO98_MAGICIAN_KEY_RECORD_MD (98 | GPIO_IN)
#define GPIO99_MAGICIAN_HEADPHONE_IN_MD (99 | GPIO_IN)
#define GPIO100_MAGICIAN_KEY_VOL_UP_MD (100 | GPIO_IN)
#define GPIO101_MAGICIAN_KEY_VOL_DOWN_MD (101 | GPIO_IN)
#define GPIO102_MAGICIAN_KEY_PHONE_MD (102 | GPIO_IN)
#define GPIO103_MAGICIAN_LED_KP_MD (103 | GPIO_OUT)
#define GPIO104_MAGICIAN_LCD_POWER_1_MD (104 | GPIO_OUT)
#define GPIO105_MAGICIAN_LCD_POWER_2_MD (105 | GPIO_OUT)
#define GPIO106_MAGICIAN_LCD_POWER_3_MD (106 | GPIO_OUT)
#define GPIO107_MAGICIAN_DS1WM_IRQ_MD (107 | GPIO_IN)
#define GPIO108_MAGICIAN_GSM_READY_MD (108 | GPIO_IN)
#define GPIO114_MAGICIAN_UNKNOWN_MD (114 | GPIO_OUT)
#define GPIO115_MAGICIAN_nPEN_IRQ_MD (115 | GPIO_IN)
#define GPIO116_MAGICIAN_nCAM_EN_MD (116 | GPIO_OUT)
#define GPIO119_MAGICIAN_UNKNOWN_MD (119 | GPIO_OUT)
#define GPIO120_MAGICIAN_UNKNOWN_MD (120 | GPIO_OUT)
#endif /* _MAGICIAN_H_ */

1
include/asm-arm/arch-pxa/mfp-pxa300.h
View File

@ -16,6 +16,7 @@
#define __ASM_ARCH_MFP_PXA300_H
#include <asm/arch/mfp.h>
#include <asm/arch/mfp-pxa3xx.h>
/* GPIO */
#define GPIO46_GPIO MFP_CFG(GPIO46, AF1)

1
include/asm-arm/arch-pxa/mfp-pxa320.h
View File

@ -16,6 +16,7 @@
#define __ASM_ARCH_MFP_PXA320_H
#include <asm/arch/mfp.h>
#include <asm/arch/mfp-pxa3xx.h>
/* GPIO */
#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)

252
include/asm-arm/arch-pxa/mfp-pxa3xx.h Normal file
View File

@ -0,0 +1,252 @@
#ifndef __ASM_ARCH_MFP_PXA3XX_H
#define __ASM_ARCH_MFP_PXA3XX_H
#define MFPR_BASE (0x40e10000)
#define MFPR_SIZE (PAGE_SIZE)
/* MFPR register bit definitions */
#define MFPR_PULL_SEL (0x1 << 15)
#define MFPR_PULLUP_EN (0x1 << 14)
#define MFPR_PULLDOWN_EN (0x1 << 13)
#define MFPR_SLEEP_SEL (0x1 << 9)
#define MFPR_SLEEP_OE_N (0x1 << 7)
#define MFPR_EDGE_CLEAR (0x1 << 6)
#define MFPR_EDGE_FALL_EN (0x1 << 5)
#define MFPR_EDGE_RISE_EN (0x1 << 4)
#define MFPR_SLEEP_DATA(x) ((x) << 8)
#define MFPR_DRIVE(x) (((x) & 0x7) << 10)
#define MFPR_AF_SEL(x) (((x) & 0x7) << 0)
#define MFPR_EDGE_NONE (0)
#define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN)
#define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN)
#define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL)
/*
* Table that determines the low power modes outputs, with actual settings
* used in parentheses for don't-care values. Except for the float output,
* the configured driven and pulled levels match, so if there is a need for
* non-LPM pulled output, the same configuration could probably be used.
*
* Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
* (bit 7) (bit 8) (bit 14) (bit 13) (bit 15)
*
* Input 0 X(0) X(0) X(0) 0
* Drive 0 0 0 0 X(1) 0
* Drive 1 0 1 X(1) 0 0
* Pull hi (1) 1 X(1) 1 0 0
* Pull lo (0) 1 X(0) 0 1 0
* Z (float) 1 X(0) 0 0 0
*/
#define MFPR_LPM_INPUT (0)
#define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN)
#define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN)
#define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N)
#define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N)
#define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N)
#define MFPR_LPM_MASK (0xe080)
/*
* The pullup and pulldown state of the MFP pin at run mode is by default
* determined by the selected alternate function. In case that some buggy
* devices need to override this default behavior, the definitions below
* indicates the setting of corresponding MFPR bits
*
* Definition pull_sel pullup_en pulldown_en
* MFPR_PULL_NONE 0 0 0
* MFPR_PULL_LOW 1 0 1
* MFPR_PULL_HIGH 1 1 0
* MFPR_PULL_BOTH 1 1 1
*/
#define MFPR_PULL_NONE (0)
#define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN)
#define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN)
#define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN)
/* PXA3xx common MFP configurations - processor specific ones defined
* in mfp-pxa300.h and mfp-pxa320.h
*/
#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0)
#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0)
#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0)
#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0)
#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0)
#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0)
#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0)
/*
* each MFP pin will have a MFPR register, since the offset of the
* register varies between processors, the processor specific code
* should initialize the pin offsets by pxa3xx_mfp_init_addr()
*
* pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
* structure, which represents a range of MFP pins from "start" to
* "end", with the offset begining at "offset", to define a single
* pin, let "end" = -1
*
* use
*
* MFP_ADDR_X() to define a range of pins
* MFP_ADDR() to define a single pin
* MFP_ADDR_END to signal the end of pin offset definitions
*/
struct pxa3xx_mfp_addr_map {
unsigned int start;
unsigned int end;
unsigned long offset;
};
#define MFP_ADDR_X(start, end, offset) \
{ MFP_PIN_##start, MFP_PIN_##end, offset }
#define MFP_ADDR(pin, offset) \
{ MFP_PIN_##pin, -1, offset }
#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
/*
* pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
* to the MFPR register
*/
unsigned long pxa3xx_mfp_read(int mfp);
void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
/*
* pxa3xx_mfp_config - configure the MFPR registers
*
* used by board specific initialization code
*/
void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num);
/*
* pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
* index and MFPR register offset
*
* used by processor specific code
*/
void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
void __init pxa3xx_init_mfp(void);
#endif /* __ASM_ARCH_MFP_PXA3XX_H */

405
include/asm-arm/arch-pxa/mfp.h
View File

@ -16,9 +16,6 @@
#ifndef __ASM_ARCH_MFP_H
#define __ASM_ARCH_MFP_H
#define MFPR_BASE (0x40e10000)
#define MFPR_SIZE (PAGE_SIZE)
#define mfp_to_gpio(m) ((m) % 128)
/* list of all the configurable MFP pins */
@ -216,115 +213,22 @@ enum {
MFP_PIN_MAX,
};
/*
* Table that determines the low power modes outputs, with actual settings
* used in parentheses for don't-care values. Except for the float output,
* the configured driven and pulled levels match, so if there is a need for
* non-LPM pulled output, the same configuration could probably be used.
*
* Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
* (bit 7) (bit 8) (bit 14d) (bit 13d)
*
* Drive 0 0 0 0 X (1) 0
* Drive 1 0 1 X (1) 0 0
* Pull hi (1) 1 X(1) 1 0 0
* Pull lo (0) 1 X(0) 0 1 0
* Z (float) 1 X(0) 0 0 0
*/
#define MFP_LPM_DRIVE_LOW 0x8
#define MFP_LPM_DRIVE_HIGH 0x6
#define MFP_LPM_PULL_HIGH 0x7
#define MFP_LPM_PULL_LOW 0x9
#define MFP_LPM_FLOAT 0x1
#define MFP_LPM_PULL_NEITHER 0x0
/*
* The pullup and pulldown state of the MFP pin is by default determined by
* selected alternate function. In case some buggy devices need to override
* this default behavior, pxa3xx_mfp_set_pull() can be invoked with one of
* the following definition as the parameter.
*
* Definition pull_sel pullup_en pulldown_en
* MFP_PULL_HIGH 1 1 0
* MFP_PULL_LOW 1 0 1
* MFP_PULL_BOTH 1 1 1
* MFP_PULL_NONE 1 0 0
* MFP_PULL_DEFAULT 0 X X
*
* NOTE: pxa3xx_mfp_set_pull() will modify the PULLUP_EN and PULLDOWN_EN
* bits, which will cause potential conflicts with the low power mode
* setting, device drivers should take care of this
*/
#define MFP_PULL_BOTH (0x7u)
#define MFP_PULL_HIGH (0x6u)
#define MFP_PULL_LOW (0x5u)
#define MFP_PULL_NONE (0x4u)
#define MFP_PULL_DEFAULT (0x0u)
#define MFP_AF0 (0)
#define MFP_AF1 (1)
#define MFP_AF2 (2)
#define MFP_AF3 (3)
#define MFP_AF4 (4)
#define MFP_AF5 (5)
#define MFP_AF6 (6)
#define MFP_AF7 (7)
#define MFP_DS01X (0)
#define MFP_DS02X (1)
#define MFP_DS03X (2)
#define MFP_DS04X (3)
#define MFP_DS06X (4)
#define MFP_DS08X (5)
#define MFP_DS10X (6)
#define MFP_DS12X (7)
#define MFP_EDGE_BOTH 0x3
#define MFP_EDGE_RISE 0x2
#define MFP_EDGE_FALL 0x1
#define MFP_EDGE_NONE 0x0
#define MFPR_AF_MASK 0x0007
#define MFPR_DRV_MASK 0x1c00
#define MFPR_RDH_MASK 0x0200
#define MFPR_LPM_MASK 0xe180
#define MFPR_PULL_MASK 0xe000
#define MFPR_EDGE_MASK 0x0070
#define MFPR_ALT_OFFSET 0
#define MFPR_ERE_OFFSET 4
#define MFPR_EFE_OFFSET 5
#define MFPR_EC_OFFSET 6
#define MFPR_SON_OFFSET 7
#define MFPR_SD_OFFSET 8
#define MFPR_SS_OFFSET 9
#define MFPR_DRV_OFFSET 10
#define MFPR_PD_OFFSET 13
#define MFPR_PU_OFFSET 14
#define MFPR_PS_OFFSET 15
#define MFPR(af, drv, rdh, lpm, edge) \
(((af) & 0x7) | (((drv) & 0x7) << 10) |\
(((rdh) & 0x1) << 9) |\
(((lpm) & 0x3) << 7) |\
(((lpm) & 0x4) << 12)|\
(((lpm) & 0x8) << 10)|\
((!(edge)) << 6) |\
(((edge) & 0x1) << 5) |\
(((edge) & 0x2) << 3))
/*
* a possible MFP configuration is represented by a 32-bit integer
* bit 0..15 - MFPR value (16-bit)
* bit 16..31 - mfp pin index (used to obtain the MFPR offset)
*
* bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
* bit 10..12 - Alternate Function Selection
* bit 13..15 - Drive Strength
* bit 16..18 - Low Power Mode State
* bit 19..20 - Low Power Mode Edge Detection
* bit 21..22 - Run Mode Pull State
*
* to facilitate the definition, the following macros are provided
*
* MFPR_DEFAULT - default MFPR value, with
* MFP_CFG_DEFAULT - default MFP configuration value, with
* alternate function = 0,
* drive strength = fast 1mA (MFP_DS01X)
* drive strength = fast 3mA (MFP_DS03X)
* low power mode = default
* release dalay hold = false (RDH bit)
* edge detection = none
*
* MFP_CFG - default MFPR value with alternate function
@ -334,251 +238,74 @@ enum {
* low power mode
* MFP_CFG_X - default MFPR value with alternate function,
* pin drive strength and low power mode
*
* use
*
* MFP_CFG_PIN - to get the MFP pin index
* MFP_CFG_VAL - to get the corresponding MFPR value
*/
typedef uint32_t mfp_cfg_t;
typedef unsigned long mfp_cfg_t;
#define MFP_CFG_PIN(mfp_cfg) (((mfp_cfg) >> 16) & 0xffff)
#define MFP_CFG_VAL(mfp_cfg) ((mfp_cfg) & 0xffff)
#define MFP_PIN(x) ((x) & 0x3ff)
/*
* MFP register defaults to
* drive strength fast 3mA (010'b)
* edge detection logic disabled
* alternate function 0
*/
#define MFPR_DEFAULT (0x0840)
#define MFP_AF0 (0x0 << 10)
#define MFP_AF1 (0x1 << 10)
#define MFP_AF2 (0x2 << 10)
#define MFP_AF3 (0x3 << 10)
#define MFP_AF4 (0x4 << 10)
#define MFP_AF5 (0x5 << 10)
#define MFP_AF6 (0x6 << 10)
#define MFP_AF7 (0x7 << 10)
#define MFP_AF_MASK (0x7 << 10)
#define MFP_AF(x) (((x) >> 10) & 0x7)
#define MFP_DS01X (0x0 << 13)
#define MFP_DS02X (0x1 << 13)
#define MFP_DS03X (0x2 << 13)
#define MFP_DS04X (0x3 << 13)
#define MFP_DS06X (0x4 << 13)
#define MFP_DS08X (0x5 << 13)
#define MFP_DS10X (0x6 << 13)
#define MFP_DS13X (0x7 << 13)
#define MFP_DS_MASK (0x7 << 13)
#define MFP_DS(x) (((x) >> 13) & 0x7)
#define MFP_LPM_INPUT (0x0 << 16)
#define MFP_LPM_DRIVE_LOW (0x1 << 16)
#define MFP_LPM_DRIVE_HIGH (0x2 << 16)
#define MFP_LPM_PULL_LOW (0x3 << 16)
#define MFP_LPM_PULL_HIGH (0x4 << 16)
#define MFP_LPM_FLOAT (0x5 << 16)
#define MFP_LPM_STATE_MASK (0x7 << 16)
#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7)
#define MFP_LPM_EDGE_NONE (0x0 << 19)
#define MFP_LPM_EDGE_RISE (0x1 << 19)
#define MFP_LPM_EDGE_FALL (0x2 << 19)
#define MFP_LPM_EDGE_BOTH (0x3 << 19)
#define MFP_LPM_EDGE_MASK (0x3 << 19)
#define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3)
#define MFP_PULL_NONE (0x0 << 21)
#define MFP_PULL_LOW (0x1 << 21)
#define MFP_PULL_HIGH (0x2 << 21)
#define MFP_PULL_BOTH (0x3 << 21)
#define MFP_PULL_MASK (0x3 << 21)
#define MFP_PULL(x) (((x) >> 21) & 0x3)
#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_INPUT |\
MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
#define MFP_CFG(pin, af) \
((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af))
((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\
(MFP_PIN(MFP_PIN_##pin) | MFP_##af))
#define MFP_CFG_DRV(pin, af, drv) \
((MFP_PIN_##pin << 16) | (MFPR_DEFAULT & ~MFPR_DRV_MASK) |\
((MFP_##drv) << 10) | (MFP_##af))
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\
(MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
#define MFP_CFG_LPM(pin, af, lpm) \
((MFP_PIN_##pin << 16) | (MFPR_DEFAULT & ~MFPR_LPM_MASK) |\
(((MFP_LPM_##lpm) & 0x3) << 7) |\
(((MFP_LPM_##lpm) & 0x4) << 12) |\
(((MFP_LPM_##lpm) & 0x8) << 10) |\
(MFP_##af))
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\
(MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
#define MFP_CFG_X(pin, af, drv, lpm) \
((MFP_PIN_##pin << 16) |\
(MFPR_DEFAULT & ~(MFPR_DRV_MASK | MFPR_LPM_MASK)) |\
((MFP_##drv) << 10) | (MFP_##af) |\
(((MFP_LPM_##lpm) & 0x3) << 7) |\
(((MFP_LPM_##lpm) & 0x4) << 12) |\
(((MFP_LPM_##lpm) & 0x8) << 10))
/* common MFP configurations - processor specific ones defined
* in mfp-pxa3xx.h
*/
#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0)
#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0)
#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0)
#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0)
#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0)
#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0)
#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0)
/*
* each MFP pin will have a MFPR register, since the offset of the
* register varies between processors, the processor specific code
* should initialize the pin offsets by pxa3xx_mfp_init_addr()
*
* pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
* structure, which represents a range of MFP pins from "start" to
* "end", with the offset begining at "offset", to define a single
* pin, let "end" = -1
*
* use
*
* MFP_ADDR_X() to define a range of pins
* MFP_ADDR() to define a single pin
* MFP_ADDR_END to signal the end of pin offset definitions
*/
struct pxa3xx_mfp_addr_map {
unsigned int start;
unsigned int end;
unsigned long offset;
};
#define MFP_ADDR_X(start, end, offset) \
{ MFP_PIN_##start, MFP_PIN_##end, offset }
#define MFP_ADDR(pin, offset) \
{ MFP_PIN_##pin, -1, offset }
#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
struct pxa3xx_mfp_pin {
unsigned long mfpr_off; /* MFPRxx register offset */
unsigned long mfpr_val; /* MFPRxx register value */
};
/*
* pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
* to the MFPR register
*/
unsigned long pxa3xx_mfp_read(int mfp);
void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
/*
* pxa3xx_mfp_set_afds - set MFP alternate function and drive strength
* pxa3xx_mfp_set_rdh - set MFP release delay hold on/off
* pxa3xx_mfp_set_lpm - set MFP low power mode state
* pxa3xx_mfp_set_edge - set MFP edge detection in low power mode
*
* use these functions to override/change the default configuration
* done by pxa3xx_mfp_set_config(s)
*/
void pxa3xx_mfp_set_afds(int mfp, int af, int ds);
void pxa3xx_mfp_set_rdh(int mfp, int rdh);
void pxa3xx_mfp_set_lpm(int mfp, int lpm);
void pxa3xx_mfp_set_edge(int mfp, int edge);
/*
* pxa3xx_mfp_config - configure the MFPR registers
*
* used by board specific initialization code
*/
void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num);
/*
* pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
* index and MFPR register offset
*
* used by processor specific code
*/
void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
void __init pxa3xx_init_mfp(void);
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
(MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
#endif /* __ASM_ARCH_MFP_H */

2
include/asm-arm/arch-pxa/mmc.h
View File

@ -17,5 +17,7 @@ struct pxamci_platform_data {
};
extern void pxa_set_mci_info(struct pxamci_platform_data *info);
extern void pxa3xx_set_mci2_info(struct pxamci_platform_data *info);
extern void pxa3xx_set_mci3_info(struct pxamci_platform_data *info);
#endif

75
include/asm-arm/arch-pxa/pcm027.h Normal file
View File

@ -0,0 +1,75 @@
/*
* linux/include/asm-arm/arch-pxa/pcm027.h
*
* (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
* (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* Definitions of CPU card resources only
*/
/* I2C RTC */
#define PCM027_RTC_IRQ_GPIO 0
#define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO)
#define PCM027_RTC_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
#define ADR_PCM027_RTC 0x51 /* I2C address */
/* I2C EEPROM */
#define ADR_PCM027_EEPROM 0x54 /* I2C address */
/* Ethernet chip (SMSC91C111) */
#define PCM027_ETH_IRQ_GPIO 52
#define PCM027_ETH_IRQ IRQ_GPIO(PCM027_ETH_IRQ_GPIO)
#define PCM027_ETH_IRQ_EDGE IRQ_TYPE_EDGE_RISING
#define PCM027_ETH_PHYS PXA_CS5_PHYS
#define PCM027_ETH_SIZE (1*1024*1024)
/* CAN controller SJA1000 (unsupported yet) */
#define PCM027_CAN_IRQ_GPIO 114
#define PCM027_CAN_IRQ IRQ_GPIO(PCM027_CAN_IRQ_GPIO)
#define PCM027_CAN_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
#define PCM027_CAN_PHYS 0x22000000
#define PCM027_CAN_SIZE 0x100
/* SPI GPIO expander (unsupported yet) */
#define PCM027_EGPIO_IRQ_GPIO 27
#define PCM027_EGPIO_IRQ IRQ_GPIO(PCM027_EGPIO_IRQ_GPIO)
#define PCM027_EGPIO_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
#define PCM027_EGPIO_CS 24
/*
* TODO: Switch this pin from dedicated usage to GPIO if
* more than the MAX7301 device is connected to this SPI bus
*/
#define PCM027_EGPIO_CS_MODE GPIO24_SFRM_MD
/* Flash memory */
#define PCM027_FLASH_PHYS 0x00000000
#define PCM027_FLASH_SIZE 0x02000000
/* onboard LEDs connected to GPIO */
#define PCM027_LED_CPU 90
#define PCM027_LED_HEARD_BEAT 91
/*
* This CPU module needs a baseboard to work. After basic initializing
* its own devices, it calls baseboard's init function.
* TODO: Add your own basebaord init function and call it from
* inside pcm027_init(). This example here is for the developmen board.
* Refer pcm990-baseboard.c
*/
extern void pcm990_baseboard_init(void);

275
include/asm-arm/arch-pxa/pcm990_baseboard.h Normal file
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@ -0,0 +1,275 @@
/*
* include/asm-arm/arch-pxa/pcm990_baseboard.h
*
* (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
* (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <asm/arch/pcm027.h>
/*
* definitions relevant only when the PCM-990
* development base board is in use
*/
/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
#define PCM990_CTRL_INT_IRQ_GPIO 9
#define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO)
#define PCM990_CTRL_INT_IRQ_EDGE IRQT_RISING
#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */
#define PCM990_CTRL_BASE 0xea000000
#define PCM990_CTRL_SIZE (1*1024*1024)
#define PCM990_CTRL_PWR_IRQ_GPIO 14
#define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO)
#define PCM990_CTRL_PWR_IRQ_EDGE IRQT_RISING
/* visible CPLD (U7) registers */
#define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */
#define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */
#define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */
#define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */
#define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */
#define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */
#define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */
#define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */
#define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */
#define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */
#define PCM990_CTRL_LEDBAS 0x0002 /* BASIS LED enable */
#define PCM990_CTRL_LEDUSR 0x0004 /* USER LED enable */
#define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */
#define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */
#define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */
#define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */
#define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */
#define PCM990_CTRL_REG4 0x0008 /* MMC1 CTRL REGISTER 4 */
#define PCM990_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */
#define PCM990_CTRL_REG5 0x000A /* MMC2 CTRL REGISTER 5 */
#define PCM990_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */
#define PCM990_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */
#define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */
#define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */
#define PCM990_CTRL_REG6 0x000C /* Interrupt Clear REGISTER */
#define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */
#define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */
#define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */
#define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */
#define PCM990_CTRL_REG7 0x000E /* Interrupt Enable REGISTER */
#define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */
#define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */
#define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */
#define PCM990_CTRL_ENAINT3 0x0008 /* Enable Int PM_5V off */
#define PCM990_CTRL_REG8 0x0014 /* Uart REGISTER */
#define PCM990_CTRL_FFSD 0x0001 /* BT Uart Enable */
#define PCM990_CTRL_BTSD 0x0002 /* FF Uart Enable */
#define PCM990_CTRL_FFRI 0x0004 /* FF Uart RI detect */
#define PCM990_CTRL_BTRX 0x0008 /* BT Uart Rx detect */
#define PCM990_CTRL_REG9 0x0010 /* AC97 Flash REGISTER */
#define PCM990_CTRL_FLWP 0x0001 /* pC Flash Write Protect */
#define PCM990_CTRL_FLDIS 0x0002 /* pC Flash Disable */
#define PCM990_CTRL_AC97ENA 0x0004 /* Enable AC97 Expansion */
#define PCM990_CTRL_REG10 0x0012 /* GPS-REGISTER */
#define PCM990_CTRL_GPSPWR 0x0004 /* GPS-Modul Power on */
#define PCM990_CTRL_GPSENA 0x0008 /* GPS-Modul Enable */
#define PCM990_CTRL_REG11 0x0014 /* Accu REGISTER */
#define PCM990_CTRL_ACENA 0x0001 /* Charge Enable */
#define PCM990_CTRL_ACSEL 0x0002 /* Charge Akku -> DC Enable */
#define PCM990_CTRL_ACPRES 0x0004 /* DC Present */
#define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */
#define PCM990_CTRL_P2V(x) ((x) - PCM990_CTRL_PHYS + PCM990_CTRL_BASE)
#define PCM990_CTRL_V2P(x) ((x) - PCM990_CTRL_BASE + PCM990_CTRL_PHYS)
#ifndef __ASSEMBLY__
# define __PCM990_CTRL_REG(x) \
(*((volatile unsigned char *)PCM990_CTRL_P2V(x)))
#else
# define __PCM990_CTRL_REG(x) PCM990_CTRL_P2V(x)
#endif
#define PCM990_INTMSKENA __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
#define PCM990_INTSETCLR __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
#define PCM990_CTRL0 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG0)
#define PCM990_CTRL1 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG1)
#define PCM990_CTRL2 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG2)
#define PCM990_CTRL3 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3)
#define PCM990_CTRL4 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG4)
#define PCM990_CTRL5 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5)
#define PCM990_CTRL6 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
#define PCM990_CTRL7 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
#define PCM990_CTRL8 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG8)
#define PCM990_CTRL9 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG9)
#define PCM990_CTRL10 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG10)
#define PCM990_CTRL11 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG11)
/*
* IDE
*/
#define PCM990_IDE_IRQ_GPIO 13
#define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO)
#define PCM990_IDE_IRQ_EDGE IRQT_RISING
#define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */
#define PCM990_IDE_PLD_BASE 0xee000000
#define PCM990_IDE_PLD_SIZE (1*1024*1024)
/* visible CPLD (U6) registers */
#define PCM990_IDE_PLD_REG0 0x1000 /* OFFSET IDE REGISTER 0 */
#define PCM990_IDE_PM5V 0x0004 /* R System VCC_5V */
#define PCM990_IDE_STBY 0x0008 /* R System StandBy */
#define PCM990_IDE_PLD_REG1 0x1002 /* OFFSET IDE REGISTER 1 */
#define PCM990_IDE_IDEMODE 0x0001 /* R TrueIDE Mode */
#define PCM990_IDE_DMAENA 0x0004 /* RW DMA Enable */
#define PCM990_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */
#define PCM990_IDE_PLD_REG2 0x1004 /* OFFSET IDE REGISTER 2 */
#define PCM990_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */
#define PCM990_IDE_RES 0x0002 /* RW IDE Reset Bit */
#define PCM990_IDE_RDY 0x0008 /* RDY */
#define PCM990_IDE_PLD_REG3 0x1006 /* OFFSET IDE REGISTER 3 */
#define PCM990_IDE_IDEOE 0x0001 /* RW Latch on Databus */
#define PCM990_IDE_IDEON 0x0002 /* RW Latch on Control Address */
#define PCM990_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */
#define PCM990_IDE_PLD_REG4 0x1008 /* OFFSET IDE REGISTER 4 */
#define PCM990_IDE_PWRENA 0x0001 /* RW IDE Power enable */
#define PCM990_IDE_5V 0x0002 /* R IDE Power 5V */
#define PCM990_IDE_PWG 0x0008 /* R IDE Power is on */
#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE)
#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS)
#ifndef __ASSEMBLY__
# define __PCM990_IDE_PLD_REG(x) \
(*((volatile unsigned char *)PCM990_IDE_PLD_P2V(x)))
#else
# define __PCM990_IDE_PLD_REG(x) PCM990_IDE_PLD_P2V(x)
#endif
#define PCM990_IDE0 \
__PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG0)
#define PCM990_IDE1 \
__PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG1)
#define PCM990_IDE2 \
__PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG2)
#define PCM990_IDE3 \
__PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG3)
#define PCM990_IDE4 \
__PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG4)
/*
* Compact Flash
*/
#define PCM990_CF_IRQ_GPIO 11
#define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO)
#define PCM990_CF_IRQ_EDGE IRQT_RISING
#define PCM990_CF_CD_GPIO 12
#define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO)
#define PCM990_CF_CD_EDGE IRQT_RISING
#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */
#define PCM990_CF_PLD_BASE 0xef000000
#define PCM990_CF_PLD_SIZE (1*1024*1024)
#define PCM990_CF_PLD_P2V(x) ((x) - PCM990_CF_PLD_PHYS + PCM990_CF_PLD_BASE)
#define PCM990_CF_PLD_V2P(x) ((x) - PCM990_CF_PLD_BASE + PCM990_CF_PLD_PHYS)
/* visible CPLD (U6) registers */
#define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */
#define PCM990_CF_REG0_LED 0x0001 /* RW LED on */
#define PCM990_CF_REG0_BLK 0x0002 /* RW LED flash when access */
#define PCM990_CF_REG0_PM5V 0x0004 /* R System VCC_5V enable */
#define PCM990_CF_REG0_STBY 0x0008 /* R System StandBy */
#define PCM990_CF_PLD_REG1 0x1002 /* OFFSET CF REGISTER 1 */
#define PCM990_CF_REG1_IDEMODE 0x0001 /* RW CF card run as TrueIDE */
#define PCM990_CF_REG1_CF0 0x0002 /* RW CF card at ADDR 0x28000000 */
#define PCM990_CF_PLD_REG2 0x1004 /* OFFSET CF REGISTER 2 */
#define PCM990_CF_REG2_RES 0x0002 /* RW CF RESET BIT */
#define PCM990_CF_REG2_RDYENA 0x0004 /* RW Enable CF_RDY */
#define PCM990_CF_REG2_RDY 0x0008 /* R CF_RDY auf PWAIT */
#define PCM990_CF_PLD_REG3 0x1006 /* OFFSET CF REGISTER 3 */
#define PCM990_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */
#define PCM990_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */
#define PCM990_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */
#define PCM990_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */
#define PCM990_CF_PLD_REG4 0x1008 /* OFFSET CF REGISTER 4 */
#define PCM990_CF_REG4_PWRENA 0x0001 /* RW CF Power on (CD1/2 = "00") */
#define PCM990_CF_REG4_5_3V 0x0002 /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */
#define PCM990_CF_REG4_3B 0x0004 /* RW 3.0V Backup from VCC (5_3V=0) */
#define PCM990_CF_REG4_PWG 0x0008 /* R CF-Power is on */
#define PCM990_CF_PLD_REG5 0x100A /* OFFSET CF REGISTER 5 */
#define PCM990_CF_REG5_BVD1 0x0001 /* R CF /BVD1 */
#define PCM990_CF_REG5_BVD2 0x0002 /* R CF /BVD2 */
#define PCM990_CF_REG5_VS1 0x0004 /* R CF /VS1 */
#define PCM990_CF_REG5_VS2 0x0008 /* R CF /VS2 */
#define PCM990_CF_PLD_REG6 0x100C /* OFFSET CF REGISTER 6 */
#define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */
#define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */
#ifndef __ASSEMBLY__
# define __PCM990_CF_PLD_REG(x) \
(*((volatile unsigned char *)PCM990_CF_PLD_P2V(x)))
#else
# define __PCM990_CF_PLD_REG(x) PCM990_CF_PLD_P2V(x)
#endif
#define PCM990_CF0 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG0)
#define PCM990_CF1 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG1)
#define PCM990_CF2 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG2)
#define PCM990_CF3 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG3)
#define PCM990_CF4 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG4)
#define PCM990_CF5 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG5)
#define PCM990_CF6 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG6)
/*
* Wolfson AC97 Touch
*/
#define PCM990_AC97_IRQ_GPIO 10
#define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO)
#define PCM990_AC97_IRQ_EDGE IRQT_RISING
/*
* MMC phyCORE
*/
#define PCM990_MMC0_IRQ_GPIO 9
#define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO)
#define PCM990_MMC0_IRQ_EDGE IRQT_FALLING
/*
* USB phyCore
*/
#define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN)
#define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT)

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@ -1597,176 +1597,10 @@
#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
/*
* SSP Serial Port Registers
* PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
* PXA255, PXA26x and PXA27x have extra ports, registers and bits.
* SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
*/
/* Common PXA2xx bits first */
#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
#define SSCR0_National (0x2 << 4) /* National Microwire */
#define SSCR0_ECS (1 << 6) /* External clock select */
#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
#if defined(CONFIG_PXA25x)
#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
#elif defined(CONFIG_PXA27x)
#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
#define SSCR0_EDSS (1 << 20) /* Extended data size select */
#define SSCR0_NCS (1 << 21) /* Network clock select */
#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
#define SSCR0_ADC (1 << 30) /* Audio clock select */
#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
#endif
#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
#define SSSR_BSY (1 << 4) /* SSP Busy */
#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
#define SSCR0_NCS (1 << 21) /* Network Clock Select */
#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
#define SSSR_BCE (1 << 23) /* Bit Count Error */
#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
#define SSSR_EOC (1 << 20) /* End Of Chain */
#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
#define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */
#define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */
#define SSSR_P1 __REG(0x41000008) /* SSP Port 1 Status Register */
#define SSITR_P1 __REG(0x4100000C) /* SSP Port 1 Interrupt Test Register */
#define SSDR_P1 __REG(0x41000010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */
/* Support existing PXA25x drivers */
#define SSCR0 SSCR0_P1 /* SSP Control Register 0 */
#define SSCR1 SSCR1_P1 /* SSP Control Register 1 */
#define SSSR SSSR_P1 /* SSP Status Register */
#define SSITR SSITR_P1 /* SSP Interrupt Test Register */
#define SSDR SSDR_P1 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
/* PXA27x ports */
#if defined (CONFIG_PXA27x)
#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
#define SSTSA_P1 __REG(0x41000030) /* SSP Port 1 Tx Timeslot Active */
#define SSRSA_P1 __REG(0x41000034) /* SSP Port 1 Rx Timeslot Active */
#define SSTSS_P1 __REG(0x41000038) /* SSP Port 1 Timeslot Status */
#define SSACD_P1 __REG(0x4100003C) /* SSP Port 1 Audio Clock Divider */
#define SSCR0_P2 __REG(0x41700000) /* SSP Port 2 Control Register 0 */
#define SSCR1_P2 __REG(0x41700004) /* SSP Port 2 Control Register 1 */
#define SSSR_P2 __REG(0x41700008) /* SSP Port 2 Status Register */
#define SSITR_P2 __REG(0x4170000C) /* SSP Port 2 Interrupt Test Register */
#define SSDR_P2 __REG(0x41700010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
#define SSTO_P2 __REG(0x41700028) /* SSP Port 2 Time Out Register */
#define SSPSP_P2 __REG(0x4170002C) /* SSP Port 2 Programmable Serial Protocol */
#define SSTSA_P2 __REG(0x41700030) /* SSP Port 2 Tx Timeslot Active */
#define SSRSA_P2 __REG(0x41700034) /* SSP Port 2 Rx Timeslot Active */
#define SSTSS_P2 __REG(0x41700038) /* SSP Port 2 Timeslot Status */
#define SSACD_P2 __REG(0x4170003C) /* SSP Port 2 Audio Clock Divider */
#define SSCR0_P3 __REG(0x41900000) /* SSP Port 3 Control Register 0 */
#define SSCR1_P3 __REG(0x41900004) /* SSP Port 3 Control Register 1 */
#define SSSR_P3 __REG(0x41900008) /* SSP Port 3 Status Register */
#define SSITR_P3 __REG(0x4190000C) /* SSP Port 3 Interrupt Test Register */
#define SSDR_P3 __REG(0x41900010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
#define SSTO_P3 __REG(0x41900028) /* SSP Port 3 Time Out Register */
#define SSPSP_P3 __REG(0x4190002C) /* SSP Port 3 Programmable Serial Protocol */
#define SSTSA_P3 __REG(0x41900030) /* SSP Port 3 Tx Timeslot Active */
#define SSRSA_P3 __REG(0x41900034) /* SSP Port 3 Rx Timeslot Active */
#define SSTSS_P3 __REG(0x41900038) /* SSP Port 3 Timeslot Status */
#define SSACD_P3 __REG(0x4190003C) /* SSP Port 3 Audio Clock Divider */
#else /* PXA255 (only port 2) and PXA26x ports*/
#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
#define SSCR0_P2 __REG(0x41400000) /* SSP Port 2 Control Register 0 */
#define SSCR1_P2 __REG(0x41400004) /* SSP Port 2 Control Register 1 */
#define SSSR_P2 __REG(0x41400008) /* SSP Port 2 Status Register */
#define SSITR_P2 __REG(0x4140000C) /* SSP Port 2 Interrupt Test Register */
#define SSDR_P2 __REG(0x41400010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
#define SSTO_P2 __REG(0x41400028) /* SSP Port 2 Time Out Register */
#define SSPSP_P2 __REG(0x4140002C) /* SSP Port 2 Programmable Serial Protocol */
#define SSCR0_P3 __REG(0x41500000) /* SSP Port 3 Control Register 0 */
#define SSCR1_P3 __REG(0x41500004) /* SSP Port 3 Control Register 1 */
#define SSSR_P3 __REG(0x41500008) /* SSP Port 3 Status Register */
#define SSITR_P3 __REG(0x4150000C) /* SSP Port 3 Interrupt Test Register */
#define SSDR_P3 __REG(0x41500010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
#define SSTO_P3 __REG(0x41500028) /* SSP Port 3 Time Out Register */
#define SSPSP_P3 __REG(0x4150002C) /* SSP Port 3 Programmable Serial Protocol */
#endif
#define SSCR0_P(x) (*(((x) == 1) ? &SSCR0_P1 : ((x) == 2) ? &SSCR0_P2 : ((x) == 3) ? &SSCR0_P3 : NULL))
#define SSCR1_P(x) (*(((x) == 1) ? &SSCR1_P1 : ((x) == 2) ? &SSCR1_P2 : ((x) == 3) ? &SSCR1_P3 : NULL))
#define SSSR_P(x) (*(((x) == 1) ? &SSSR_P1 : ((x) == 2) ? &SSSR_P2 : ((x) == 3) ? &SSSR_P3 : NULL))
#define SSITR_P(x) (*(((x) == 1) ? &SSITR_P1 : ((x) == 2) ? &SSITR_P2 : ((x) == 3) ? &SSITR_P3 : NULL))
#define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL))
#define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
#define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
#define SSTSA_P(x) (*(((x) == 1) ? &SSTSA_P1 : ((x) == 2) ? &SSTSA_P2 : ((x) == 3) ? &SSTSA_P3 : NULL))
#define SSRSA_P(x) (*(((x) == 1) ? &SSRSA_P1 : ((x) == 2) ? &SSRSA_P2 : ((x) == 3) ? &SSRSA_P3 : NULL))
#define SSTSS_P(x) (*(((x) == 1) ? &SSTSS_P1 : ((x) == 2) ? &SSTSS_P2 : ((x) == 3) ? &SSTSS_P3 : NULL))
#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
/*
* MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
*/
@ -2014,71 +1848,8 @@
#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
/*
* Memory controller
*/
#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
/*
* More handy macros for PCMCIA
*
* Arg is socket number
*/
#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
/* MECR register defines */
#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
#ifdef CONFIG_PXA27x
#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
/*
* Keypad
*/
@ -2135,74 +1906,6 @@
#define KPAS_SO (0x1 << 31)
#define KPASMKPx_SO (0x1 << 31)
/*
* UHC: USB Host Controller (OHCI-like) register definitions
*/
#define UHC_BASE_PHYS (0x4C000000)
#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
Interrupt Enable*/
#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
/* Camera Interface */
#define CICR0 __REG(0x50000000)
#define CICR1 __REG(0x50000004)
@ -2350,6 +2053,77 @@
#endif
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
/*
* UHC: USB Host Controller (OHCI-like) register definitions
*/
#define UHC_BASE_PHYS (0x4C000000)
#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
Interrupt Enable*/
#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
/* PWRMODE register M field values */
#define PWRMODE_IDLE 0x1

84
include/asm-arm/arch-pxa/pxa2xx-regs.h Normal file
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@ -0,0 +1,84 @@
/*
* linux/include/asm-arm/arch-pxa/pxa2xx-regs.h
*
* Taken from pxa-regs.h by Russell King
*
* Author: Nicolas Pitre
* Copyright: MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PXA2XX_REGS_H
#define __PXA2XX_REGS_H
/*
* Memory controller
*/
#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
/*
* More handy macros for PCMCIA
*
* Arg is socket number
*/
#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
/* MECR register defines */
#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
#ifdef CONFIG_PXA27x
#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
#endif
#endif

24
include/asm-arm/arch-pxa/pxa2xx_spi.h
View File

@ -22,32 +22,8 @@
#define PXA2XX_CS_ASSERT (0x01)
#define PXA2XX_CS_DEASSERT (0x02)
#if defined(CONFIG_PXA25x)
#define CLOCK_SPEED_HZ 3686400
#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/2/(x+1))<<8)&0x0000ff00)
#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#elif defined(CONFIG_PXA27x)
#define CLOCK_SPEED_HZ 13000000
#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#endif
#define SSP1_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(1)))))
#define SSP2_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(2)))))
#define SSP3_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(3)))))
enum pxa_ssp_type {
SSP_UNDEFINED = 0,
PXA25x_SSP, /* pxa 210, 250, 255, 26x */
PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
PXA27x_SSP,
};
/* device.platform_data for SSP controller devices */
struct pxa2xx_spi_master {
enum pxa_ssp_type ssp_type;
u32 clock_enable;
u16 num_chipselect;
u8 enable_dma;

86
include/asm-arm/arch-pxa/pxa3xx-regs.h
View File

@ -13,6 +13,92 @@
#ifndef __ASM_ARCH_PXA3XX_REGS_H
#define __ASM_ARCH_PXA3XX_REGS_H
/*
* Slave Power Managment Unit
*/
#define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */
#define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */
#define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */
#define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */
#define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */
#define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */
#define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */
#define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */
#define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */
#define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */
#define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */
#define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */
#define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */
#define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */
/*
* Application Subsystem Configuration bits.
*/
#define ASCR_RDH (1 << 31)
#define ASCR_D1S (1 << 2)
#define ASCR_D2S (1 << 1)
#define ASCR_D3S (1 << 0)
/*
* Application Reset Status bits.
*/
#define ARSR_GPR (1 << 3)
#define ARSR_LPMR (1 << 2)
#define ARSR_WDT (1 << 1)
#define ARSR_HWR (1 << 0)
/*
* Application Subsystem Wake-Up bits.
*/
#define ADXER_WRTC (1 << 31) /* RTC */
#define ADXER_WOST (1 << 30) /* OS Timer */
#define ADXER_WTSI (1 << 29) /* Touchscreen */
#define ADXER_WUSBH (1 << 28) /* USB host */
#define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */
#define ADXER_WMSL0 (1 << 24) /* MSL port 0*/
#define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */
#define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */
#define ADXER_WKP (1 << 21) /* Keypad */
#define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */
#define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */
#define ADXER_WOTG (1 << 16) /* USBOTG input */
#define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */
#define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */
#define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */
#define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */
#define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */
#define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */
#define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */
#define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */
#define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */
#define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */
#define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */
#define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */
#define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */
#define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */
#define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */
#define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */
/*
* AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320.
*/
#define ADXR_L2 (1 << 8)
#define ADXR_R5 (1 << 5)
#define ADXR_R4 (1 << 4)
#define ADXR_R3 (1 << 3)
#define ADXR_R2 (1 << 2)
#define ADXR_R1 (1 << 1)
#define ADXR_R0 (1 << 0)
/*
* Values for PWRMODE CP15 register
*/
#define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */
#define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */
#define PXA3xx_PM_S0D2C2 0x03 /* aka standby */
#define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */
#define PXA3xx_PM_S0D0C1 0x01
/*
* Application Subsystem Clock
*/

112
include/asm-arm/arch-pxa/regs-ssp.h Normal file
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@ -0,0 +1,112 @@
#ifndef __ASM_ARCH_REGS_SSP_H
#define __ASM_ARCH_REGS_SSP_H
/*
* SSP Serial Port Registers
* PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
* PXA255, PXA26x and PXA27x have extra ports, registers and bits.
*/
#define SSCR0 (0x00) /* SSP Control Register 0 */
#define SSCR1 (0x04) /* SSP Control Register 1 */
#define SSSR (0x08) /* SSP Status Register */
#define SSITR (0x0C) /* SSP Interrupt Test Register */
#define SSDR (0x10) /* SSP Data Write/Data Read Register */
#define SSTO (0x28) /* SSP Time Out Register */
#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
#define SSTSA (0x30) /* SSP Tx Timeslot Active */
#define SSRSA (0x34) /* SSP Rx Timeslot Active */
#define SSTSS (0x38) /* SSP Timeslot Status */
#define SSACD (0x3C) /* SSP Audio Clock Divider */
/* Common PXA2xx bits first */
#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
#define SSCR0_National (0x2 << 4) /* National Microwire */
#define SSCR0_ECS (1 << 6) /* External clock select */
#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
#if defined(CONFIG_PXA25x)
#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
#elif defined(CONFIG_PXA27x)
#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
#define SSCR0_EDSS (1 << 20) /* Extended data size select */
#define SSCR0_NCS (1 << 21) /* Network clock select */
#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
#define SSCR0_ADC (1 << 30) /* Audio clock select */
#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
#endif
#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
#define SSSR_BSY (1 << 4) /* SSP Busy */
#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
#define SSCR0_NCS (1 << 21) /* Network Clock Select */
#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
#define SSSR_BCE (1 << 23) /* Bit Count Error */
#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
#define SSSR_EOC (1 << 20) /* End Of Chain */
#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
#endif /* __ASM_ARCH_REGS_SSP_H */

2
include/asm-arm/arch-pxa/sharpsl.h
View File

@ -16,7 +16,7 @@ int corgi_ssp_max1111_get(unsigned long data);
*/
struct corgits_machinfo {
unsigned long (*get_hsync_len)(void);
unsigned long (*get_hsync_invperiod)(void);
void (*put_hsync)(void);
void (*wait_hsync)(void);
};

2
include/asm-arm/arch-pxa/spitz.h
View File

@ -156,5 +156,3 @@ extern struct platform_device spitzscoop_device;
extern struct platform_device spitzscoop2_device;
extern struct platform_device spitzssp_device;
extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
extern void spitz_lcd_power(int on, struct fb_var_screeninfo *var);

36
include/asm-arm/arch-pxa/ssp.h
View File

@ -13,10 +13,37 @@
* PXA255 SSP, NSSP
* PXA26x SSP, NSSP, ASSP
* PXA27x SSP1, SSP2, SSP3
* PXA3xx SSP1, SSP2, SSP3, SSP4
*/
#ifndef SSP_H
#define SSP_H
#ifndef __ASM_ARCH_SSP_H
#define __ASM_ARCH_SSP_H
#include <linux/list.h>
enum pxa_ssp_type {
SSP_UNDEFINED = 0,
PXA25x_SSP, /* pxa 210, 250, 255, 26x */
PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
PXA27x_SSP,
};
struct ssp_device {
struct platform_device *pdev;
struct list_head node;
struct clk *clk;
void __iomem *mmio_base;
unsigned long phys_base;
const char *label;
int port_id;
int type;
int use_count;
int irq;
int drcmr_rx;
int drcmr_tx;
};
/*
* SSP initialisation flags
@ -31,6 +58,7 @@ struct ssp_state {
};
struct ssp_dev {
struct ssp_device *ssp;
u32 port;
u32 mode;
u32 flags;
@ -50,4 +78,6 @@ int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags);
int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
void ssp_exit(struct ssp_dev *dev);
#endif
struct ssp_device *ssp_request(int port, const char *label);
void ssp_free(struct ssp_device *);
#endif /* __ASM_ARCH_SSP_H */

14
include/asm-arm/arch-pxa/uncompress.h
View File

@ -9,19 +9,21 @@
* published by the Free Software Foundation.
*/
#define FFUART ((volatile unsigned long *)0x40100000)
#define BTUART ((volatile unsigned long *)0x40200000)
#define STUART ((volatile unsigned long *)0x40700000)
#define HWUART ((volatile unsigned long *)0x41600000)
#include <linux/serial_reg.h>
#include <asm/arch/pxa-regs.h>
#define __REG(x) ((volatile unsigned long *)x)
#define UART FFUART
static inline void putc(char c)
{
while (!(UART[5] & 0x20))
if (!(UART[UART_IER] & IER_UUE))
return;
while (!(UART[UART_LSR] & LSR_TDRQ))
barrier();
UART[0] = c;
UART[UART_TX] = c;
}
/*

9
include/asm-arm/arch-pxa/zylonite.h
View File

@ -3,9 +3,18 @@
#define ZYLONITE_ETH_PHYS 0x14000000
#define EXT_GPIO(x) (128 + (x))
/* the following variables are processor specific and initialized
* by the corresponding zylonite_pxa3xx_init()
*/
struct platform_mmc_slot {
int gpio_cd;
int gpio_wp;
};
extern struct platform_mmc_slot zylonite_mmc_slot[];
extern int gpio_backlight;
extern int gpio_eth_irq;